Multiple cycle implementation (not pipelined)

• Instruction fetch and increment PC

• Decode and read registers; branch address computation

• ALU use for either arithmetic or memory address computation; branch condition and next PC determined

• Memory access

• Store result in register

• With this decomposition, instructions will take either

  • 3 cycles (branch)
  • 4 cycles (everything else except branch and load)
  • 5 cycles (load)

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