Table of Contents
CSE 586 Computer Architecture
Introduction--CSE 586 : Computer Architecture
Course mechanics
Course mechanics (cont’d)
Course mechanics (cont’d)
Class list and e-mail
Course outline (will most certainly be modified; look at web page periodically)
Course outline (cont’d)
Technological improvements
Processor-Memory Performance Gap
Improvements in Processor Speed
Intel x86 Progression
Speed improvement: expose ISA to the compiler/user
Performance evaluation basics
Components of the CPI
Benchmarking
Available benchmark suites
Comparing and summarizing benchmark performance
Normalized execution times
Computer design: Make the common case fast
Instruction Set Architecture
What is not part of the ISA (but interesting!)
CPU-centric operations (arith-logical)
RISC vs. CISC (highly abstracted)
Addressing modes for either load-store or cpu-centric ops
Flow of control – Conditional branches
Unconditional transfers
Registers (visible to the ISA)
A sample of less conventional features
Extensions to basic ISA
From 32b to 64b ISA’s
Instruction Execution Cycle
Multiple cycle implementation (not pipelined)
PPT Slide
Multiple cycle implementation (RTL level)
Multiple cycle impl. (cont’d)
PPT Slide
PPT Slide
PPT Slide
Pipelining
Basic pipeline implementation
PPT Slide
PPT Slide
Hazards
Pipeline speed-up
Example of structural hazard
Data hazards
PPT Slide
Forwarding
PPT Slide
Other data hazards
Forwarding cannot solve all conflicts
PPT Slide
PPT Slide
Compiler solution: pipeline scheduling
|