An Alternative Design

Combine the best of the blocked and interleaved approaches

• Use a standard processor

• Issue instructions from each ready thread, fairly

• When a memory operation makes tread unready, squash any later issued instructions for that thread

IF1

IF1

RF

Ex

DF1

DF1

WB

Ai+2

Ci+1

Bi+1

Ai+1

Ci

Bi

Ai

Pipeline

Blocked

Interleaved

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