Memory and MIMD Computers
It was easier to invision an MIMD machine than to build one ... the problem is memory
We are accustomed to a flat, global memory
Memory Coherency
P1
a: 4 5
P2
a:
P3
a: 4
a: 4 5
P1 reads a into cache
P3 reads a into cache
P1 updates a to 5, wt
-- P3 has stale data --
Writeback is worse
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