P2 Reads a Into Cache
•Dirty bit ON -- home
controller sends reply to Px of the processor
ID of Py, the owner; Px asks Py for data
•Owner Py controller, sets
state to “shared,” forwards data to Px and sends data
to home
•At home, data is updated, dirty bit is turned OFF and the xth presence bit is set ON and yth presence bit remains ON
P1
a:I:4
Controller
P2
a:V:5
Controller
P3
a:V:5
Controller
P0
a:I:4
Controller
Interconnection
Network
Msg: P2 to P1, Read a
Msg: P1 to P2, P3 has
it
Msg: P2 to P3, Read a
Msg: P3 to P2, Here’s a
Msg: P3 to P1, Here’s a