•Px controller awaits ACKs from all those
nodes
•Px controller delivers blk to cache in dirty
state
–Dirty
bit is ON
•Home
notifies owner Py of
Px’s
write request
•Py controller invalidates its blk, sends data
to Px
•Home
clears yth presence bit, turns xth bit ON and dirty bit stays ON
–On
writeback, home stores data, clears both presence and dirty bits