Cache Coherence -- The Problem
•Processors can modify shared locations without other processors being aware of it unless special hardware is added
P1 reads a into its cache
P3 reads a into its cache
P1 changes a to 5 and writes the result through to main memory leaving P3 with stale data
P3 reads a … incoherent
P1
4 5
P2
P3
4
4 5          Memory
a:
a: