Survey of Parallel Computation

Write-through Coherency

•State diagrams show the protocol

PrRd/--

PrWr/BusWr

PrWr/BusWr

V

I

PrRd/BusRd

BusWr/--

States of a cache line

V is valid

I is invalid

Transactions

Reads (Rd) or Writes (Wr)

by processor or bus

Labeling A/B

If A is observed

Then transaction B is

generated