Architecture of an SMP
•A
symmetric multiprocessor (SMP) is a set of processor/cache pairs connected to a
bus
•The
bus is both good news and bad news
•The (memory) bus is a point at which all processors can “see” memory
activity, and can know what is happening
•A bus
is used “serially,” and becomes a “bottleneck,” limiting scaling
P0
Cache
P1
Cache
P2
Cache
P3
Cache
Memory
Bus