CSE591N: Reconfigurable Systems Group, Winter 2010

Date Leader Paper
January 8 Mike Haselman Virtual Configuration Management: A Technique for Partial Runtime Reconfiguration

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January 15 Nate McVicar CGRA Express: Accelerating Execution using Dynamic Operation Fusion
Yongjun Park, Hyunchul Park and Scott Mahlke
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January 22 Abhishek Power-aware RAM mapping for FPGA embedded memory blocks
Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy Proceedings of the 2006 ACM/SIGDA 14th international symposium on FPGA
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January 29 Corey Olson Next-generation Gap
John D McPherson, Nature Methods Supplement, November 2009
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Sense from sequence reads: methods for alignment and assembly
Paul Flicek & Ewan Birney, Nature Methods Supplement, November 2009
local copy
Patternhunter: faster and more sensitive homology search
Bin Ma, John Tromp, and Ming Li, Bioinformatics, Vol 18, no 3 2002, pgs. 440-445
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Plus an additional paper on short reads
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February 5 Ziyuan Zhang Ultra-scale vehicle tracking in low spatial-resolution and low frame-rate overhead video
C. J. Carrano
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February 12 Adam Megacz, UC Berkeley How do you program a clockless, packet-switched FPGA
Fleet is most concisely described as a clockless, packet-switched FPGA. It is the result of "listening to the silicon" and designing a machine that does not attempt to defy the basic laws of physics. Fleet discourages the use of memory as a communication medium. Where all previous transport-triggered architectures have used a bus, Fleet instead uses a switch fabric. Unlike dataflow machines, Fleet eschews expensive tagging and token buffers.
February 19 Brian Van Essen Designing Efficient Sorting Algorithms for Manycore GPUs
Nadathur Satish, Mark Harris, Michael Garland
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February 26 Stephen Friedman

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March 5 Satnam Singh, MSR Cambridge Programming Heterogeneous Systems with Re-targetable Data Parallel Descriptions
Satnam Singh
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March 12 Robin Panda

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