CSE590G: Architecture Seminar, Autumn 2012

Mondays, 12:30-13:30, Room CSE503.

A discussion leader does not need to prepare a full presentation, just 2-3 slides with the summary and discussion points. Focus on what we should all think about!



Here is the list of papers to choose from. Email luisceze and oskin if you have any questions, suggestions or complaints. We can also use the mailing list.
  1. Centip3De: A 3930DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores , ISCA 2012.

  2. Viper: virtual pipelines for enhanced reliability , ISCA 2012.

  3. Scale-out processors, ISCA 2012.

  4. End-to-end sequential consistency , ISCA 2012.

  5. iSwitch: coordinating and optimizing renewable energy powered server clusters , ISCA 2012.

  6. Euripus: A Flexible Unified Hardware Memory Checkpointing Accelerator for Bidirectional-Debugging and Reliability , ISCA 2012.

  7. Can traditional programming bridge the Ninja performance gap for parallel computing applications? , ISCA 2012.

  8. Computational Sprinting , HPCA 2012.

  9. Why On-Chip Cache Coherence Is Here to Stay , CACM 2012.

  10. The Yin and Yang of Power and Performance for Asymmetric Hardware and Managed Software , ISCA 2012.

  11. A Case for Random Shortcut Topologies for HPC Interconnects - ISCA 2012

  12. Side-Channel Vulnerability Factor: A Metric for Measuring Information Leakage - ISCA 2012

  13. Harmony: Collection and Analysis of Parallel Block Vectors - ISCA 2012

DateDiscussion LeaderPaper
Sep 24 Luis/Mark. Organizational Meeting, paper assignments
Oct 1 Hadi Side-Channel Vulnerability Factor: A Metric for Measuring Information Leakage - ISCA 2012
Oct 8 Brandon H. and Paul Can traditional programming bridge the Ninja performance gap for parallel computing applications?
Oct 15 Andre and Adrian Why On-Chip Cache Coherence Is Here to Stay
Oct 22 Brandon M and Marshall Scale-out processors
Oct 29 Mike R. and Thierry Harmony: Collection and Analysis of Parallel Block Vectors - ISCA 2012
Nov 5 Katelin and Irene Euripus: A Flexible Unified Hardware Memory Checkpointing Accelerator for Bidirectional-Debugging and Reliability
Nov 12 Veterans Veterans Day
Nov 19 Robin Centip3De: A 3930DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores
Nov 26 Guest speaker: Eric Chung Reading: (yes there is reading!) here

Title: "CoRAM: An In-Fabric Memory Architecture for Portable and Scalable FPGA-Based Computing"

Abstract: FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despite their promise in both processing performance and efficiency, FPGAs have not yet gained widespread acceptance as mainstream computing devices. A fundamental obstacle to FPGA-based computing today is the FPGA's lack of a common, scalable memory architecture. When developing applications for FPGAs, designers are often directly responsible for crafting the application-specific memory hierarchy that manages and transports data to and from the processing kernels. This infrastructure not only increases design time and effort but will frequently lock a design to a particular FPGA product line, hindering scalability and portability. We propose a new FPGA memory architecture called Connected RAM (CoRAM) to serve as a portable bridge between the distributed computation kernels and the external memory interfaces. In addition to improving performance and efficiency, the CoRAM architecture provides a virtualized memory environment as seen by the hardware kernels to simplify development and to improve an application's portability and scalability.

Bio: Eric Chung is currently a post-doc at Microsoft Research Silicon Valley and received his Ph.D. from Carnegie Mellon in 2011. Eric is broadly interested in the scalability and programmability of future, energy-efficient computer architectures, spanning mobile devices to datacenter-scale computers. His goals are to: (1) identify and expand the role of specialized and programmable logic in future systems, and (2) to enable specialization for the "masses" by improving the architecture, portability, programmability, and debuggability of future specialized hardware. During his time at CMU, Eric led the CoRAM project, an effort to re-think the architecture of FPGAs for computing. He was also the project lead for ProtoFlex, which developed large-scale, full-system multiprocessor emulators using FPGAs.

Dec 3 Colin End-to-end sequential consistency