CSE 590G - ARCHITECTURE LUNCH

Winter 2002

Tuesdays, 12:30, EE1 003

Professor Susan Eggers

We are using a web-based signup tool to pick papers to present in class. If you have problems, please send email to rose@cs.washington.edu and let him know specific details about the problem.

Here are the papers for this quarter:

• Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors, Cintra, Martinez, and Torrellas (ISCA 2000) *
• HLS:  Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs, Oskin, Chong, and Farrens (ISCA 2000)
• Recency-based TLB Preloading, Saulsbury, Dahlgren, and Stenstrom (ISCA 2000)
• Memory Access Scheduling, Rixner, Dally, Kapasi, Mattson, and Owens (ISCA 2000)
• On the Value Locality of Store Instructions, Lepak and Lipasti (ISCA 2000)
• Multiple-Banked Register File Architectures, Cruz, Gonzalez, Valero, and Topham (ISCA 2000)
• Defect Tolerant Molecular Electronics: Algorithms, Architectures and Atoms, Keukes (MICRO-33)
• Silent Stores for Free, Lepak and Lipasti (MICRO-33)
• Efficient Checker Processor Design, Chatterjee, Weaver and Austin (MICRO-33)
• Two-Level Hierarchical Register File Organization for VLIW Processors, Zalamea, Llosa Ayguade and Valero (MICRO-33)
• A Static Power Model for Architects, Butts and Sohi (MICRO-33)
• Register Intedration: A Simple and Efficient Implementation, Roth and Sohi (MICRO-33)
• Slipstream Processors, Purser, Sundaramoorthy and Rotenberg (ASPLOS 2000) and A Study of Slipstream Processors, Purser, Sundaramoorthy and Rotenberg (MICRO-33)
• Relational Profiling": Enabling Thread-Level Parallelism, Heil and Smith (MICRO-33)
• Increasing the Size of Atomic Instruction Blocks Using Control, Patel, Tung, Bose and Crum (MICRO-33)
• Reducing the Wire Delay Penalty through Value Prediction, Parcerisa and Gonzalez (MICRO-33)
• Instruction Distribution Heuristics for Quad-Cluster, Baniasadi and Moshovos (MICRO-33)
• Performance Improvement with Circuit-Level Speculation, Liu and Lu (MICRO-33)
• Predictor-Directed Stream Buffers, Sherwood, Sair and Calder (MICRO-33)
• Hardware Support for Dynamic Activation 0f Compiler-Directed Computation Reuse, Connors, Hunter, Cheng and Hwu (ASPLOS 2000)
• OS and Compiler Considerations in the Design of the IA-64 Architecure, Zahir, Ross, Morris and Hess (ASPLOS 2000)
• Software Profiling for Hot Path Prediction: Less is More, Duesterwald and Bala (ASPLOS 2000)
• Efficient and Flexible Value Sampling, Burrows, Erlingson, Leung, Vandevoorde, Waldspurger, Walker and Weihl (ASPLOS 2000)
• Power Aware Page Allocation, Lebeck, Fan, Zeng and Ellis (ASPLOS 2000)
• System Architecture Directions for Networked Sensors Hill, Szewczyk, Woo, Hollar, Culler and Pister (ASPLOS 2000)
• Architecture and Design of AlphaServer GS320, Gharachorloo, Sharma, Steely and Van Doren (ASPLOS 2000)
• Designing Computer Systems with MEMS-based Storage, Schlosser, Griffin, Nagle and Ganger (ASPLOS 2000)
• Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs, Krintz, Calder, Lee and Zorn (ASPLOS 1998)
• Performance Characterization of a Hardware Mechanism for Dynamic Optimization, Fahs, Bose, Crum, Slechta, Spadini, Tung, Patel and Lumetta (MICRO-34)
• Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real Tim Systems, Rotenberg (MICRO-34)
• A Design Space Evaluation of Grid Processor Architectures, Nagarajan, Sankaralingam, Burger and Keckler (MICRO-34)
• Reducing Power with Dynamic Critical Path Information, Seng, Tune and Tullsen (MICRO-34)
• Direct Addressed Caches for Reduced Power Consumption, Witchel, Larsen, Ananian and Asanovic (MICRO-34)
• Modulo Schedule Buffers, Merten and Hwy (MICRO-34) *
• The Impact of  If-Conversion and Branch prediction on Program Execution on the Intel Itanium Processor, Choi, Knies, Gerke and Ngai (MICRO-34)
• Mapping Reference Code to irregular DSPs within the Retargetable, Optimizing Compiler COGEN(T), Grewal and Wilson (MICRO-34)
• Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications, Hughes, Srinivasan and Adve
• Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, Rajawar and Goodman
• Dynamic Speculative Precomputation, Collins, Tullsen, Wang and Shen (MICRO-34)
• Handling Long-latency Loads in a Simultaneous Multithreading Processor, Tullsen and Brown (MICRO-34)
• Correctly Implementing Value Prediction in Microproccessors that Support Multithreading or Multiprocessing, Martin, Sorin, Cain, Hill and Lipasti (MICRO-34) *
• Asim: A Performance Model Framework, Emer, Ahuja, Binkert, Borch, Espasa, Juan, Klauser, Luk, Manne, Mukherjee, Patil and Wallace (IEEE Computer appearing Feb. 2002)

*  Denotes papers by CSE Faculty Candidates for 2002

Last modified on 01.03.02
S.Gilmore and M. Kadenko