| Date | Presenter | Readings | Notes |
| 9/28 | None | None | Link |
| 10/3 | Ray |
Technology
Cramming more components onto integrated circuits
Semiconductor Industry Association Roadmap Executive Summary
Pages 15-26 (note this is 25-36 in the PDF file). Warning: this can be tough to read if you don't have an EE background, but just do your best and we'll discuss in class. Focus on the higher-level architectural grand challenges.
| Link |
| 10/5 | None | Class canceled | |
| 10/10 | Brandon M |
Pipelining
The Engineering Design of the Stretch Computer
The Microrachitecture of the Pentium 4 Processor
| Link |
| 10/12 | Will |
Scoreboarding & the 6600
Parallel Operation in the Control Data 6600
Design of the 6600 Scoreboard
| Link |
| 10/17 | Hadi |
Register renaming
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
HPSm, a high performance restricted data flow architecture having minimal functionality
|
Link |
| 10/19 | Brandon H |
VLIW
Very Long Instruction Word Architectures & Retrospective
AMD r600(focus around ~ slide 17)
| Link |
| 10/24 | Galen |
Branch Prediction
An Analysys of Correlation and Predictability
A Language for Describing Predictors
Optional but highly recommended:
A Study of Prediction Strategies, Retrospective
Optional: Dynamic Branch Prediction with Perceptrons
|
Link |
| 10/26 | Vincent |
Caching
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
The ZCache: Decoupling Ways from Associativity
Optional: Improving Direct Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,Retrospective
Optional: Lockup Free Instruction Fetch/Prefetch Cache Organization, Retrospective
|
Link |
| 10/31 | Daniel |
Prefetching
Prefetching using Markov Predictors
Predictor Directed Stream-buffers
|
Link |
| 11/2 | Katelin |
Consistency
A Primer on Memory Consistency and Cache CoherencePages 1 - 6 (skim/skip), Pages 9 - 15, Pages 17-32, Pages 37-47 (It looks like a lot, but the font is big)
|
Link |
| 11/7 | |
Coherence
A Primer on Memory Consistency and Cache CoherencePages 99 - 119, Pages 133-137, Pages 139 - 153, Pages 169-170
Optional:Atomic Coherence: Leveraging Nanophotonics to Build Race-Free Cache Coherence Protocols (worth reading the first 2 pages)
|
Link |
| 11/9 | David |
Power
Optimizing Pipeline sfor Power and Performance
(First 2 and a half pages)GreenDroid: Exploring the Next Evolution in Smartphone Application Processors
Dark Silicon and the End of Multicore Scaling
|
Link |
| 11/14 | David |
Bug avoidance
Color Safe: Architectural Support for Debugging and Dynamically Avoiding Multi-variable Atomicity Violations
A Case for an Interleaving Constrained Shared-Memory Multiprocessor
|
| 11/15 | |
Dataflow
A Preliminary Architecture for a Basic Dataflow Architecture
Two Fundamental Limits on Dataflow Multiprocessing
WaveScalar
|
| 11/21 | |
Vector machines
An Analysis of the Cray-1 Computer
|
Link |
| 11/23 --- CANCELED | |
Work on projects / see your family
|
| 11/28 --- CANCELED | |
Work on projects / see your family
|
| 11/30 | |
Emerging technologies
Architectural Implications of Nanoscale Integrated Sensing and Computing
Microcoded Architectures for Ion-Trap Quantum Computers
|
| 12/5 | |
Project presentations #1
|
| 12/7 | |
Project presentations #2
|