CSE 548: Computer Architecture - Winter 2010

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CSE 548 Schedule (Winter 2010) This course schedule will be updated, so check it often. Readings for each week will be posted here as the readings are assigned Date Lecture Topic Reading HW/Project Info January 4th Introduction: Overview, Scope, Project Ideas Moore's Law Lecture 1 Slides Start Thinking about Project Ideas and Groups January 6th Metrics Textbook Chapter 1 Summarizing Performance as a Single Number Lecture 2 Slides Optional: Jacob & Mudge: Notes on Calculating Computer Performance Paper Critique #1 Assigned Schedule your project proposal meeting here January 11th ISAs Part 1 Appendix B Appendix J.2 (RISC ISAs) J.3 (x86) Lecture 3 Slides Optional: A Case for RISC Comments on A Case for RISC Meet to discuss your proposal this week January 13th ISAs Part 2 -- ISAs and Binary Translation Optional: The Transmeta Architecture Meet to discuss your proposal this week January 18th No Class -- Martin Luther King Jr. Day Paper Critique #1 Due January 20th Pipelining Review and Branch Prediction Patt on Branch Prediction Skim Appendix A Textbook Sec 2.1-2.3 Branch Prediction Lecture Slides Pipelining Review Lecture Slides Project Proposals Due January 25th Branch Prediction Part 2 Superscalar Basics Textbook Sec 2.4-2.9 The Alpha 21264 Architecture Sohi on The Microarchitecture of Superscalar Processors Branch Prediction Part 2 Lecture Slides Superscalar Lecture Slides January 27th Instruction Level Parallelism Part 2 Chapter 3 Optional: Limits to Instruction Level Parallelism Smith: Precise Interrupts February 1st Finish-up OoO Scheduling Hardware Multi-Threading Textbook Sec 3.5 Tullsen on Fetch and Issue in an implementable SMT OoO Scheduling Lecture Slides OoO Scheduling Part 2 Lecture Slides Hardware Multithreading Lecture Slides February 3rd The Memory Hierarchy Part 1 Jouppi on Victim Buffers Joseph on Markov Prefetchers Appendix C Chapter 5 Memory Hierarchy Part 1 Lecture Slides Homework #1 Due Homework #2 Assigned February 8th The Memory Hierarchy Part 2 Memory Hierarchy Part 2 Lecture Slides February 10th Virtual Memory Multiprocessor Architecture Part 1 Chapter 4.1 Cray 1 Vector Machine Reading Wavescalar Virtual Memory Lecture Slides Multiprocessor Intro Lecture Slides Part 1 Paper Critique #3 Due February 15th No Class February 17th Guest Lecture: Doug Burger - Phase Change Memory Homework #2 Due February 22nd Luis Out of Town -- No Class February 24th Multiprocessor Architecture Part 2 Stenstrom's Survey of Cache Coherence Schemes for Multiprocessors Lamport - How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs Token Coherence: Decoupling Performance and Correctness The Tera Computer System Cache Coherence Lecture Slides Part 1 March 1st Guest Lecture: Shaz Qadeer - Verifying Cache Coherence Protocols March 3rd Multiprocessor Architecture Part 3 Hill: Multiprocessors Should Support Simple Memory Consistency Models Memory Consistency and event ordering in scalable shared-memory multiprocessors Gharachorloo: Two Techniques to Enhance the Performance of Memory Consistency Models Pai: An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors BulkSC:Bulk Enforcement of Sequential Consistency Cache Coherence Lecture Slides Part 2 Memory Consistency Lecture Slides March 8th Multiprocessor Architecture Part 4 Mellor-Crummey/Scott: Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors Hammond: Transactional Memory Coherence and Consistency DMP: Deterministic Shared-Memory MultiProcessing March 10th Wrap-up, 1k-1M cores :). Master/Slave Speculative Parallelization Core Fusion: Accomodating Software Diversity in Chip Multiprocessors March 19th - 8:30AM - 1:00PM Project Presentations March 21st Final Project Reports Due

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