| Monday 2/5 | Introduction |
| Wednesday 2/7 |
The Engineering Design of the Strech Computer
H&P Appendix A.1 - A.4 (Weighted towards the front/skim the back).
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| Monday 2/12 |
Excerpts from Design of a Computer: the Control Data 6600
Parallel Operation in the Control Data 6600
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| Wednesday 2/14 |
An Efficient Algorithm for Exploiting Multiple Arithmetic Units
HPS, a new microarchitecture: rationale and introduction
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| Wednesday 2/21 |
A Preliminary Architecture for a Basic Data-flow Processor
Two Fundamental Limits on Dataflow Multiprocessing
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| Monday 2/26 |
Very Long Instruction Word Architectures and The ELI-512
Retrospective: The ELI-512
A Design Space Evaluation of Grid Processor Architectures
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| Wednesday 2/28 |
A Study of Branch Prediction Strategies
Retrospective: A Study of Branch Prediction Strategies
H&P Pages 196-215
(If you do not have the H&P book yet) An Analysis of Correlation and Predictability: What Makes Two Level Branch Predictors Work
Optional: A Language for Describing Predictors for Automatic Synthesis
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| Monday 2/2 |
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
Optional: Section in H&P about caches as background depending upon your prior experience
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| Wednesday 2/5 |
The Microarchitecture of SuperScalar Processors
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| Wednesday 2/18 |
Limits of Control Flow on Parallelism
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| Monday 2/23 |
Clock Rate versus IPC
Optimizing Pipelines for Power and Performance
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| Wednesday 2/25 |
Martha
Andrew
Atri & Parag
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| Monday 3/1 |
Charlie & Chris
Tyler & Benson
Lucas & Steve
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| Wednesday 3/3 |
Swapna & Daniel
Abhishek
Alex & Xu
Muthu & Bhushan
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| Monday 3/8 |
Cache Coherence Protocols: Evaluation using a Multiprocessor Simulation Model
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| Wednesday 3/10 |
Read the abstracts from the papers here
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