When compiling algorithms for reconfigurable architectures such as FPGAs or coarse-grained architectures, it is standard to use a place-and-route method to map a given algorithm to the target architecture. However, it may be possible to improve the performance of such an algorithm by allowing the placement method to accurately predict wire congestion. This would allow it to create placements that would permit the router to produce better results. I will present my work in creating a congestion estimation metric for the time-multiplexed Schedule, Place and Route compiler that has been developed here at UW for working with coarse-grained architectures.
Advised by Carl Ebeling
CSE 403
Wednesday
April 4, 2007
4:30 - 5:20 pm