The following questions are optional.
Recall the RISC-V instructions auipc
and jalr
from the base ISA manual.
They are often used as a pair to form a 32-bit PC-relative jump:
Can you use the pair with some imm20/imm12 values to jump to offset 0x7ffffffc
(231 - 4)
on 64-bit RISC-V? Briefly explain why or why not.
Consider the BPF JIT for 64-bit RISC-V for the BPF_ALU | BPF_ADD | BPF_X
instruction (32-bit reg-reg add: DST = (u64)((u32)DST + (u32)SRC)
).
Is emit_zext_32
at line 471 needed? Briefly explain why or why not.