you don’t have to program in assembly a lot in this course
it’s good to have some ideas on what the instructions look like
we will talk about systems-related instructions next week
instruction
I: base integer instructions
a single letter represents an instruction set extension
example extensions:
M: integer multiplication and division
A: atomic memory instructions
F: single-precision floating-point instructions
D: double-precision floating-point instructions
Zicsr: Control and Status Register (CSR) instructions
Zifencei: FENCE.I
G: standard general-purpose ISA, IMAFDZicsr_Zifencei
example: RV64G (i.e., RV64IMAFDZicsr_Zifencei)
you might be interested in more extensions
C: compressed instructions (see
B: bit manipulation (will have a lecture on this)
integer registers: x0-x31
x0/zero
x1/ra (return address)
x2/sp (stack pointer)
x8/s0/fp (frame pointer)
x10-x17/a0-a7: argument registers; return value in a0
which registers are preserved across calls?
example
get assembly: riscv64-unknown-elf-gcc -S -o - -O2 t.c
alternative (raw instructions and bytes):
riscv64-unknown-elf-gcc -c -O2 t.c and riscv64-unknown-elf-objdump -d t.o
how’s the result different (no compressed instructions):
riscv64-unknown-elf-gcc -mabi=lp64 -march=rv64i -O2 -c t.c and riscv64-unknown-elf-objdump -d t.o
the output has two instructions: addi and ret
how to use the RISC-V manual?
you often need to look up in chapter 2, “RV32I Base Integer Instruction Set” (even for RV64I)
Q: why is addi a0,a0,1 encoded as 0x00150513? try to encode this yourself, using chapter 24, “RV32/64G Instruction Set Listings”
Q: what if we change the C code to “x + 5000”? how many instructions does gcc generate? how is this different from x86?
Q: what’s ret? can you find it in the RV32I part of the manual? if not, try chapter 25, “RISC-V Assembly Programmer’s Handbook”