--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Application Note: SoC with Xilinx Virtex
-- File:         xsvPADS.vhd
-- Description:  FPGA Pin Mapping.
-- Version:      FB, 2001jan30
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

-- synopsys translate_off 
library VIRTEX;
-- synopsys translate_on 

entity xsvPads is
	port(
		clk_p89:     in  STD_LOGIC;
		sw1_p174:    in  STD_LOGIC;
		-- Philips PDIUSBP11A USB Transceiver
		rcv_p11:     in  STD_LOGIC;
		vp_p10:      in  STD_LOGIC;
		vm_p9:       in  STD_LOGIC;
		vpo_p13:     out STD_LOGIC;
		fse0_p17:    out STD_LOGIC;
		oe_p12:      out STD_LOGIC;
		suspnd_p176: out STD_LOGIC;
		-- 7-Segment left
		sl0_p177:    out STD_LOGIC;
		sl1_p167:    out STD_LOGIC;
		sl2_p163:    out STD_LOGIC;
		sl3_p156:    out STD_LOGIC;
		sl4_p145:    out STD_LOGIC;
		sl5_p138:    out STD_LOGIC;
		sl6_p134:    out STD_LOGIC;
		-- 7-Segment right
		sr0_p124:    out STD_LOGIC;
		sr1_p132:    out STD_LOGIC;
		sr2_p133:    out STD_LOGIC;
		sr3_p139:    out STD_LOGIC;
		sr4_p141:    out STD_LOGIC;
		sr5_p144:    out STD_LOGIC;
		sr6_p147:    out STD_LOGIC;

		-- SRAM right
		ram_ce:	out STD_LOGIC;
		ram_oe:	out STD_LOGIC;
		ram_we:	out STD_LOGIC;

		d0:	inout STD_LOGIC;
		d1:	inout STD_LOGIC;
		d2:	inout STD_LOGIC;
		d3:	inout STD_LOGIC;
		d4:	inout STD_LOGIC;
		d5:	inout STD_LOGIC;
		d6:	inout STD_LOGIC;
		d7:	inout STD_LOGIC;
		d8:	inout STD_LOGIC;
		d9:	inout STD_LOGIC;
		d10:	inout STD_LOGIC;
		d11:	inout STD_LOGIC;
		d12:	inout STD_LOGIC;
		d13:	inout STD_LOGIC;
		d14:	inout STD_LOGIC;
		d15:	inout STD_LOGIC;
		a0:	out STD_LOGIC;
		a1:	out STD_LOGIC;
		a2:	out STD_LOGIC;
		a3:	out STD_LOGIC;
		a4:	out STD_LOGIC;
		a5:	out STD_LOGIC;
		a6:	out STD_LOGIC;
		a7:	out STD_LOGIC;
		a8:	out STD_LOGIC;
		a9:	out STD_LOGIC;
		a10:	out STD_LOGIC;
		a11:	out STD_LOGIC;
		a12:	out STD_LOGIC;
		a13:	out STD_LOGIC;
		a14:	out STD_LOGIC;
		a15:	out STD_LOGIC;
		a16:	out STD_LOGIC;
		a17:	out STD_LOGIC;
		a18:	out STD_LOGIC	
		);
end xsvPads;

--------------------------------------------------------------------------------
architecture BHV of xsvPads is
	
	component dll_standard
		port (
			CLKIN : in STD_LOGIC;
			RESET : in STD_LOGIC;
			CLK0 : out STD_LOGIC;
			CLK2X : out STD_LOGIC;
			LOCKED : out STD_LOGIC
			);
	end component;

	--component bufg
	--	port (
	--		I : in std_ulogic;
	--		O : out std_ulogic
	--		);
	--end component;
	
	component inv
		port (
			I : in std_ulogic;
			O : out std_ulogic
			);
	end component;
	
	component xsvCore
		port (
			clk48 : in STD_LOGIC;
			clk48x2 : in STD_LOGIC;
			rcv : in STD_LOGIC;
			rst : in STD_LOGIC;
			vm : in STD_LOGIC;
			vp : in STD_LOGIC;
			fse0 : out STD_LOGIC;
			oe : out STD_LOGIC;
			sl : out STD_LOGIC_VECTOR (6 downto 0);
			sr : out STD_LOGIC_VECTOR (6 downto 0);
			suspnd : out STD_LOGIC;
			vpo : out STD_LOGIC;
			ram_ce:		out STD_LOGIC;
			ram_oe:		out STD_LOGIC;
			ram_we:		out STD_LOGIC;
			d:		inout STD_LOGIC_VECTOR (15 downto 0);
			a:		out STD_LOGIC_VECTOR (18 downto 0)
			);
	end component;
	
	signal CLK48 : STD_LOGIC;
	signal CLK48X2: STD_LOGIC;
	signal RST : STD_LOGIC;
	signal SL : STD_LOGIC_VECTOR (6 downto 0);
	signal SR : STD_LOGIC_VECTOR (6 downto 0);
	signal D : STD_LOGIC_VECTOR (15 downto 0);
	signal A : STD_LOGIC_VECTOR (18 downto 0);
	
	-- synopsys translate_off
	for U2 : inv use entity VIRTEX.inv;
	--for U1 : bufg use entity VIRTEX.bufg;
	-- synopsys translate_on
	
begin
	
	Udll : dll_standard
		port map(
		CLKIN => clk_p89,
		RESET => rst,
		CLK0 => CLK48, 
		CLK2X => clk48x2
		);	


	--U1 : bufg
	--port map(
	--	I => clk_p89,
	--	O => clk48
	--	);
	
	U2 : inv
	port map(
		I => sw1_p174,
		O => rst
		);
	
	Ucore : xsvCore
	port map(
		clk48 => clk48,
		clk48x2 => clk48x2,
		fse0 => fse0_p17,
		oe => oe_p12,
		rcv => rcv_p11,
		rst => rst,
		sl => sl,
		sr => sr,
		suspnd => suspnd_p176,
		vm => vm_p9,
		vp => vp_p10,
		vpo => vpo_p13,
		ram_ce => ram_ce,
		ram_oe => ram_oe,
		ram_we => ram_we,
		d => d,
		a => a
		);
	
	sl0_p177 <= sl(0);
	sl1_p167 <= sl(1);
	sl2_p163 <= sl(2);
	sl3_p156 <= sl(3);
	sl4_p145 <= sl(4);
	sl5_p138 <= sl(5);
	sl6_p134 <= sl(6);
	
	sr0_p124 <= sr(0);
	sr1_p132 <= sr(1);
	sr2_p133 <= sr(2);
	sr3_p139 <= sr(3);
	sr4_p141 <= sr(4);
	sr5_p144 <= sr(5);
	sr6_p147 <= sr(6);
					
	d0 <= d(0);
	d1 <= d(1);
	d2 <= d(2);
	d3 <= d(3);
	d4 <= d(4);
	d5 <= d(5);
	d6 <= d(6);
	d7 <= d(7);
	d8 <= d(8);
	d9 <= d(9);
	d10 <= d(10);
	d11 <= d(11);
	d12 <= d(12);
	d13 <= d(13);
	d14 <= d(14);
	d15 <= d(15);
	a0 <= a(0);
	a1 <= a(1);
	a2 <= a(2);
	a3 <= a(3);
	a4 <= a(4);
	a5 <= a(5);
	a6 <= a(6);
	a7 <= a(7);
	a8 <= a(8);
	a9 <= a(9);
	a10 <= a(10);
	a11 <= a(11);
	a12 <= a(12);
	a13 <= a(13);
	a14 <= a(14);
	a15 <= a(15);
	a16 <= a(16);
	a17 <= a(17);
	a18 <= a(18);	
	
end BHV;

--------------------------------------------------------------------------------
-- end of file
