--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Application Note: SoC with Xilinx Virtex
-- File:         xsvCORE.vhd
-- Description:  FPGA Core Logic.
-- Version:      FB, 2001jan24
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity xsvCore is
	port(
		clk48:  in  STD_LOGIC;                     -- 48MHz clock 
		clk48x2: in STD_LOGIC;
		rst:    in  STD_LOGIC;                     -- async reset
		-- Philips PDIUSBP11A USB Transceiver
		rcv:    in  STD_LOGIC;
		vp:     in  STD_LOGIC;
		vm:     in  STD_LOGIC;
		vpo:    out STD_LOGIC;
		fse0:   out STD_LOGIC;
		oe:     out STD_LOGIC;
		suspnd: out STD_LOGIC;
		-- Functional Block
		sl:     out STD_LOGIC_VECTOR (6 downto 0); -- 7-Segment left
		sr:     out STD_LOGIC_VECTOR (6 downto 0);  -- 7-Segment right
		-- SRAM
		ram_ce:		out STD_LOGIC;
		ram_oe:		out STD_LOGIC;
		ram_we:		out STD_LOGIC;
		d:		inout STD_LOGIC_VECTOR (15 downto 0);
		a:		out STD_LOGIC_VECTOR (18 downto 0)
		);
end xsvCore;

--------------------------------------------------------------------------------
architecture BHV of xsvCore is
	component usbMacro
		port (
			clk48 : in STD_LOGIC;
			din : in STD_LOGIC_VECTOR (15 downto 0);
			rst : in STD_LOGIC;
			urx0 : in STD_LOGIC;
			urxd : in STD_LOGIC;
			dout : out STD_LOGIC_VECTOR (15 downto 0);
			utx0 : out STD_LOGIC;
			utxd : out STD_LOGIC;
			utxoe : out STD_LOGIC
			);
	end component;
	component xsvFunc
		port (
			clk48 : in STD_LOGIC;
			clk48x2: in STD_LOGIC;
			dout : in STD_LOGIC_VECTOR (15 downto 0);
			rst : in STD_LOGIC;
			din : out STD_LOGIC_VECTOR (15 downto 0);
			sl : out STD_LOGIC_VECTOR (6 downto 0);
			sr : out STD_LOGIC_VECTOR (6 downto 0);
			urx0 : in STD_LOGIC;
			-- SRAM
			ram_ce:	out STD_LOGIC;
			ram_oe:	out STD_LOGIC;
			ram_we:	out STD_LOGIC;
			d:	inout STD_LOGIC_VECTOR (15 downto 0);
			a:	out STD_LOGIC_VECTOR (18 downto 0)
			);
	end component;
	component xsvPHY
		port (
			rcv : in STD_LOGIC;
			utx0 : in STD_LOGIC;
			utxd : in STD_LOGIC;
			utxoe : in STD_LOGIC;
			vm : in STD_LOGIC;
			vp : in STD_LOGIC;
			fse0 : out STD_LOGIC;
			oe : out STD_LOGIC;
			suspnd : out STD_LOGIC;
			urx0 : out STD_LOGIC;
			urxd : out STD_LOGIC;
			vpo : out STD_LOGIC
			);
	end component;
	
	signal DIN:   STD_LOGIC_VECTOR (15 downto 0);
	signal DOUT:  STD_LOGIC_VECTOR (15 downto 0);
	signal URX0:  STD_LOGIC;
	signal URXD:  STD_LOGIC;
	signal UTX0:  STD_LOGIC;
	signal UTXD:  STD_LOGIC;
	signal UTXOE: STD_LOGIC;
begin
	
	Ufunc : xsvFunc
	port map(
		clk48 => clk48,
		clk48x2 => clk48x2,
		din => din,
		dout => dout,
		rst => rst,
		sl => sl,
		sr => sr,
		urx0 => urx0,
		ram_ce => ram_ce,
		ram_oe => ram_oe,
		ram_we => ram_we,
		d => d,
		a => a
		);
	
	Uphy : xsvPHY
	port map(
		fse0 => fse0,
		oe => oe,
		rcv => rcv,
		suspnd => suspnd,
		urx0 => urx0,
		urxd => urxd,
		utx0 => utx0,
		utxd => utxd,
		utxoe => utxoe,
		vm => vm,
		vp => vp,
		vpo => vpo
		);
	
	Uusb : usbMacro
	port map(
		clk48 => clk48,
		din => din,
		dout => dout,
		rst => rst,
		urx0 => urx0,
		urxd => urxd,
		utx0 => utx0,
		utxd => utxd,
		utxoe => utxoe
		);
	
end BHV;

--------------------------------------------------------------------------------
-- end of file
