## Implement Log

Created on 21:09:38 06/10/04

InputFile = z:/CSE477/xsv300/usb/implement/xie4.ini
Executing C:\Xilinx\bin\nt\ngdbuild.exe -p V300PQ240-6 -sd "z:\CSE477\xsv300\usb\synthesis" -sd "z:\CSE477\xsv300\usb\compile" -sd "z:\CSE477\xsv300\usb\src" -sd "C:\Program Files\Aldec\Active-HDL 6.2\vlib\VIRTEX\compile" -uc "xsvPads.ucf" "xsvPads.edf" "xsvPads.ngd"
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngdbuild G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p V300PQ240-6 -sd z:\CSE477\xsv300\usb\synthesis -sd
z:\CSE477\xsv300\usb\compile -sd z:\CSE477\xsv300\usb\src -sd "C:\Program
Files\Aldec\Active-HDL 6.2\vlib\VIRTEX\compile" -uc xsvPads.ucf xsvPads.edf
xsvPads.ngd
Launcher: Executing edif2ngd "xsvPads.edf" "xsvPads.ngo"
INFO:NgdBuild - Release 6.1i - edif2ngd G.23
INFO:NgdBuild - Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Writing the design to "xsvPads.ngo"...
Reading NGO file "z:/CSE477/xsv300/usb/implement/ver1/rev1/xsvPads.ngo" ...
Reading component libraries for design expansion...
Launcher: "usbMacro.ngo" is up to date.
Loading design module "z:\CSE477\xsv300\usb\implement\ver1\rev1\usbMacro.ngo"...
Annotating constraints to design from file "xsvPads.ucf" ...
Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "clk_p89", used in period specification "TS_clk_p89",
was traced into CLKDLL instance "Udll/dll". The following new TNM groups and
period specifications were generated at the CLKDLL output(s):
CLK90: TS_Udll_CLK2X_dll=PERIOD Udll_CLK2X_dll TS_clk_p89*1.000000 PHASE +
5.208000 nS HIGH 50.000000%
CLK0: TS_Udll_CLK0_dll=PERIOD Udll_CLK0_dll TS_clk_p89*1.000000 HIGH
50.000000%
XdmHelpers:662 - Period specification "TS_Udll_CLK2X_dll" references the
TNM group "Udll_CLK2X_dll", which contains both pads and synchronous
elements. The timing analyzer will ignore the pads for this specification.
You might want to use a qualifier (e.g. "FFS") on the TNM property to remove
the pads from this group.
Checking expanded design ...
NgdBuild:477 - clock net 'clk48x2' has non-clock connections. These
problematic connections include:
pin I2 on block Ucore/Ufunc/sram/un8_doingwrite1 with type LUT3,
pin I2 on block Ucore/Ufunc/sram/un3_doingwrite1 with type LUT3
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 2
Total memory usage is 44760 kilobytes
Writing NGD file "xsvPads.ngd" ...
Writing NGDBUILD log file "xsvPads.bld"...
NGDBUILD done.
Executing C:\Xilinx\bin\nt\map.exe -p V300PQ240-6 -o "map.ncd" "xsvPads.ngd" "xsvPads.pcf"
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Map G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Using target part "v300pq240-6".
Removing unused or disabled logic...
Running cover...
Writing file map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Writing design file "map.ncd"...
Design Summary:
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 780 out of 6,144 12%
Number of 4 input LUTs: 1,514 out of 6,144 24%
Logic Distribution:
Number of occupied Slices: 1,032 out of 3,072 33%
Number of Slices containing only related logic: 1,032 out of 1,032 100%
Number of Slices containing unrelated logic: 0 out of 1,032 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1,692 out of 6,144 27%
Number used as logic: 1,514
Number used as a route-thru: 106
Number used for 32x1 RAMs: 64
(Two LUTs used per 32x1 RAM)
Number used as 16x1 RAMs: 8
Number of bonded IOBs: 59 out of 166 35%
IOB Flip Flops: 1
Number of Tbufs: 40 out of 3,200 1%
Number of Block RAMs: 2 out of 16 12%
Number of GCLKs: 4 out of 4 100%
Number of GCLKIOBs: 1 out of 4 25%
Number of DLLs: 1 out of 4 25%
Number of RPM macros: 2
Total equivalent gate count for design: 66,047
Additional JTAG gate count for IOBs: 2,880
Peak Memory Usage: 79 MB
NOTES:
Related logic is defined as being logic that shares connectivity -
e.g. two LUTs are "related" if they share common inputs.
When assembling slices, Map gives priority to combine logic that
is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin
packing unrelated logic into a slice once 99% of the slices are
occupied through related logic packing.
Note that once logic distribution reaches the 99% level through
related logic packing, this does not mean the device is completely
utilized. Unrelated logic packing will then begin, continuing until
all usable LUTs and FFs are occupied. Depending on your timing
budget, increased levels of unrelated logic packing may adversely
affect the overall timing performance of your design.
Mapping completed.
See MAP report file "map.mrp" for details.
Executing C:\Xilinx\bin\nt\par.exe -w -ol 3 map.ncd "xsvPads.ncd" "xsvPads.pcf"
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Par G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Constraints file: xsvPads.pcf
Loading device database for application Par from file "map.ncd".
"xsvPads" is an NCD, version 2.38, device xcv300, package pq240, speed -6
Loading device for application Par from file 'v300.nph' in environment
C:/Xilinx.
Device speed data version: FINAL 1.123 2003-06-19.
Resolving physical constraints.
Finished resolving physical constraints.
Device utilization summary:
Number of External GCLKIOBs 1 out of 4 25%
Number of External IOBs 59 out of 166 35%
Number of LOCed External IOBs 59 out of 59 100%
Number of BLOCKRAMs 2 out of 16 12%
Number of SLICEs 1032 out of 3072 33%
Number of DLLs 1 out of 4 25%
Number of GCLKs 4 out of 4 100%
Number of TBUFs 40 out of 3200 1%
Overall effort level (-ol): Medium (set by user)
Placer effort level (-pl): Medium (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): Medium (set by user)
Starting initial Timing Analysis. REAL time: 0 secs
Finished initial Timing Analysis. REAL time: 0 secs
Phase 1.1
Phase 1.1 (Checksum:98d92b) REAL time: 0 secs
Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs
Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs
Phase 5.8
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Phase 5.8 (Checksum:b2f308) REAL time: 26 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 26 secs
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 33 secs
Writing design to file xsvPads.ncd.
Total REAL time to Placer completion: 33 secs
Total CPU time to Placer completion: 33 secs
Phase 1: 7393 unrouted; REAL time: 33 secs
Phase 2: 6818 unrouted; REAL time: 39 secs
Phase 3: 1813 unrouted; REAL time: 42 secs
Phase 4: 1813 unrouted; (0) REAL time: 42 secs
Phase 5: 1813 unrouted; (0) REAL time: 43 secs
Phase 6: 1813 unrouted; (0) REAL time: 43 secs
Phase 7: 0 unrouted; (0) REAL time: 45 secs
Total REAL time to Router completion: 46 secs
Total CPU time to Router completion: 45 secs
Generating "par" statistics.
**************************
Generating Clock Report
**************************
+----------------------------+----------+--------+------------+-------------+
| Clock Net | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
| Ucore/Uusb/CLK24 | Global | 229 | 0.250 | 0.506 |
+----------------------------+----------+--------+------------+-------------+
| Ucore/Uusb/CLK12 | Global | 121 | 0.053 | 0.504 |
+----------------------------+----------+--------+------------+-------------+
| clk48x2 | Global | 167 | 0.062 | 0.507 |
+----------------------------+----------+--------+------------+-------------+
| clk48 | Global | 17 | 0.033 | 0.496 |
+----------------------------+----------+--------+------------+-------------+
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
TS_clk_p89 = PERIOD TIMEGRP "clk_p89" 20 | N/A | N/A | N/A
.833 nS HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
TS_Ucore_Uusb_CLK12 = PERIOD TIMEGRP "Uco | 83.333ns | 14.509ns | 5
re/Uusb/CLK12" 83.333 nS HIGH 50.000000 | | |
% | | |
--------------------------------------------------------------------------------
TS_Ucore_Uusb_CLK24 = PERIOD TIMEGRP "Uco | 41.667ns | 27.436ns | 13
re/Uusb/CLK24" 41.667 nS HIGH 50.000000 | | |
% | | |
--------------------------------------------------------------------------------
TS_Udll_CLK2X_dll = PERIOD TIMEGRP "Udll_ | 20.833ns | 15.492ns | 5
CLK2X_dll" TS_clk_p89 / 1.000000 PHASE + | | |
5.208 nS HIGH 50.000 % | | |
--------------------------------------------------------------------------------
TS_Udll_CLK0_dll = PERIOD TIMEGRP "Udll_C | 20.833ns | 11.951ns | 3
LK0_dll" TS_clk_p89 / 1.000000 HIGH 50.0 | | |
00 % | | |
--------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 48 secs
Peak Memory Usage: 93 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Writing design to file xsvPads.ncd.
PAR done.
Executing C:\Xilinx\bin\nt\trce.exe -e 3 "xsvPads.ncd" "xsvPads.pcf" -o "xsvPads.twr"
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Loading device database for application trce.exe from file "xsvPads.ncd".
"xsvPads" is an NCD, version 2.38, device xcv300, package pq240, speed -6
Loading device for application trce.exe from file 'v300.nph' in environment
C:/Xilinx.
--------------------------------------------------------------------------------
Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -e 3 xsvPads.ncd xsvPads.pcf -o xsvPads.twr
Design file: xsvPads.ncd
Physical constraint file: xsvPads.pcf
Device,speed: xcv300,-6 (FINAL 1.123 2003-06-19)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 763302 paths, 0 nets, and 7036 connections
Design statistics:
Minimum period: 27.436ns (Maximum frequency: 36.448MHz)
Analysis completed Thu Jun 10 21:09:13 2004
--------------------------------------------------------------------------------
Generating Report ...
Total time: 3 secs
Executing C:\Xilinx\bin\nt\ngdanno.exe "xsvPads.ncd" map.ngm
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngdanno G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line : C:\Xilinx\bin\nt\ngdanno.exe xsvPads.ncd map.ngm
Anno - Ngdanno and the netlist writers (ngd2ver, ngd2vhdl) are combined
into one new executable: netgen. It is highly recommended that the user
convert their scripts (flows) from ngdanno, ngd2ver and ngd2vhdl as soon as
possible. Please see netgen command line help or refer to netgen user
documentation for further details on the replacement executable.
Writing .nga file "xsvPads.nga"...
Executing C:\Xilinx\bin\nt\ngd2vhdl.exe -w "xsvPads.nga" "z:\CSE477\xsv300\usb\implement\ver1\rev1\time_sim.vhd" -xon true
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngd2vhdl G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
NetListWriters:596 - Ngdanno and the netlist writers (ngd2ver, ngd2vhdl)
are combined into one new executable: netgen. It is highly recommended that
the user convert their scripts (flows) from ngdanno and ngd2vhdl as soon as
possible. Please see netgen command line help or refer to netgen user
documentation for further details on the replacement executable.
Using netgen to create VHDL netlist.
Release 6.1i - netgen G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Loading device database for application netgen from file "xsvPads.ncd".
"xsvPads" is an NCD, version 2.38, device xcv300, package pq240, speed -6
Loading device for application netgen from file 'v300.nph' in environment
C:/Xilinx.
Flattening design ...
Flattening design completed.
Specializing design ...
Specializing design completed.
Preping physical only global signals ...
Preping design's networks ...
Preping design's macros ...
Writing VHDL netlist z:/CSE477/xsv300/usb/implement/ver1/rev1/time_sim.vhd ...
Writing VHDL SDF file z:\CSE477\xsv300\usb\implement\ver1\rev1\time_sim.sdf ...
Total memory usage is 81700 kilobytes
Created ngd2vhdl log file 'ngd2vhdl.log'.
Executing C:\Xilinx\bin\nt\bitgen.exe -w -l "xsvPads.ncd" "xsvPads" "xsvPads.pcf"
z:\CSE477\xsv300\usb\implement\ver1\rev1>set XILINX=C:\Xilinx
z:\CSE477\xsv300\usb\implement\ver1\rev1>set PATH=C:\Xilinx\bin\nt
Release 6.1i - Bitgen G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "xsvPads.ncd".
"xsvPads" is an NCD, version 2.38, device xcv300, package pq240, speed -6
Loading device for application Bitgen from file 'v300.nph' in environment
C:/Xilinx.
Opened constraints file xsvPads.pcf.
Thu Jun 10 21:09:35 2004
Running DRC.
DRC detected 0 errors and 0 warnings.
Saving ll file in "xsvpads.ll".
Creating bit map...
Saving bit stream in "xsvpads.bit".
Bitstream generation is complete.
Implementation ver1->rev1: 0 error(s), 4 warning(s)
Implementation ended with warning(s).