-- Xilinx Vhdl netlist produced by netgen application (version G.23)
-- Command       : -ofmt vhdl -ngm map.ngm -log ngd2vhdl.log -w -xon true xsvPads.ncd z:\CSE477\xsv300\usb\implement\ver1\rev1\time_sim.vhd 
-- Input file    : xsvPads.ncd
-- Output file   : z:/CSE477/xsv300/usb/implement/ver1/rev1/time_sim.vhd
-- Design name   : xsvPads
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : v300pq240-6 (FINAL 1.123 2003-06-19)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity xsvPads is
  port (
    oe_p12 : out STD_LOGIC; 
    vpo_p13 : out STD_LOGIC; 
    fse0_p17 : out STD_LOGIC; 
    d9 : inout STD_LOGIC; 
    d8 : inout STD_LOGIC; 
    d7 : inout STD_LOGIC; 
    d6 : inout STD_LOGIC; 
    d5 : inout STD_LOGIC; 
    d4 : inout STD_LOGIC; 
    sr2_p133 : out STD_LOGIC; 
    d3 : inout STD_LOGIC; 
    d2 : inout STD_LOGIC; 
    d1 : inout STD_LOGIC; 
    d0 : inout STD_LOGIC; 
    sw1_p174 : in STD_LOGIC := 'X'; 
    ram_we : out STD_LOGIC; 
    a9 : out STD_LOGIC; 
    a8 : out STD_LOGIC; 
    sr1_p132 : out STD_LOGIC; 
    a7 : out STD_LOGIC; 
    a6 : out STD_LOGIC; 
    a5 : out STD_LOGIC; 
    a4 : out STD_LOGIC; 
    a3 : out STD_LOGIC; 
    a2 : out STD_LOGIC; 
    a1 : out STD_LOGIC; 
    a0 : out STD_LOGIC; 
    sl6_p134 : out STD_LOGIC; 
    sr0_p124 : out STD_LOGIC; 
    a18 : out STD_LOGIC; 
    a17 : out STD_LOGIC; 
    sl5_p138 : out STD_LOGIC; 
    a16 : out STD_LOGIC; 
    a15 : out STD_LOGIC; 
    a14 : out STD_LOGIC; 
    a13 : out STD_LOGIC; 
    a12 : out STD_LOGIC; 
    a11 : out STD_LOGIC; 
    a10 : out STD_LOGIC; 
    rcv_p11 : in STD_LOGIC := 'X'; 
    sl4_p145 : out STD_LOGIC; 
    sl3_p156 : out STD_LOGIC; 
    ram_oe : out STD_LOGIC; 
    sl2_p163 : out STD_LOGIC; 
    sl1_p167 : out STD_LOGIC; 
    d15 : inout STD_LOGIC; 
    d14 : inout STD_LOGIC; 
    d13 : inout STD_LOGIC; 
    d12 : inout STD_LOGIC; 
    d11 : inout STD_LOGIC; 
    d10 : inout STD_LOGIC; 
    sl0_p177 : out STD_LOGIC; 
    vp_p10 : in STD_LOGIC := 'X'; 
    sr6_p147 : out STD_LOGIC; 
    suspnd_p176 : out STD_LOGIC; 
    sr5_p144 : out STD_LOGIC; 
    vm_p9 : in STD_LOGIC := 'X'; 
    clk_p89 : in STD_LOGIC := 'X'; 
    ram_ce : out STD_LOGIC; 
    sr4_p141 : out STD_LOGIC; 
    sr3_p139 : out STD_LOGIC 
  );
end xsvPads;

architecture STRUCTURE of xsvPads is
  signal Ucore_Uusb_CLK24 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N34 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N37 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N36 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RWR : STD_LOGIC; 
  signal Ucore_Uusb_syn5161 : STD_LOGIC; 
  signal Ucore_Uusb_syn27130 : STD_LOGIC; 
  signal Ucore_Uusb_syn6514 : STD_LOGIC; 
  signal Ucore_Uusb_syn6519 : STD_LOGIC; 
  signal Ucore_Uusb_syn6524 : STD_LOGIC; 
  signal Ucore_Uusb_syn6527 : STD_LOGIC; 
  signal Ucore_Uusb_CLK12 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_NET71 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_sel : STD_LOGIC; 
  signal Ucore_Uusb_syn5667 : STD_LOGIC; 
  signal Ucore_Uusb_syn26073 : STD_LOGIC; 
  signal Ucore_Uusb_syn5686 : STD_LOGIC; 
  signal Ucore_Uusb_syn5293 : STD_LOGIC; 
  signal Ucore_Uusb_syn20278 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C597 : STD_LOGIC; 
  signal Ucore_Uusb_syn26076 : STD_LOGIC; 
  signal Ucore_Uusb_syn26088 : STD_LOGIC; 
  signal Ucore_Uusb_syn5725 : STD_LOGIC; 
  signal Ucore_Uusb_syn23094 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C675 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C419_C0_C4 : STD_LOGIC; 
  signal Ucore_Uusb_syn20137 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C689 : STD_LOGIC; 
  signal Ucore_Uusb_syn26072 : STD_LOGIC; 
  signal Ucore_Uusb_syn20364 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C461_C0 : STD_LOGIC; 
  signal vpo_p13_c : STD_LOGIC; 
  signal a0_c : STD_LOGIC; 
  signal a1_c : STD_LOGIC; 
  signal a2_c : STD_LOGIC; 
  signal a3_c : STD_LOGIC; 
  signal a4_c : STD_LOGIC; 
  signal a5_c : STD_LOGIC; 
  signal a6_c : STD_LOGIC; 
  signal d0_in : STD_LOGIC; 
  signal un3_doingwrite1_n : STD_LOGIC; 
  signal a7_c : STD_LOGIC; 
  signal d1_in : STD_LOGIC; 
  signal a8_c : STD_LOGIC; 
  signal d2_in : STD_LOGIC; 
  signal a9_c : STD_LOGIC; 
  signal d3_in : STD_LOGIC; 
  signal d4_in : STD_LOGIC; 
  signal d5_in : STD_LOGIC; 
  signal d6_in : STD_LOGIC; 
  signal d7_in : STD_LOGIC; 
  signal d8_in : STD_LOGIC; 
  signal d9_in : STD_LOGIC; 
  signal vm_p9_c : STD_LOGIC; 
  signal sw1_p174_c : STD_LOGIC; 
  signal Ucore_utxoe : STD_LOGIC; 
  signal a10_c : STD_LOGIC; 
  signal a11_c : STD_LOGIC; 
  signal a12_c : STD_LOGIC; 
  signal a13_c : STD_LOGIC; 
  signal a14_c : STD_LOGIC; 
  signal a15_c : STD_LOGIC; 
  signal a16_c : STD_LOGIC; 
  signal a17_c : STD_LOGIC; 
  signal a18_c : STD_LOGIC; 
  signal d10_in : STD_LOGIC; 
  signal d11_in : STD_LOGIC; 
  signal d12_in : STD_LOGIC; 
  signal d13_in : STD_LOGIC; 
  signal d14_in : STD_LOGIC; 
  signal d15_in : STD_LOGIC; 
  signal fse0_p17_c : STD_LOGIC; 
  signal clk48x2 : STD_LOGIC; 
  signal ram_oe_c : STD_LOGIC; 
  signal ram_we_c : STD_LOGIC; 
  signal Udll_CLKIN_w : STD_LOGIC; 
  signal vp_p10_c : STD_LOGIC; 
  signal Ucore_Uusb_CLK24I : STD_LOGIC; 
  signal Ucore_Uusb_CLK12I : STD_LOGIC; 
  signal Udll_CLK2X_dll : STD_LOGIC; 
  signal Udll_CLK0_dll : STD_LOGIC; 
  signal clk48 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N37 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N31 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N33 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_0_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_6_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N101 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N12 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_3_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N18 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_2_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_7_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N36 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_5_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N48 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N42 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_1_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_9_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_8_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_7_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_6_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_5_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_4_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_3_Q : STD_LOGIC; 
  signal Ucore_Ufunc_sram_doWrite : STD_LOGIC; 
  signal Ucore_Ufunc_sram_N_231_i : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_rep1 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_8_0 : STD_LOGIC; 
  signal g0_L1_n : STD_LOGIC; 
  signal g0_L3_n : STD_LOGIC; 
  signal g0_L5_O : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_fast : STD_LOGIC; 
  signal Ucore_Ufunc_N_249 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCWR : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N54 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N60 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N66 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N72 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N78 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N84 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N90 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N96 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N12 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N18 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N36 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N42 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N48 : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_13_n : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C4_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C6_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C8_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C10_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C12_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C14_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C16_C1_O : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_55_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_59 : STD_LOGIC; 
  signal Ucore_Ufunc_N_11_0 : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_28_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_19 : STD_LOGIC; 
  signal Ucore_Ufunc_N_35 : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_19_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0 : STD_LOGIC; 
  signal Ucore_Ufunc_N_43 : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36 : STD_LOGIC; 
  signal Ucore_Ufunc_N_51 : STD_LOGIC; 
  signal Ucore_Ufunc_N_3_0 : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_7_i_i_a2_n : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_28_O : STD_LOGIC; 
  signal I_10_n_0 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C3_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N373 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C5_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N374 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N375 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C7_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N376 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N377 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C9_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N378 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N379 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C11_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N380 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N381 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C13_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N382 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N383 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C15_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N384 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N385 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N386 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N387 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite29 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_16_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_28_O : STD_LOGIC; 
  signal I_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_218 : STD_LOGIC; 
  signal Ucore_Ufunc_N_217_i : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_15_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_17_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_13_n : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_14_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data37_8_16_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_240_1 : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_3 : STD_LOGIC; 
  signal Ucore_Ufunc_N_259_i : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_16_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_1_O : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_13_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_15_n : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_N1358 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_28_O : STD_LOGIC; 
  signal I_10_n_1 : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_13_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_15_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_3_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_2_rep1 : STD_LOGIC; 
  signal Ucore_Ufunc_ie : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_15_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_17_O : STD_LOGIC; 
  signal Ucore_Ufunc_doneflag : STD_LOGIC; 
  signal g0_0_a3_13_O : STD_LOGIC; 
  signal g0_0_a3_16 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_2_8 : STD_LOGIC; 
  signal Ucore_Ufunc_N_45 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data42_4_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data38 : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data40 : STD_LOGIC; 
  signal Ucore_Ufunc_ram_canRead : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data42_4_1 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_46 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_47 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_48 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_49 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_15_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_50 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_16_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_0 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_17_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_52 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_53 : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_1_21_1 : STD_LOGIC; 
  signal N_125 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1_9 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1_10 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1_11 : STD_LOGIC; 
  signal g0_1_L3_O : STD_LOGIC; 
  signal g0_1_L5_n : STD_LOGIC; 
  signal g0_1_1 : STD_LOGIC; 
  signal g0_3_a2_13_O : STD_LOGIC; 
  signal g0_0_7 : STD_LOGIC; 
  signal g0_2_4 : STD_LOGIC; 
  signal g0_2_5 : STD_LOGIC; 
  signal g0_2_8_O : STD_LOGIC; 
  signal g0_3_5_0 : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_483 : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_fast_0_Q : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_fast_2_Q : STD_LOGIC; 
  signal Ucore_Ufunc_sram_doWrite_u_L1_O : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_3_Q : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_1_18_n : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_ss0_O : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_1_21_O : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite34 : STD_LOGIC; 
  signal Ucore_Ufunc_un37_nextresize_state : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_m2_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_220 : STD_LOGIC; 
  signal Ucore_Ufunc_un37_nextresize_statelto9_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_39 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_40 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_41 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_42 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_43_0 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_44 : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_x_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_243 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data26_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_O : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data37 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data37_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_1_Q : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un41_nextaddr_offset_i_a2_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_60 : STD_LOGIC; 
  signal Ucore_Ufunc_N_501 : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_0 : STD_LOGIC; 
  signal Ucore_Ufunc_N_62 : STD_LOGIC; 
  signal Ucore_Ufunc_N_61 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9 : STD_LOGIC; 
  signal Ucore_Ufunc_N_395_i : STD_LOGIC; 
  signal Ucore_Ufunc_N_438 : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_0_rep1 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N137 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C2_N12 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C763 : STD_LOGIC; 
  signal Ucore_Uusb_syn7015 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C755 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C2_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6 : STD_LOGIC; 
  signal Ucore_Uusb_syn6629 : STD_LOGIC; 
  signal Ucore_Uusb_N1552 : STD_LOGIC; 
  signal Ucore_Uusb_syn8070 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2 : STD_LOGIC; 
  signal Ucore_Uusb_syn24588 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3 : STD_LOGIC; 
  signal Ucore_Uusb_N1554 : STD_LOGIC; 
  signal Ucore_Ufunc_N_429 : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doRead : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6 : STD_LOGIC; 
  signal Ucore_urx0 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C2_N26 : STD_LOGIC; 
  signal Ucore_Uusb_syn5306 : STD_LOGIC; 
  signal Ucore_Uusb_syn27599 : STD_LOGIC; 
  signal Ucore_Uusb_N1483 : STD_LOGIC; 
  signal Ucore_Uusb_syn6831 : STD_LOGIC; 
  signal Ucore_Ufunc_N_253_i : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N15 : STD_LOGIC; 
  signal Ucore_Uusb_N1468 : STD_LOGIC; 
  signal Ucore_Uusb_syn6653 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1471 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_in_en : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C30_N9 : STD_LOGIC; 
  signal Ucore_Uusb_syn28150 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1039 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1024 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C27_N9 : STD_LOGIC; 
  signal Ucore_Uusb_syn5544 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2 : STD_LOGIC; 
  signal Ucore_Uusb_NET136 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C328 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET2015 : STD_LOGIC; 
  signal Ucore_Uusb_N1494 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N28 : STD_LOGIC; 
  signal Ucore_Uusb_syn28560 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_N103 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_N26 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C568 : STD_LOGIC; 
  signal Ucore_Uusb_syn7362 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2646 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C588 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C570 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C654 : STD_LOGIC; 
  signal Ucore_Uusb_syn7532 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C656 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C580 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C0_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C640 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399 : STD_LOGIC; 
  signal Ucore_Uusb_syn7460 : STD_LOGIC; 
  signal Ucore_Uusb_syn7274 : STD_LOGIC; 
  signal Ucore_Uusb_syn7285 : STD_LOGIC; 
  signal Ucore_Uusb_syn7088 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C765 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C667 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1049 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N529 : STD_LOGIC; 
  signal Ucore_Uusb_syn5344 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474 : STD_LOGIC; 
  signal Ucore_Uusb_syn27968 : STD_LOGIC; 
  signal Ucore_Uusb_N1524 : STD_LOGIC; 
  signal Ucore_Uusb_syn8063 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_NET230 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N84 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s : STD_LOGIC; 
  signal Ucore_Uusb_syn5302 : STD_LOGIC; 
  signal Ucore_Uusb_syn5326 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N133 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C780 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_in_trac : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_n_1032 : STD_LOGIC; 
  signal Ucore_Uusb_syn7341 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1523 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_N53 : STD_LOGIC; 
  signal Ucore_Uusb_syn27986 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C556 : STD_LOGIC; 
  signal Ucore_Uusb_syn27992 : STD_LOGIC; 
  signal Ucore_Uusb_N1512 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C751 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N29 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_relf : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C0_N5 : STD_LOGIC; 
  signal Ucore_Uusb_syn5327 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N485 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C1_N6 : STD_LOGIC; 
  signal Ucore_Uusb_syn28312 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_7_i : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_4 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C355 : STD_LOGIC; 
  signal Ucore_Uusb_syn5165 : STD_LOGIC; 
  signal Ucore_Uusb_syn7855 : STD_LOGIC; 
  signal Ucore_Uusb_syn28154 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_S_62_cell0 : STD_LOGIC; 
  signal Ucore_Uusb_syn7877 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C348 : STD_LOGIC; 
  signal Ucore_Uusb_syn8079 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C485 : STD_LOGIC; 
  signal Ucore_Uusb_syn28046 : STD_LOGIC; 
  signal Ucore_Uusb_syn28047 : STD_LOGIC; 
  signal Ucore_Uusb_syn6493 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2257 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2171 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_0_Q : STD_LOGIC; 
  signal Ucore_Uusb_syn27841 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C642 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C598 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_Q : STD_LOGIC; 
  signal Ucore_Uusb_syn27876 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C705 : STD_LOGIC; 
  signal Ucore_Uusb_syn5249 : STD_LOGIC; 
  signal Ucore_Uusb_syn7473 : STD_LOGIC; 
  signal Ucore_Uusb_N1495 : STD_LOGIC; 
  signal Ucore_Uusb_syn5318 : STD_LOGIC; 
  signal Ucore_Uusb_syn6904 : STD_LOGIC; 
  signal Ucore_Uusb_syn6926 : STD_LOGIC; 
  signal Ucore_Uusb_syn20438 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146 : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite35 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C39_N30 : STD_LOGIC; 
  signal Ucore_Uusb_N1467 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9 : STD_LOGIC; 
  signal Ucore_Uusb_syn8481 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519 : STD_LOGIC; 
  signal Ucore_Uusb_syn7896 : STD_LOGIC; 
  signal Ucore_Uusb_syn5458 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C12_N6 : STD_LOGIC; 
  signal Ucore_Uusb_syn8288 : STD_LOGIC; 
  signal Ucore_Uusb_syn5329 : STD_LOGIC; 
  signal Ucore_Uusb_syn8421 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C584 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C758 : STD_LOGIC; 
  signal Ucore_Uusb_syn7335 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C564 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C806 : STD_LOGIC; 
  signal Ucore_Uusb_syn5312 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C650 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C597 : STD_LOGIC; 
  signal Ucore_Uusb_syn27978 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C13_N18 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C363 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6 : STD_LOGIC; 
  signal Ucore_Uusb_syn8037 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C171 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C2_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2517 : STD_LOGIC; 
  signal Ucore_Uusb_syn7410 : STD_LOGIC; 
  signal Ucore_Uusb_syn7414 : STD_LOGIC; 
  signal Ucore_Uusb_syn27928 : STD_LOGIC; 
  signal Ucore_Uusb_syn27929 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1437 : STD_LOGIC; 
  signal Ucore_Uusb_syn7499 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C664 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C578 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1351 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C9_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1469 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_stall_en : STD_LOGIC; 
  signal Ucore_Ufunc_sram_doRead : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N791 : STD_LOGIC; 
  signal Ucore_Uusb_syn28235 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2 : STD_LOGIC; 
  signal Ucore_Uusb_syn7394 : STD_LOGIC; 
  signal Ucore_Uusb_N1541 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186 : STD_LOGIC; 
  signal Ucore_Uusb_syn6626 : STD_LOGIC; 
  signal Ucore_Uusb_N1511 : STD_LOGIC; 
  signal Ucore_Uusb_syn5332 : STD_LOGIC; 
  signal Ucore_Uusb_syn6779 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_T2WR : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C487 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C157 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C492 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_N210 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_N219 : STD_LOGIC; 
  signal Ucore_Uusb_syn6704 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_txen1 : STD_LOGIC; 
  signal Ucore_Uusb_NET3345 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C29_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1454 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C33_N15 : STD_LOGIC; 
  signal Ucore_Uusb_syn6739 : STD_LOGIC; 
  signal Ucore_Uusb_syn5315 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_setup_en : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_out_en : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1221 : STD_LOGIC; 
  signal Ucore_Uusb_syn7441 : STD_LOGIC; 
  signal Ucore_Uusb_syn5290 : STD_LOGIC; 
  signal Ucore_Uusb_syn5300 : STD_LOGIC; 
  signal Ucore_Uusb_syn7321 : STD_LOGIC; 
  signal Ucore_Uusb_syn7304 : STD_LOGIC; 
  signal Ucore_Uusb_syn5163 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C576 : STD_LOGIC; 
  signal Ucore_Uusb_syn27960 : STD_LOGIC; 
  signal Ucore_Ufunc_N_64 : STD_LOGIC; 
  signal Ucore_Ufunc_N_63 : STD_LOGIC; 
  signal Ucore_Ufunc_N_66 : STD_LOGIC; 
  signal Ucore_Ufunc_N_65 : STD_LOGIC; 
  signal Ucore_Ufunc_N_56 : STD_LOGIC; 
  signal Ucore_Ufunc_N_68 : STD_LOGIC; 
  signal Ucore_Ufunc_N_67 : STD_LOGIC; 
  signal Ucore_Ufunc_N_58 : STD_LOGIC; 
  signal Ucore_Ufunc_N_57 : STD_LOGIC; 
  signal Ucore_Ufunc_N_69 : STD_LOGIC; 
  signal g0_3_a2_7 : STD_LOGIC; 
  signal g0_0_a3_10 : STD_LOGIC; 
  signal g0_1_4 : STD_LOGIC; 
  signal g0_0_a3_11 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_ram_writeAddr_1_11 : STD_LOGIC; 
  signal g0_0_a3_12 : STD_LOGIC; 
  signal g0_0_a3_17 : STD_LOGIC; 
  signal Ucore_Ufunc_N_520 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_sn_m2_i_a2_1 : STD_LOGIC; 
  signal Ucore_Ufunc_N_567 : STD_LOGIC; 
  signal Ucore_Uusb_syn28585 : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_6_Q : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_7_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BWR : STD_LOGIC; 
  signal Ucore_Ufunc_dwire6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_T1WR : STD_LOGIC; 
  signal g0_3_a2_14 : STD_LOGIC; 
  signal g0_1_5 : STD_LOGIC; 
  signal g0_3_a2_18 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_ram_writeAddr_1 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05 : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_0_Q : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_1_Q : STD_LOGIC; 
  signal g0_1_L1_n : STD_LOGIC; 
  signal g0_0_a2_x_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_7 : STD_LOGIC; 
  signal g4_0 : STD_LOGIC; 
  signal N_112 : STD_LOGIC; 
  signal g4_1 : STD_LOGIC; 
  signal Ucore_Ufunc_N_244 : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data39 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_2_0_a2_n : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C25_N12 : STD_LOGIC; 
  signal Ucore_Ufunc_N_246_i : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data37_1 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_3 : STD_LOGIC; 
  signal Ucore_dout_7_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_P0WR : STD_LOGIC; 
  signal Ucore_Ufunc_N_500 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ADXWR : STD_LOGIC; 
  signal Ucore_Uusb_N1514 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_12_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12 : STD_LOGIC; 
  signal Ucore_Ufunc_N_70 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid : STD_LOGIC; 
  signal g0_1_a2_2 : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_14_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_13_Q : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_15_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_N89 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_INI : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite_1 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C0_N39 : STD_LOGIC; 
  signal Ucore_dout_15_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13 : STD_LOGIC; 
  signal Ucore_Uusb_syn7870 : STD_LOGIC; 
  signal Ucore_Uusb_syn5330 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1035 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1461 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2 : STD_LOGIC; 
  signal Ucore_Uusb_syn28128 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C603_C6 : STD_LOGIC; 
  signal Ucore_Uusb_syn5299 : STD_LOGIC; 
  signal Ucore_Uusb_syn5311 : STD_LOGIC; 
  signal Ucore_Uusb_syn7544 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_cell6 : STD_LOGIC; 
  signal Ucore_Uusb_syn28141 : STD_LOGIC; 
  signal Ucore_Uusb_syn28144 : STD_LOGIC; 
  signal Ucore_Uusb_syn7799 : STD_LOGIC; 
  signal Ucore_Uusb_syn28142 : STD_LOGIC; 
  signal Ucore_Uusb_syn28143 : STD_LOGIC; 
  signal Ucore_Uusb_syn28147 : STD_LOGIC; 
  signal Ucore_Uusb_syn7852 : STD_LOGIC; 
  signal Ucore_Uusb_syn28193 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C483 : STD_LOGIC; 
  signal Ucore_Uusb_syn28034 : STD_LOGIC; 
  signal Ucore_Uusb_syn28106 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C458 : STD_LOGIC; 
  signal Ucore_Uusb_syn7677 : STD_LOGIC; 
  signal Ucore_Uusb_syn28078 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_N59 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N311 : STD_LOGIC; 
  signal Ucore_Uusb_syn7527 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C286 : STD_LOGIC; 
  signal Ucore_Uusb_syn7848 : STD_LOGIC; 
  signal Ucore_Uusb_syn5328 : STD_LOGIC; 
  signal Ucore_Uusb_syn5313 : STD_LOGIC; 
  signal Ucore_Uusb_syn27750 : STD_LOGIC; 
  signal Ucore_Uusb_syn27752 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C477 : STD_LOGIC; 
  signal Ucore_Uusb_syn7197 : STD_LOGIC; 
  signal Ucore_Uusb_syn7724 : STD_LOGIC; 
  signal Ucore_Uusb_syn7727 : STD_LOGIC; 
  signal Ucore_Uusb_syn7842 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C479 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C491 : STD_LOGIC; 
  signal Ucore_Uusb_syn5336 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_Q : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C464 : STD_LOGIC; 
  signal Ucore_Uusb_syn28107 : STD_LOGIC; 
  signal Ucore_Uusb_syn28090 : STD_LOGIC; 
  signal Ucore_Uusb_syn28089 : STD_LOGIC; 
  signal Ucore_Uusb_syn28093 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C792 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C788 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C784 : STD_LOGIC; 
  signal Ucore_Uusb_syn27751 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C558 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C746 : STD_LOGIC; 
  signal Ucore_Uusb_syn5295 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C700 : STD_LOGIC; 
  signal Ucore_Uusb_syn28033 : STD_LOGIC; 
  signal Ucore_Uusb_syn28023 : STD_LOGIC; 
  signal Ucore_Uusb_syn6430 : STD_LOGIC; 
  signal Ucore_Uusb_syn28104 : STD_LOGIC; 
  signal Ucore_Uusb_syn28105 : STD_LOGIC; 
  signal Ucore_Uusb_syn28110 : STD_LOGIC; 
  signal Ucore_Uusb_syn5162 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C481 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C456 : STD_LOGIC; 
  signal Ucore_Uusb_syn28077 : STD_LOGIC; 
  signal Ucore_Uusb_syn28061 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C617 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C611 : STD_LOGIC; 
  signal Ucore_Uusb_syn6992 : STD_LOGIC; 
  signal Ucore_Uusb_syn23519 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C661 : STD_LOGIC; 
  signal Ucore_Uusb_syn6920 : STD_LOGIC; 
  signal Ucore_Uusb_syn27530 : STD_LOGIC; 
  signal Ucore_Uusb_syn6989 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C454 : STD_LOGIC; 
  signal Ucore_Uusb_syn21091 : STD_LOGIC; 
  signal Ucore_Uusb_syn27684 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C702 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1697 : STD_LOGIC; 
  signal Ucore_Uusb_syn5301 : STD_LOGIC; 
  signal Ucore_Uusb_syn28016 : STD_LOGIC; 
  signal Ucore_Uusb_syn7706 : STD_LOGIC; 
  signal Ucore_Uusb_syn28080 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C690 : STD_LOGIC; 
  signal Ucore_Uusb_syn6957 : STD_LOGIC; 
  signal Ucore_Uusb_syn5903 : STD_LOGIC; 
  signal Ucore_Uusb_syn6991 : STD_LOGIC; 
  signal Ucore_Uusb_syn5317 : STD_LOGIC; 
  signal Ucore_Uusb_syn6472 : STD_LOGIC; 
  signal Ucore_Uusb_syn27544 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RAWR : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C690 : STD_LOGIC; 
  signal Ucore_Uusb_syn7264 : STD_LOGIC; 
  signal Ucore_Uusb_syn28036 : STD_LOGIC; 
  signal Ucore_Uusb_syn7709 : STD_LOGIC; 
  signal Ucore_Uusb_syn28060 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C569 : STD_LOGIC; 
  signal Ucore_Uusb_syn6532 : STD_LOGIC; 
  signal Ucore_Uusb_syn5945 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1827 : STD_LOGIC; 
  signal Ucore_Uusb_syn27833 : STD_LOGIC; 
  signal Ucore_Uusb_syn5539 : STD_LOGIC; 
  signal Ucore_Uusb_syn28062 : STD_LOGIC; 
  signal Ucore_Uusb_syn6964 : STD_LOGIC; 
  signal Ucore_Uusb_syn23977 : STD_LOGIC; 
  signal Ucore_Uusb_syn27492 : STD_LOGIC; 
  signal Ucore_Uusb_syn27498 : STD_LOGIC; 
  signal Ucore_Uusb_syn27499 : STD_LOGIC; 
  signal Ucore_Uusb_syn6004 : STD_LOGIC; 
  signal Ucore_Uusb_syn26082 : STD_LOGIC; 
  signal Ucore_Uusb_syn27516 : STD_LOGIC; 
  signal Ucore_Uusb_syn6981 : STD_LOGIC; 
  signal Ucore_Uusb_syn27695 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3 : STD_LOGIC; 
  signal Ucore_Uusb_syn5333 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1465 : STD_LOGIC; 
  signal Ucore_Uusb_syn27276 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C458_C13 : STD_LOGIC; 
  signal Ucore_Uusb_syn5736 : STD_LOGIC; 
  signal Ucore_Uusb_syn6023 : STD_LOGIC; 
  signal Ucore_Uusb_syn27676 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C555 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C165 : STD_LOGIC; 
  signal Ucore_Uusb_syn7644 : STD_LOGIC; 
  signal Ucore_Uusb_syn28005 : STD_LOGIC; 
  signal Ucore_Uusb_syn6694 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1450 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C9_C0 : STD_LOGIC; 
  signal Ucore_Uusb_syn6707 : STD_LOGIC; 
  signal Ucore_Uusb_syn27291 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C603 : STD_LOGIC; 
  signal Ucore_Uusb_syn5913 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C683 : STD_LOGIC; 
  signal Ucore_Uusb_syn20390 : STD_LOGIC; 
  signal Ucore_Uusb_syn27532 : STD_LOGIC; 
  signal Ucore_Uusb_syn5325 : STD_LOGIC; 
  signal Ucore_Uusb_syn28024 : STD_LOGIC; 
  signal Ucore_Uusb_syn26085 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C433_C2_C5 : STD_LOGIC; 
  signal Ucore_Uusb_syn20388 : STD_LOGIC; 
  signal Ucore_Uusb_syn5624 : STD_LOGIC; 
  signal Ucore_Uusb_syn6505 : STD_LOGIC; 
  signal Ucore_Uusb_syn27122 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C929 : STD_LOGIC; 
  signal Ucore_Uusb_syn27327 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C11_C1 : STD_LOGIC; 
  signal Ucore_Uusb_syn27650 : STD_LOGIC; 
  signal Ucore_Uusb_syn27651 : STD_LOGIC; 
  signal Ucore_Uusb_syn27958 : STD_LOGIC; 
  signal Ucore_Uusb_syn6498 : STD_LOGIC; 
  signal Ucore_Uusb_syn27110 : STD_LOGIC; 
  signal Ucore_Uusb_syn27103 : STD_LOGIC; 
  signal Ucore_Uusb_syn27104 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C939 : STD_LOGIC; 
  signal Ucore_Uusb_syn27248 : STD_LOGIC; 
  signal Ucore_Uusb_syn27249 : STD_LOGIC; 
  signal Ucore_Uusb_syn5164 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C681 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C677 : STD_LOGIC; 
  signal Ucore_Uusb_syn6908 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C665 : STD_LOGIC; 
  signal Ucore_Uusb_syn27466 : STD_LOGIC; 
  signal Ucore_Uusb_syn5323 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C325 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C319 : STD_LOGIC; 
  signal Ucore_Uusb_syn26906 : STD_LOGIC; 
  signal Ucore_Uusb_syn27855 : STD_LOGIC; 
  signal Ucore_Uusb_syn6951 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C756 : STD_LOGIC; 
  signal Ucore_Uusb_syn27984 : STD_LOGIC; 
  signal Ucore_Uusb_syn27054 : STD_LOGIC; 
  signal Ucore_Uusb_syn23576 : STD_LOGIC; 
  signal Ucore_Uusb_syn27056 : STD_LOGIC; 
  signal Ucore_Uusb_syn6437 : STD_LOGIC; 
  signal Ucore_Uusb_syn27093 : STD_LOGIC; 
  signal Ucore_Uusb_syn27094 : STD_LOGIC; 
  signal Ucore_Uusb_syn6451 : STD_LOGIC; 
  signal Ucore_Uusb_syn6464 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_S_1_cell0 : STD_LOGIC; 
  signal Ucore_Uusb_syn6691 : STD_LOGIC; 
  signal Ucore_Uusb_syn27278 : STD_LOGIC; 
  signal Ucore_Uusb_syn20436 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C331 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C327 : STD_LOGIC; 
  signal Ucore_Uusb_syn26593 : STD_LOGIC; 
  signal Ucore_Uusb_syn26858 : STD_LOGIC; 
  signal Ucore_Uusb_syn23598 : STD_LOGIC; 
  signal Ucore_Uusb_syn23597 : STD_LOGIC; 
  signal Ucore_Uusb_syn27072 : STD_LOGIC; 
  signal Ucore_Uusb_syn27073 : STD_LOGIC; 
  signal Ucore_Uusb_syn27074 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C541 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C167 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3 : STD_LOGIC; 
  signal Ucore_Uusb_syn5303 : STD_LOGIC; 
  signal Ucore_Uusb_syn27277 : STD_LOGIC; 
  signal Ucore_Uusb_syn6805 : STD_LOGIC; 
  signal Ucore_Uusb_syn27389 : STD_LOGIC; 
  signal Ucore_Uusb_syn6821 : STD_LOGIC; 
  signal Ucore_Uusb_syn6824 : STD_LOGIC; 
  signal Ucore_Uusb_syn5316 : STD_LOGIC; 
  signal Ucore_Uusb_syn27935 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C339 : STD_LOGIC; 
  signal Ucore_Uusb_syn5952 : STD_LOGIC; 
  signal Ucore_Uusb_syn26597 : STD_LOGIC; 
  signal Ucore_Uusb_syn26862 : STD_LOGIC; 
  signal Ucore_Uusb_syn6690 : STD_LOGIC; 
  signal Ucore_Uusb_syn27279 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C424_C0_C3 : STD_LOGIC; 
  signal Ucore_Uusb_syn23120 : STD_LOGIC; 
  signal Ucore_Uusb_syn23109 : STD_LOGIC; 
  signal Ucore_Uusb_syn26461 : STD_LOGIC; 
  signal Ucore_Uusb_syn6264 : STD_LOGIC; 
  signal Ucore_Uusb_syn6225 : STD_LOGIC; 
  signal Ucore_Uusb_syn26592 : STD_LOGIC; 
  signal Ucore_Uusb_syn26857 : STD_LOGIC; 
  signal Ucore_Uusb_syn6478 : STD_LOGIC; 
  signal Ucore_Uusb_syn6444 : STD_LOGIC; 
  signal Ucore_Uusb_N1471 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C743 : STD_LOGIC; 
  signal Ucore_Uusb_syn5751 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C317 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C313 : STD_LOGIC; 
  signal Ucore_Uusb_syn26591 : STD_LOGIC; 
  signal Ucore_Uusb_syn26856 : STD_LOGIC; 
  signal Ucore_Uusb_syn27084 : STD_LOGIC; 
  signal Ucore_Uusb_syn27086 : STD_LOGIC; 
  signal Ucore_Uusb_N1540 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid : STD_LOGIC; 
  signal Ucore_Uusb_syn6673 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C67_C3_C1 : STD_LOGIC; 
  signal Ucore_Uusb_syn27944 : STD_LOGIC; 
  signal Ucore_Uusb_syn26646 : STD_LOGIC; 
  signal Ucore_Uusb_syn26807 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C351 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C345 : STD_LOGIC; 
  signal Ucore_Uusb_syn26595 : STD_LOGIC; 
  signal Ucore_Uusb_syn27013 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C191 : STD_LOGIC; 
  signal Ucore_Uusb_syn23575 : STD_LOGIC; 
  signal Ucore_Uusb_syn27328 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C220 : STD_LOGIC; 
  signal Ucore_Uusb_syn26645 : STD_LOGIC; 
  signal Ucore_Uusb_syn26806 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPWR : STD_LOGIC; 
  signal Ucore_Uusb_syn26808 : STD_LOGIC; 
  signal Ucore_Uusb_syn26809 : STD_LOGIC; 
  signal Ucore_Uusb_syn26810 : STD_LOGIC; 
  signal Ucore_Uusb_syn26811 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C353 : STD_LOGIC; 
  signal Ucore_Uusb_syn6177 : STD_LOGIC; 
  signal Ucore_Uusb_syn26816 : STD_LOGIC; 
  signal Ucore_Uusb_syn26817 : STD_LOGIC; 
  signal Ucore_Uusb_syn5237 : STD_LOGIC; 
  signal Ucore_Uusb_syn6213 : STD_LOGIC; 
  signal Ucore_Uusb_syn26838 : STD_LOGIC; 
  signal Ucore_Uusb_syn26839 : STD_LOGIC; 
  signal Ucore_Uusb_syn26841 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C341 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C333 : STD_LOGIC; 
  signal Ucore_Uusb_syn26594 : STD_LOGIC; 
  signal Ucore_Uusb_syn27012 : STD_LOGIC; 
  signal Ucore_Uusb_syn5645 : STD_LOGIC; 
  signal Ucore_Uusb_syn27376 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C153 : STD_LOGIC; 
  signal Ucore_Uusb_syn6817 : STD_LOGIC; 
  signal Ucore_Uusb_syn6818 : STD_LOGIC; 
  signal Ucore_Uusb_syn27574 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C69 : STD_LOGIC; 
  signal Ucore_Uusb_syn27619 : STD_LOGIC; 
  signal Ucore_Uusb_syn5632 : STD_LOGIC; 
  signal Ucore_Uusb_syn5653 : STD_LOGIC; 
  signal Ucore_Uusb_syn5659 : STD_LOGIC; 
  signal Ucore_Uusb_syn5664 : STD_LOGIC; 
  signal Ucore_Uusb_syn26909 : STD_LOGIC; 
  signal Ucore_Uusb_syn26775 : STD_LOGIC; 
  signal Ucore_Uusb_syn5190 : STD_LOGIC; 
  signal Ucore_Uusb_syn6158 : STD_LOGIC; 
  signal Ucore_Uusb_syn6162 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C359 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C357 : STD_LOGIC; 
  signal Ucore_Uusb_syn26650 : STD_LOGIC; 
  signal Ucore_Uusb_syn26932 : STD_LOGIC; 
  signal Ucore_Uusb_syn26933 : STD_LOGIC; 
  signal Ucore_Uusb_syn26937 : STD_LOGIC; 
  signal Ucore_Uusb_syn26988 : STD_LOGIC; 
  signal Ucore_Uusb_syn20067 : STD_LOGIC; 
  signal Ucore_Uusb_syn26948 : STD_LOGIC; 
  signal Ucore_Uusb_syn26989 : STD_LOGIC; 
  signal Ucore_Uusb_syn26992 : STD_LOGIC; 
  signal Ucore_Uusb_syn26647 : STD_LOGIC; 
  signal Ucore_Uusb_syn27011 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uactrl_C214 : STD_LOGIC; 
  signal Ucore_Uusb_syn7732 : STD_LOGIC; 
  signal Ucore_Uusb_syn5304 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304 : STD_LOGIC; 
  signal Ucore_Uusb_syn28539 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C447_C18 : STD_LOGIC; 
  signal Ucore_Uusb_syn5697 : STD_LOGIC; 
  signal Ucore_Uusb_syn23133 : STD_LOGIC; 
  signal Ucore_Uusb_syn6176 : STD_LOGIC; 
  signal Ucore_Uusb_syn6007 : STD_LOGIC; 
  signal Ucore_Uusb_syn26789 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C424_C2_C5 : STD_LOGIC; 
  signal Ucore_Uusb_syn26791 : STD_LOGIC; 
  signal Ucore_Uusb_syn26649 : STD_LOGIC; 
  signal Ucore_Uusb_syn6607 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C0_N64 : STD_LOGIC; 
  signal Ucore_Uusb_syn5309 : STD_LOGIC; 
  signal Ucore_Uusb_syn5349 : STD_LOGIC; 
  signal Ucore_Uusb_syn8374 : STD_LOGIC; 
  signal Ucore_Uusb_syn24763 : STD_LOGIC; 
  signal Ucore_Uusb_syn28608 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C593 : STD_LOGIC; 
  signal Ucore_Uusb_syn26313 : STD_LOGIC; 
  signal Ucore_Uusb_syn26697 : STD_LOGIC; 
  signal Ucore_Uusb_syn26753 : STD_LOGIC; 
  signal Ucore_Uusb_syn26648 : STD_LOGIC; 
  signal Ucore_Uusb_syn5310 : STD_LOGIC; 
  signal Ucore_Uusb_syn26824 : STD_LOGIC; 
  signal Ucore_Uusb_syn26837 : STD_LOGIC; 
  signal Ucore_Uusb_syn27009 : STD_LOGIC; 
  signal Ucore_Uusb_syn27010 : STD_LOGIC; 
  signal Ucore_Uusb_syn27015 : STD_LOGIC; 
  signal Ucore_Uusb_syn27019 : STD_LOGIC; 
  signal Ucore_Uusb_syn23827 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C1_C0 : STD_LOGIC; 
  signal Ucore_Uusb_syn26908 : STD_LOGIC; 
  signal Ucore_Uusb_syn26696 : STD_LOGIC; 
  signal Ucore_Uusb_syn26752 : STD_LOGIC; 
  signal Ucore_Uusb_syn5322 : STD_LOGIC; 
  signal Ucore_Uusb_syn5341 : STD_LOGIC; 
  signal Ucore_Uusb_syn26785 : STD_LOGIC; 
  signal Ucore_Uusb_syn26786 : STD_LOGIC; 
  signal Ucore_Uusb_syn26788 : STD_LOGIC; 
  signal Ucore_Uusb_syn26698 : STD_LOGIC; 
  signal Ucore_Uusb_syn5342 : STD_LOGIC; 
  signal Ucore_Uusb_syn6329 : STD_LOGIC; 
  signal Ucore_Uusb_syn26960 : STD_LOGIC; 
  signal Ucore_Uusb_syn26961 : STD_LOGIC; 
  signal Ucore_Uusb_syn5324 : STD_LOGIC; 
  signal Ucore_Uusb_syn23522 : STD_LOGIC; 
  signal Ucore_Uusb_syn26137 : STD_LOGIC; 
  signal Ucore_Uusb_syn28530 : STD_LOGIC; 
  signal Ucore_Uusb_syn28531 : STD_LOGIC; 
  signal Ucore_Uusb_syn28551 : STD_LOGIC; 
  signal Ucore_Uusb_syn26290 : STD_LOGIC; 
  signal Ucore_Uusb_syn5608 : STD_LOGIC; 
  signal Ucore_Uusb_syn26580 : STD_LOGIC; 
  signal Ucore_Uusb_syn26582 : STD_LOGIC; 
  signal Ucore_Uusb_syn26911 : STD_LOGIC; 
  signal Ucore_Uusb_syn23149 : STD_LOGIC; 
  signal Ucore_Uusb_syn26737 : STD_LOGIC; 
  signal Ucore_Uusb_syn6127 : STD_LOGIC; 
  signal Ucore_Uusb_syn26762 : STD_LOGIC; 
  signal Ucore_Uusb_syn26763 : STD_LOGIC; 
  signal Ucore_Uusb_syn26754 : STD_LOGIC; 
  signal Ucore_Uusb_syn26755 : STD_LOGIC; 
  signal Ucore_Uusb_syn26756 : STD_LOGIC; 
  signal Ucore_Uusb_syn26757 : STD_LOGIC; 
  signal Ucore_Uusb_syn6110 : STD_LOGIC; 
  signal Ucore_Uusb_syn26979 : STD_LOGIC; 
  signal Ucore_Uusb_syn26980 : STD_LOGIC; 
  signal Ucore_Uusb_syn6350 : STD_LOGIC; 
  signal Ucore_Uusb_syn6106 : STD_LOGIC; 
  signal Ucore_Uusb_syn26931 : STD_LOGIC; 
  signal Ucore_Uusb_syn26934 : STD_LOGIC; 
  signal Ucore_Uusb_syn27014 : STD_LOGIC; 
  signal Ucore_Uusb_syn20073 : STD_LOGIC; 
  signal Ucore_Uusb_syn27020 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C921 : STD_LOGIC; 
  signal Ucore_Uusb_syn6513 : STD_LOGIC; 
  signal Ucore_Uusb_syn28298 : STD_LOGIC; 
  signal Ucore_Uusb_syn28299 : STD_LOGIC; 
  signal Ucore_Uusb_syn8001 : STD_LOGIC; 
  signal Ucore_Uusb_syn8006 : STD_LOGIC; 
  signal Ucore_Uusb_syn27319 : STD_LOGIC; 
  signal Ucore_Uusb_syn28318 : STD_LOGIC; 
  signal Ucore_Uusb_syn28319 : STD_LOGIC; 
  signal Ucore_Uusb_syn8044 : STD_LOGIC; 
  signal Ucore_Uusb_syn28337 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_cell17 : STD_LOGIC; 
  signal Ucore_Uusb_syn26700 : STD_LOGIC; 
  signal Ucore_Uusb_syn5340 : STD_LOGIC; 
  signal Ucore_Uusb_syn26578 : STD_LOGIC; 
  signal Ucore_Uusb_syn26812 : STD_LOGIC; 
  signal Ucore_Uusb_syn5191 : STD_LOGIC; 
  signal Ucore_Uusb_syn27151 : STD_LOGIC; 
  signal Ucore_Uusb_syn28418 : STD_LOGIC; 
  signal Ucore_Uusb_syn28463 : STD_LOGIC; 
  signal Ucore_Uusb_syn28465 : STD_LOGIC; 
  signal Ucore_Uusb_syn8331 : STD_LOGIC; 
  signal Ucore_Uusb_syn5652 : STD_LOGIC; 
  signal Ucore_Uusb_syn26306 : STD_LOGIC; 
  signal Ucore_Uusb_syn5292 : STD_LOGIC; 
  signal Ucore_Uusb_syn5917 : STD_LOGIC; 
  signal Ucore_Uusb_syn6012 : STD_LOGIC; 
  signal Ucore_Uusb_syn26579 : STD_LOGIC; 
  signal Ucore_Uusb_syn26907 : STD_LOGIC; 
  signal Ucore_Uusb_syn26651 : STD_LOGIC; 
  signal Ucore_Uusb_syn26702 : STD_LOGIC; 
  signal Ucore_Uusb_syn26735 : STD_LOGIC; 
  signal Ucore_Uusb_syn26736 : STD_LOGIC; 
  signal Ucore_Uusb_syn26699 : STD_LOGIC; 
  signal Ucore_Uusb_syn6352 : STD_LOGIC; 
  signal Ucore_Uusb_syn6341 : STD_LOGIC; 
  signal Ucore_Uusb_syn26990 : STD_LOGIC; 
  signal Ucore_Uusb_syn26994 : STD_LOGIC; 
  signal Ucore_Uusb_syn6431 : STD_LOGIC; 
  signal Ucore_Uusb_syn28436 : STD_LOGIC; 
  signal Ucore_Uusb_syn28438 : STD_LOGIC; 
  signal Ucore_Uusb_syn28427 : STD_LOGIC; 
  signal Ucore_Uusb_syn28641 : STD_LOGIC; 
  signal Ucore_Uusb_syn5320 : STD_LOGIC; 
  signal Ucore_Uusb_syn26285 : STD_LOGIC; 
  signal Ucore_Uusb_syn6360 : STD_LOGIC; 
  signal Ucore_Uusb_syn26968 : STD_LOGIC; 
  signal Ucore_Uusb_syn26969 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_N484 : STD_LOGIC; 
  signal Ucore_Uusb_syn28409 : STD_LOGIC; 
  signal Ucore_Uusb_syn28314 : STD_LOGIC; 
  signal Ucore_Uusb_syn28445 : STD_LOGIC; 
  signal Ucore_Uusb_syn5618 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C461 : STD_LOGIC; 
  signal Ucore_Uusb_syn5338 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C589 : STD_LOGIC; 
  signal Ucore_Uusb_syn6257 : STD_LOGIC; 
  signal Ucore_Uusb_syn6260 : STD_LOGIC; 
  signal Ucore_Uusb_syn26707 : STD_LOGIC; 
  signal Ucore_Uusb_syn6075 : STD_LOGIC; 
  signal Ucore_Uusb_syn26708 : STD_LOGIC; 
  signal Ucore_Uusb_syn26733 : STD_LOGIC; 
  signal Ucore_Uusb_syn26719 : STD_LOGIC; 
  signal Ucore_Uusb_syn26734 : STD_LOGIC; 
  signal Ucore_Uusb_syn27134 : STD_LOGIC; 
  signal Ucore_Uusb_syn28454 : STD_LOGIC; 
  signal Ucore_Uusb_syn28456 : STD_LOGIC; 
  signal Ucore_Uusb_syn26236 : STD_LOGIC; 
  signal Ucore_Uusb_syn27118 : STD_LOGIC; 
  signal Ucore_Uusb_syn5298 : STD_LOGIC; 
  signal Ucore_Uusb_syn5910 : STD_LOGIC; 
  signal Ucore_Uusb_syn6265 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C458_C8 : STD_LOGIC; 
  signal Ucore_Uusb_syn6073 : STD_LOGIC; 
  signal Ucore_Uusb_syn26758 : STD_LOGIC; 
  signal Ucore_Uusb_syn20065 : STD_LOGIC; 
  signal Ucore_Uusb_syn26953 : STD_LOGIC; 
  signal Ucore_Uusb_syn26947 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292 : STD_LOGIC; 
  signal Ucore_Uusb_syn28306 : STD_LOGIC; 
  signal Ucore_Uusb_syn8011 : STD_LOGIC; 
  signal Ucore_Uusb_syn28429 : STD_LOGIC; 
  signal Ucore_Uusb_syn26135 : STD_LOGIC; 
  signal Ucore_Uusb_syn28612 : STD_LOGIC; 
  signal Ucore_Uusb_syn8470 : STD_LOGIC; 
  signal Ucore_Uusb_syn8513 : STD_LOGIC; 
  signal Ucore_Uusb_syn26270 : STD_LOGIC; 
  signal Ucore_Uusb_syn22957 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C585 : STD_LOGIC; 
  signal Ucore_Uusb_syn6059 : STD_LOGIC; 
  signal Ucore_Uusb_syn26679 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C433_C0_C3 : STD_LOGIC; 
  signal Ucore_Uusb_syn26681 : STD_LOGIC; 
  signal Ucore_Uusb_syn26701 : STD_LOGIC; 
  signal Ucore_Uusb_syn26732 : STD_LOGIC; 
  signal Ucore_Uusb_syn26078 : STD_LOGIC; 
  signal Ucore_Uusb_syn27132 : STD_LOGIC; 
  signal Ucore_Uusb_syn8277 : STD_LOGIC; 
  signal Ucore_Uusb_syn8279 : STD_LOGIC; 
  signal Ucore_Uusb_syn5294 : STD_LOGIC; 
  signal Ucore_Uusb_syn5868 : STD_LOGIC; 
  signal Ucore_Uusb_syn5869 : STD_LOGIC; 
  signal Ucore_Uusb_syn26575 : STD_LOGIC; 
  signal Ucore_Uusb_syn23229 : STD_LOGIC; 
  signal Ucore_Uusb_syn26905 : STD_LOGIC; 
  signal Ucore_Uusb_syn26916 : STD_LOGIC; 
  signal Ucore_Uusb_syn26890 : STD_LOGIC; 
  signal Ucore_Uusb_syn26917 : STD_LOGIC; 
  signal Ucore_Uusb_syn28447 : STD_LOGIC; 
  signal Ucore_Uusb_syn26572 : STD_LOGIC; 
  signal Ucore_Uusb_syn26677 : STD_LOGIC; 
  signal Ucore_Uusb_syn26678 : STD_LOGIC; 
  signal Ucore_Uusb_syn7962 : STD_LOGIC; 
  signal Ucore_Uusb_syn28420 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302 : STD_LOGIC; 
  signal Ucore_Uusb_syn5717 : STD_LOGIC; 
  signal Ucore_Uusb_syn26581 : STD_LOGIC; 
  signal Ucore_Uusb_syn6018 : STD_LOGIC; 
  signal Ucore_Uusb_syn20383 : STD_LOGIC; 
  signal Ucore_Uusb_syn26629 : STD_LOGIC; 
  signal Ucore_Uusb_syn6024 : STD_LOGIC; 
  signal Ucore_Uusb_syn26657 : STD_LOGIC; 
  signal Ucore_Uusb_syn26656 : STD_LOGIC; 
  signal Ucore_Uusb_syn26867 : STD_LOGIC; 
  signal Ucore_Uusb_syn26868 : STD_LOGIC; 
  signal Ucore_Uusb_syn26887 : STD_LOGIC; 
  signal Ucore_Uusb_syn26889 : STD_LOGIC; 
  signal Ucore_Uusb_syn26910 : STD_LOGIC; 
  signal Ucore_Uusb_syn28242 : STD_LOGIC; 
  signal Ucore_Uusb_syn26569 : STD_LOGIC; 
  signal Ucore_Uusb_syn5750 : STD_LOGIC; 
  signal Ucore_Uusb_syn6071 : STD_LOGIC; 
  signal Ucore_Uusb_syn28617 : STD_LOGIC; 
  signal Ucore_Uusb_syn28620 : STD_LOGIC; 
  signal Ucore_Uusb_syn26628 : STD_LOGIC; 
  signal Ucore_Uusb_syn26859 : STD_LOGIC; 
  signal Ucore_Uusb_syn26860 : STD_LOGIC; 
  signal Ucore_Uusb_syn26861 : STD_LOGIC; 
  signal Ucore_Uusb_syn26885 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C17_N11 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290 : STD_LOGIC; 
  signal Ucore_Uusb_syn5279 : STD_LOGIC; 
  signal Ucore_Uusb_syn7925 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C23_N9 : STD_LOGIC; 
  signal Ucore_Uusb_syn28411 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C447_C8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C447_C13 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2 : STD_LOGIC; 
  signal Ucore_Uusb_syn8151 : STD_LOGIC; 
  signal Ucore_Uusb_syn26602 : STD_LOGIC; 
  signal Ucore_Uusb_syn26603 : STD_LOGIC; 
  signal Ucore_Uusb_syn7912 : STD_LOGIC; 
  signal Ucore_Uusb_syn28225 : STD_LOGIC; 
  signal Ucore_Uusb_syn28243 : STD_LOGIC; 
  signal Ucore_Uusb_syn26596 : STD_LOGIC; 
  signal Ucore_Uusb_syn7900 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite27_i_a2_2 : STD_LOGIC; 
  signal Ucore_Uusb_syn8521 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_2_0_a2_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_4 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_5 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_6 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1367 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1365 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_7_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1264 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1262 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_6_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1161 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1159 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_5_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1058 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N1056 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_4_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N955 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N953 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_3_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N852 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N850 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_2_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N749 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N747 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_1_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N646 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N644 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RO_0_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_syn27130_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27130_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N36_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N37_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RWR_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RWR_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_7_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_7_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_5_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_5_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_3_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_3_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS63_1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_syn29043 : STD_LOGIC; 
  signal BLK0_2_XORF : STD_LOGIC; 
  signal BLK0_2_GROM : STD_LOGIC; 
  signal BLK0_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_syn29039 : STD_LOGIC; 
  signal BLK1_2_XORF : STD_LOGIC; 
  signal BLK1_2_GROM : STD_LOGIC; 
  signal BLK1_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_syn29047 : STD_LOGIC; 
  signal BLK2_2_XORF : STD_LOGIC; 
  signal BLK2_2_GROM : STD_LOGIC; 
  signal BLK2_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_syn29045 : STD_LOGIC; 
  signal BLK3_2_XORF : STD_LOGIC; 
  signal BLK3_2_GROM : STD_LOGIC; 
  signal BLK3_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_syn29041 : STD_LOGIC; 
  signal BLK4_2_XORF : STD_LOGIC; 
  signal BLK4_2_GROM : STD_LOGIC; 
  signal BLK4_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_syn29037 : STD_LOGIC; 
  signal BLK5_2_XORF : STD_LOGIC; 
  signal BLK5_2_GROM : STD_LOGIC; 
  signal BLK5_2_CYINIT : STD_LOGIC; 
  signal sr0_p124_ENABLE : STD_LOGIC; 
  signal sr0_p124_TORGTS : STD_LOGIC; 
  signal sr0_p124_OUTMUX : STD_LOGIC; 
  signal sr1_p132_ENABLE : STD_LOGIC; 
  signal sr1_p132_TORGTS : STD_LOGIC; 
  signal sr1_p132_OUTMUX : STD_LOGIC; 
  signal vpo_p13_ENABLE : STD_LOGIC; 
  signal vpo_p13_TORGTS : STD_LOGIC; 
  signal vpo_p13_OUTMUX : STD_LOGIC; 
  signal sr2_p133_ENABLE : STD_LOGIC; 
  signal sr2_p133_TORGTS : STD_LOGIC; 
  signal sr2_p133_OUTMUX : STD_LOGIC; 
  signal sr3_p139_ENABLE : STD_LOGIC; 
  signal sr3_p139_TORGTS : STD_LOGIC; 
  signal sr3_p139_OUTMUX : STD_LOGIC; 
  signal sr4_p141_ENABLE : STD_LOGIC; 
  signal sr4_p141_TORGTS : STD_LOGIC; 
  signal sr4_p141_OUTMUX : STD_LOGIC; 
  signal a0_ENABLE : STD_LOGIC; 
  signal a0_TORGTS : STD_LOGIC; 
  signal a0_OUTMUX : STD_LOGIC; 
  signal a1_ENABLE : STD_LOGIC; 
  signal a1_TORGTS : STD_LOGIC; 
  signal a1_OUTMUX : STD_LOGIC; 
  signal a2_ENABLE : STD_LOGIC; 
  signal a2_TORGTS : STD_LOGIC; 
  signal a2_OUTMUX : STD_LOGIC; 
  signal a3_ENABLE : STD_LOGIC; 
  signal a3_TORGTS : STD_LOGIC; 
  signal a3_OUTMUX : STD_LOGIC; 
  signal a4_ENABLE : STD_LOGIC; 
  signal a4_TORGTS : STD_LOGIC; 
  signal a4_OUTMUX : STD_LOGIC; 
  signal sr5_p144_ENABLE : STD_LOGIC; 
  signal sr5_p144_TORGTS : STD_LOGIC; 
  signal sr5_p144_OUTMUX : STD_LOGIC; 
  signal a5_ENABLE : STD_LOGIC; 
  signal a5_TORGTS : STD_LOGIC; 
  signal a5_OUTMUX : STD_LOGIC; 
  signal a6_ENABLE : STD_LOGIC; 
  signal a6_TORGTS : STD_LOGIC; 
  signal a6_OUTMUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GWEAND : STD_LOGIC; 
  signal d0_ENABLE : STD_LOGIC; 
  signal d0_TORGTS : STD_LOGIC; 
  signal d0_OUTMUX : STD_LOGIC; 
  signal d0_IBUF : STD_LOGIC; 
  signal a7_ENABLE : STD_LOGIC; 
  signal a7_TORGTS : STD_LOGIC; 
  signal a7_OUTMUX : STD_LOGIC; 
  signal d1_ENABLE : STD_LOGIC; 
  signal d1_TORGTS : STD_LOGIC; 
  signal d1_OUTMUX : STD_LOGIC; 
  signal d1_IBUF : STD_LOGIC; 
  signal a8_ENABLE : STD_LOGIC; 
  signal a8_TORGTS : STD_LOGIC; 
  signal a8_OUTMUX : STD_LOGIC; 
  signal d2_ENABLE : STD_LOGIC; 
  signal d2_TORGTS : STD_LOGIC; 
  signal d2_OUTMUX : STD_LOGIC; 
  signal d2_IBUF : STD_LOGIC; 
  signal a9_ENABLE : STD_LOGIC; 
  signal a9_TORGTS : STD_LOGIC; 
  signal a9_OUTMUX : STD_LOGIC; 
  signal d3_ENABLE : STD_LOGIC; 
  signal d3_TORGTS : STD_LOGIC; 
  signal d3_OUTMUX : STD_LOGIC; 
  signal d3_IBUF : STD_LOGIC; 
  signal d4_ENABLE : STD_LOGIC; 
  signal d4_TORGTS : STD_LOGIC; 
  signal d4_OUTMUX : STD_LOGIC; 
  signal d4_IBUF : STD_LOGIC; 
  signal d5_ENABLE : STD_LOGIC; 
  signal d5_TORGTS : STD_LOGIC; 
  signal d5_OUTMUX : STD_LOGIC; 
  signal d5_IBUF : STD_LOGIC; 
  signal d6_ENABLE : STD_LOGIC; 
  signal d6_TORGTS : STD_LOGIC; 
  signal d6_OUTMUX : STD_LOGIC; 
  signal d6_IBUF : STD_LOGIC; 
  signal d7_ENABLE : STD_LOGIC; 
  signal d7_TORGTS : STD_LOGIC; 
  signal d7_OUTMUX : STD_LOGIC; 
  signal d7_IBUF : STD_LOGIC; 
  signal d8_ENABLE : STD_LOGIC; 
  signal d8_TORGTS : STD_LOGIC; 
  signal d8_OUTMUX : STD_LOGIC; 
  signal d8_IBUF : STD_LOGIC; 
  signal d9_ENABLE : STD_LOGIC; 
  signal d9_TORGTS : STD_LOGIC; 
  signal d9_OUTMUX : STD_LOGIC; 
  signal d9_IBUF : STD_LOGIC; 
  signal sr6_p147_ENABLE : STD_LOGIC; 
  signal sr6_p147_TORGTS : STD_LOGIC; 
  signal sr6_p147_OUTMUX : STD_LOGIC; 
  signal suspnd_p176_ENABLE : STD_LOGIC; 
  signal suspnd_p176_TORGTS : STD_LOGIC; 
  signal suspnd_p176_OUTMUX : STD_LOGIC; 
  signal suspnd_p176_LOGIC_ZERO : STD_LOGIC; 
  signal vm_p9_IBUF : STD_LOGIC; 
  signal sw1_p174_IBUF : STD_LOGIC; 
  signal oe_p12_ENABLE : STD_LOGIC; 
  signal oe_p12_TORGTS : STD_LOGIC; 
  signal oe_p12_OUTMUX : STD_LOGIC; 
  signal oe_p12_ODNOT : STD_LOGIC; 
  signal a10_ENABLE : STD_LOGIC; 
  signal a10_TORGTS : STD_LOGIC; 
  signal a10_OUTMUX : STD_LOGIC; 
  signal a11_ENABLE : STD_LOGIC; 
  signal a11_TORGTS : STD_LOGIC; 
  signal a11_OUTMUX : STD_LOGIC; 
  signal a12_ENABLE : STD_LOGIC; 
  signal a12_TORGTS : STD_LOGIC; 
  signal a12_OUTMUX : STD_LOGIC; 
  signal a13_ENABLE : STD_LOGIC; 
  signal a13_TORGTS : STD_LOGIC; 
  signal a13_OUTMUX : STD_LOGIC; 
  signal a14_ENABLE : STD_LOGIC; 
  signal a14_TORGTS : STD_LOGIC; 
  signal a14_OUTMUX : STD_LOGIC; 
  signal a15_ENABLE : STD_LOGIC; 
  signal a15_TORGTS : STD_LOGIC; 
  signal a15_OUTMUX : STD_LOGIC; 
  signal a16_ENABLE : STD_LOGIC; 
  signal a16_TORGTS : STD_LOGIC; 
  signal a16_OUTMUX : STD_LOGIC; 
  signal a17_ENABLE : STD_LOGIC; 
  signal a17_TORGTS : STD_LOGIC; 
  signal a17_OUTMUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GWEAND : STD_LOGIC; 
  signal a18_ENABLE : STD_LOGIC; 
  signal a18_TORGTS : STD_LOGIC; 
  signal a18_OUTMUX : STD_LOGIC; 
  signal d10_ENABLE : STD_LOGIC; 
  signal d10_TORGTS : STD_LOGIC; 
  signal d10_OUTMUX : STD_LOGIC; 
  signal d10_IBUF : STD_LOGIC; 
  signal d11_ENABLE : STD_LOGIC; 
  signal d11_TORGTS : STD_LOGIC; 
  signal d11_OUTMUX : STD_LOGIC; 
  signal d11_IBUF : STD_LOGIC; 
  signal d12_ENABLE : STD_LOGIC; 
  signal d12_TORGTS : STD_LOGIC; 
  signal d12_OUTMUX : STD_LOGIC; 
  signal d12_IBUF : STD_LOGIC; 
  signal d13_ENABLE : STD_LOGIC; 
  signal d13_TORGTS : STD_LOGIC; 
  signal d13_OUTMUX : STD_LOGIC; 
  signal d13_IBUF : STD_LOGIC; 
  signal d14_ENABLE : STD_LOGIC; 
  signal d14_TORGTS : STD_LOGIC; 
  signal d14_OUTMUX : STD_LOGIC; 
  signal d14_IBUF : STD_LOGIC; 
  signal d15_ENABLE : STD_LOGIC; 
  signal d15_TORGTS : STD_LOGIC; 
  signal d15_OUTMUX : STD_LOGIC; 
  signal d15_IBUF : STD_LOGIC; 
  signal fse0_p17_ENABLE : STD_LOGIC; 
  signal fse0_p17_TORGTS : STD_LOGIC; 
  signal fse0_p17_OUTMUX : STD_LOGIC; 
  signal ram_ce_ENABLE : STD_LOGIC; 
  signal ram_ce_TORGTS : STD_LOGIC; 
  signal ram_ce_OUTMUX : STD_LOGIC; 
  signal ram_ce_c : STD_LOGIC; 
  signal ram_ce_LOGIC_ZERO : STD_LOGIC; 
  signal ram_ce_SRMUXNOT : STD_LOGIC; 
  signal sl0_p177_ENABLE : STD_LOGIC; 
  signal sl0_p177_TORGTS : STD_LOGIC; 
  signal sl0_p177_OUTMUX : STD_LOGIC; 
  signal ram_oe_ENABLE : STD_LOGIC; 
  signal ram_oe_TORGTS : STD_LOGIC; 
  signal ram_oe_OUTMUX : STD_LOGIC; 
  signal ram_we_ENABLE : STD_LOGIC; 
  signal ram_we_TORGTS : STD_LOGIC; 
  signal ram_we_OUTMUX : STD_LOGIC; 
  signal sl1_p167_ENABLE : STD_LOGIC; 
  signal sl1_p167_TORGTS : STD_LOGIC; 
  signal sl1_p167_OUTMUX : STD_LOGIC; 
  signal sl2_p163_ENABLE : STD_LOGIC; 
  signal sl2_p163_TORGTS : STD_LOGIC; 
  signal sl2_p163_OUTMUX : STD_LOGIC; 
  signal sl3_p156_ENABLE : STD_LOGIC; 
  signal sl3_p156_TORGTS : STD_LOGIC; 
  signal sl3_p156_OUTMUX : STD_LOGIC; 
  signal sl4_p145_ENABLE : STD_LOGIC; 
  signal sl4_p145_TORGTS : STD_LOGIC; 
  signal sl4_p145_OUTMUX : STD_LOGIC; 
  signal vp_p10_IBUF : STD_LOGIC; 
  signal sl5_p138_ENABLE : STD_LOGIC; 
  signal sl5_p138_TORGTS : STD_LOGIC; 
  signal sl5_p138_OUTMUX : STD_LOGIC; 
  signal sl6_p134_ENABLE : STD_LOGIC; 
  signal sl6_p134_TORGTS : STD_LOGIC; 
  signal sl6_p134_OUTMUX : STD_LOGIC; 
  signal Udll_dll_LOCKED : STD_LOGIC; 
  signal Udll_dll_CLKDV : STD_LOGIC; 
  signal Udll_dll_CLK2X : STD_LOGIC; 
  signal Udll_dll_CLK270 : STD_LOGIC; 
  signal Udll_dll_CLK180 : STD_LOGIC; 
  signal Udll_dll_RST_INTERNALNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2630_TINV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_C2631_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2640_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2632_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2641_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2633_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2650_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2642_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2634_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2651_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2643_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2635_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2660_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2652_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2644_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2636_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2661_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2661_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2653_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2645_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2637_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2629_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2662_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2662_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2654_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2646_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2638_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2663_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2663_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2655_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2647_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2639_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2664_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2664_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2656_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2648_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2665_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2665_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2657_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2649_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2666_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2666_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2658_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2667_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2667_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_C2659_TINV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_C2668_TINV : STD_LOGIC; 
  signal Ucore_Uusb_C2668_TMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DOA4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_DIA4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRA1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_ADDRA0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU0_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DOA4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA15 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA14 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA13 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA12 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_DIA4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB11 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB10 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB9 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB8 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB7 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB6 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB5 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB4 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB3 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB2 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRB0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRA1 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_ADDRA0 : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Urom_Urom_BU1_LOGIC_ONE : STD_LOGIC; 
  signal a10_c_FFX_RST : STD_LOGIC; 
  signal a10_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a11_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a12_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a13_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a14_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a15_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a16_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GWEAND : STD_LOGIC; 
  signal a17_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a18_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_x1_n : STD_LOGIC; 
  signal g0_x0_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_249_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C10_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C10_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_8_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_8_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C11_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C11_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_9_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_9_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C12_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C12_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_10_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_10_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C13_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C13_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_11_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_11_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C14_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C14_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_12_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_12_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C15_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C15_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_13_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_13_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C16_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C16_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_14_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_14_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C17_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C17_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_15_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_15_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a1_c_FFX_RST : STD_LOGIC; 
  signal a1_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a2_c_FFX_RST : STD_LOGIC; 
  signal a2_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a3_c_FFX_RST : STD_LOGIC; 
  signal a3_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a4_c_FFX_RST : STD_LOGIC; 
  signal a4_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a5_c_FFX_RST : STD_LOGIC; 
  signal a5_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a6_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a7_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a8_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal a9_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C2_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C2_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_0_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_0_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C3_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C3_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_1_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_1_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C4_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C4_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_2_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_2_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C5_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C5_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_3_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_3_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C6_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C6_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_4_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_4_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C7_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C7_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_5_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_5_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C8_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C8_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_6_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_6_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C9_N7 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uamux_C332_C9_N8 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_7_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_7_F5MUX : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_171_i : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_1_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_1_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_172_i : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_173_i : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_174_i : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_18_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_un19_nextaddr_offset_s_12_n_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N240 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C3_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N241 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N242 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C5_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N243 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N244 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C7_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N245 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N246 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C9_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N247 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N248 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C11_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N249 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N250 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C13_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N251 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N252 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C15_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N253 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_14_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_14_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_14_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N254 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ABUS_15_rt : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_C141_C17_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_14_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uinc_N255 : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_46_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_37_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_state36_0_I_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_c_9_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextc_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_r_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_0_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_r_2_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_r_2_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_2_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_r_4_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_r_4_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_4_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_r_6_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_r_6_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_6_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_r_8_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_r_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_r_8_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_r_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_27_0_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_28_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_43_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_N_51_rt : STD_LOGIC; 
  signal I_10_n_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_3_0_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_0_I_19_O : STD_LOGIC; 
  signal I_10_n_0_LOGIC_ZERO : STD_LOGIC; 
  signal I_10_n_0_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C2_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C3_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C2_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N372_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C4_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N374_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N374_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N374_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C5_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C4_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N374_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C6_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N376_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N376_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N376_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C7_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C6_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N376_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C8_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N378_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N378_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N378_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C9_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C8_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N378_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C10_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N380_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N380_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N380_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C11_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C10_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N380_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C12_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N382_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N382_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N382_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C13_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C12_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N382_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C14_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N384_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N384_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N384_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C15_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C14_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N384_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C16_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N386_XORF : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N386_XORG : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C17_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C379_C16_C2_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_N386_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_1 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_2 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_3 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_4 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_5 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_6 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_7 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_8 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_9 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_axb_10 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_3 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_3_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_4 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_3_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_4_n : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_5 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_5_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_5_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_6 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_5_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_6_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_7 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_7_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_7_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_8 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_7_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_8_n : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_9 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_9_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_9_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_axb_10 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_9_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_10_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_11_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_12_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_13_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_14_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_15_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_15_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_16_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_17_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_17_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_17_n : STD_LOGIC; 
  signal Ucore_Ufunc_SIG_7 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_cry_17_O : STD_LOGIC; 
  signal Ucore_Ufunc_addr_17_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_18_n : STD_LOGIC; 
  signal Ucore_Ufunc_N_27 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_3 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_N_11 : STD_LOGIC; 
  signal I_10_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_0 : STD_LOGIC; 
  signal Ucore_Ufunc_un1_high_temp2_1_0_I_19_O : STD_LOGIC; 
  signal I_10_n_LOGIC_ZERO : STD_LOGIC; 
  signal I_10_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_15_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_0_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_2_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_2_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_2_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_4_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_4_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_4_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_6_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_6_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_6_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_8_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_8_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_8_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_10_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_10_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_10_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_12_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_12_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_12_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_14_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_14_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_14_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_16_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_16_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_cry_16_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_16_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_166_i : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_1_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_1_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_167_i : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_168_i : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_169_i : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_SIG_17 : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_14_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un9_nextaddr_offset_s_14_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_0_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_lcry_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_0_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_1_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_1_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_1_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_3_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_3_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_3_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_3_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_5_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_5_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_5_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_5_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_7_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_7_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_7_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_7_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_9_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_9_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_9_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_9_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_11_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_11_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_11_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_11_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_13_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_13_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_13_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_13_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_15_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_15_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_15_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_15_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_17_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_cry_17_O : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_17_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_readAddr_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_126_i : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_1_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_1_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_1_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_1_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_127_i : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_128_i : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_129_i : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_SIG_27 : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_un14_nextaddr_offset_s_14_n_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_N1515 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_N1516 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C2_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Uusb_N1517 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_N1518 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C4_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_N1519 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_N1520 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C6_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYINIT : STD_LOGIC; 
  signal Ucore_Uusb_N1521 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_N1358_CYMUXG : STD_LOGIC; 
  signal Ucore_Uusb_N1522 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C446_C8_C1_O : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_N1358_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_28_O_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_11_0_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_1_O : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_N_19_rt : STD_LOGIC; 
  signal I_10_n_1_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_N_35_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_low_temp2_0_I_19_O : STD_LOGIC; 
  signal I_10_n_1_LOGIC_ZERO : STD_LOGIC; 
  signal I_10_n_1_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_N_121_i : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_1_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_1_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_122_i : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_N_123_i : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_N_124_i : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_SIG_39 : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nextaddr_offset_s_14_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORG : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_15_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_XORF : STD_LOGIC; 
  signal Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_0_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_0_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_0_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_0_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_2_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_2_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_2_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_2_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_4_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_4_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_4_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_4_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_6_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_6_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_6_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_6_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_8_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_8_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_8_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_8_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_i_10_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_10_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_10_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_10_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_12_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_12_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_12_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_12_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_14_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_14_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_14_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_14_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_16_CYMUXG : STD_LOGIC; 
  signal Ucore_Ufunc_i_16_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_i_cry_16_O : STD_LOGIC; 
  signal Ucore_Ufunc_i_16_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_i_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_18_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_i_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_i_18_CYINIT : STD_LOGIC; 
  signal g0_0_a3_13_O_FROM : STD_LOGIC; 
  signal g0_0_a3_13_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_10_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_10_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data42_4_0_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data42_4_0_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_11_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_11_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_12_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_12_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_13_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_13_O_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_14_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_14_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_15_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_15_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_16_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_16_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_17_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_17_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_GROM : STD_LOGIC; 
  signal g0_1_L3_O_FROM : STD_LOGIC; 
  signal g0_1_L3_O_GROM : STD_LOGIC; 
  signal g0_3_a2_13_O_FROM : STD_LOGIC; 
  signal g0_3_a2_13_O_GROM : STD_LOGIC; 
  signal g0_2_8_O_FROM : STD_LOGIC; 
  signal g0_2_8_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_3_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_3_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_1_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_3_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un37_nextresize_statelto9_2_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un37_nextresize_statelto9_2_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_4_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_4_O_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_5_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_5_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_6_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_6_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_7_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_7_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_8_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_8_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_9_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_5_0_1_9_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_x_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_x_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data26_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N25 : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N40 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_9_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_9_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_9_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N19 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N27 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N51 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N43 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N67 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C10_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C3_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N12 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_10_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N88 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_11_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N95 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N109 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N102 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C24_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C26_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N123 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N116 : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_503_i : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C20_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C22_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_in_en_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_in_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C0_N5 : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C29_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1039_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C25_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_bytecount_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C1075_N11 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_bytecount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C1075_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N25 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C16_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C18_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N40 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C12_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C14_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N62 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_9_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C8_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C10_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N80 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N25 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1567 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2603 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2560 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C4_N35 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2128 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_1_CEMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1006 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N963 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N268 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N14 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_4_CEMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1092 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N11 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N21 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N16 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N31 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N26 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N41 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N36 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N51 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N46 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_N303 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N615 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_in_trac_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_in_trac_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_in_trac_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET2015_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET2015_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1784 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1394 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1913 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1956 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_relf_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_relf_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_relf_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N442 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_N1523 : STD_LOGIC; 
  signal Ucore_Ufunc_state_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_N_28_i : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N37 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N16 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C12_N5 : STD_LOGIC; 
  signal fse0_p17_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C2_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N61 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N56 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N71 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N66 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N76 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2689 : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_6_rt : STD_LOGIC; 
  signal Ucore_Ufunc_un1_nextaddr_s_1_n : STD_LOGIC; 
  signal Ucore_Ufunc_addr_1_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_addr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N42 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N48 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C25_N5 : STD_LOGIC; 
  signal Ucore_Ufunc_doneflag_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_doneflag_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite37 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N12 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C38_N68 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N19 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N14 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N42 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N163 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N31 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N29 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N39 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N34 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N11 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N30 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N25 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N16 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C6_N35 : STD_LOGIC; 
  signal ram_oe_c_FROM : STD_LOGIC; 
  signal ram_oe_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_nextoen : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N21 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N47 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N27 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N3 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N19 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N14 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1654 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1611 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N29 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N24 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N39 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N34 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1740 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_502_i : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N19 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N12 : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N169 : STD_LOGIC; 
  signal Ucore_Ufunc_c_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_c_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_c_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Ufunc_c_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_c_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N77 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N103 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2345 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2302 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2431 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1308 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_stall_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C8_N5 : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_1_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_nextstate : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N748 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N877 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N834 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C3_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N90 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_sel_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_sel_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_sel_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N15 : STD_LOGIC; 
  signal a0_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C34_N20 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C34_N12 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_ADR4_INV : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GRAMS : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GWEAND : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C34_N36 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C34_N28 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C34_N53 : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_7_GROM : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldCol_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_txen1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_txen1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_txen1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_TG_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_TG_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C36_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1434_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1434_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C4_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C6_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C0_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C2_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_15_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C28_N6 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C5_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_setup_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C2_N5 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1178 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_cur_oldRow_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2818 : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_17_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite29_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite29_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_prev_cur_oldRow_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_3_a2_7_FROM : STD_LOGIC; 
  signal g0_3_a2_7_GROM : STD_LOGIC; 
  signal g0_1_4_FROM : STD_LOGIC; 
  signal g0_1_4_GROM : STD_LOGIC; 
  signal g0_0_a3_12_FROM : STD_LOGIC; 
  signal g0_0_a3_12_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_prev_cur_oldRow_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_s_prev_cur_oldRow_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_56_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_56_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_567_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_urx0_FROM : STD_LOGIC; 
  signal Ucore_urx0_GROM : STD_LOGIC; 
  signal N_125_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_8_0_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_8_0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1_11_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_1_11_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_57_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_57_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_58_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_58_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_0_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_59_0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_60_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_60_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_61_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_61_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_68_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_68_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_69_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data38_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data38_GROM : STD_LOGIC; 
  signal Ucore_Uusb_TI_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_TI_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_TI_1_BYMUXNOT : STD_LOGIC; 
  signal g0_3_5_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doRead_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doRead_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_LOGIC_ONE : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_ram_writeAddr_1_11_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_ram_writeAddr_1_11_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_prev_cur_oldRow_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_3_a2_18_FROM : STD_LOGIC; 
  signal g0_3_a2_18_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_s_prev_cur_oldRow_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_1_5_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_L3_n_FROM : STD_LOGIC; 
  signal g0_L3_n_GROM : STD_LOGIC; 
  signal g0_2_4_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal g0_2_5_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_7_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_temp2_2_7_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeData_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_217_i_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_18_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_writeAddr_18_CYINIT : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data37_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data37_GROM : STD_LOGIC; 
  signal g0_L5_O_FROM : STD_LOGIC; 
  signal g0_L5_O_GROM : STD_LOGIC; 
  signal g4_1_FROM : STD_LOGIC; 
  signal g4_1_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_244_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_244_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_state_fast_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_fast_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_fast_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp2_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_state_2_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_30_i : STD_LOGIC; 
  signal Ucore_Ufunc_state_1_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_29_i : STD_LOGIC; 
  signal Ucore_Uusb_CLK24I_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_CLK24I_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_500_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_500_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_438_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_438_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_rep1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_rep1_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_imageloaded_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_18_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_addr_offset_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_next_write_data37_1_GROM : STD_LOGIC; 
  signal g0_1_a2_2_FROM : STD_LOGIC; 
  signal g0_1_a2_2_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_220_GROM : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_15_FFY_RST : STD_LOGIC; 
  signal g0_1_L1_n_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_INI_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_INI_LOGIC_ZERO : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite_1_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_resize_doWrite_1_GROM : STD_LOGIC; 
  signal N_112_FROM : STD_LOGIC; 
  signal N_112_GROM : STD_LOGIC; 
  signal sr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_dout_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_520_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_520_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7870_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7870_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1035_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1035_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C27_N5 : STD_LOGIC; 
  signal Ucore_din_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_2_8_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_2_8_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_sram_presstate_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sl_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sl_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sl_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sl_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_dout_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal sr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_din_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_temp1_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_7_i_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ram_canRead_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_ram_canRead_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_CKMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_2_0_a2_0_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_rst_2_0_a2_0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_next_write_data37_8_16_n_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2732 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C492_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C492_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_in_trac_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_in_trac_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28147_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28147_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N27 : STD_LOGIC; 
  signal Ucore_Uusb_syn28034_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28034_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28144_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7677_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7677_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N356 : STD_LOGIC; 
  signal Ucore_Uusb_syn7527_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7527_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28141_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7848_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7848_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27750_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27750_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28143_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7842_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7842_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5311_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5311_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5336_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5336_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7724_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7724_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N48 : STD_LOGIC; 
  signal Ucore_Uusb_syn28150_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28150_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28142_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27751_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2085 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2775 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C656_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C656_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5312_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5312_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C598_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C598_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N179 : STD_LOGIC; 
  signal Ucore_Uusb_syn28033_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28033_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6430_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6430_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N29 : STD_LOGIC; 
  signal g0_L1_n_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5162_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5162_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5302_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5302_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5328_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5328_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C640_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C640_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28077_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28077_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27530_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27530_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N51 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C700_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C700_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C702_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C702_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N74 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N68 : STD_LOGIC; 
  signal Ucore_Uusb_syn5903_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5903_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27544_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27544_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5295_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5295_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5299_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5299_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2861 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N41 : STD_LOGIC; 
  signal Ucore_Uusb_syn7709_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7709_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N31_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N31_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6532_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6532_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5945_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5945_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5313_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5313_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2042 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N88 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27498_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27498_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N12 : STD_LOGIC; 
  signal Ucore_Uusb_syn7197_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7197_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5300_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5300_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2388 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1465_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1465_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6023_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6023_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1480 : STD_LOGIC; 
  signal Ucore_Uusb_syn7335_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7335_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N90 : STD_LOGIC; 
  signal Ucore_Uusb_syn6694_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C38_N56 : STD_LOGIC; 
  signal Ucore_Uusb_syn6926_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6926_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27532_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27532_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn21091_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn21091_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C664_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C664_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C650_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C650_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N58 : STD_LOGIC; 
  signal Ucore_Uusb_syn20388_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn20388_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C929_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C929_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27327_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27327_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_NET71_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_NET71_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27958_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27958_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6505_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6505_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C38_N25 : STD_LOGIC; 
  signal Ucore_Uusb_syn5164_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5164_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27466_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27466_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C617_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C617_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N37_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_N37_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C746_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C746_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26906_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26906_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27855_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27855_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23977_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23977_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27650_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1135 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N225 : STD_LOGIC; 
  signal Ucore_Uusb_syn27056_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27056_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6464_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6464_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6653_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6653_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6691_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6691_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_5_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N18 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Upsw_C0_N36 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26593_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26593_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27074_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27074_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27073_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27073_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5303_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5303_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27277_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6824_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6824_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C751_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C751_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26597_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26597_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1461_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1461_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27279_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27279_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27389_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27389_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N29 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_5_CEMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1999 : STD_LOGIC; 
  signal Ucore_Uusb_syn5325_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5325_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6264_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6264_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26592_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26592_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27104_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27104_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_P0WR_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_P0WR_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C743_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C743_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5344_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5344_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5290_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5290_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5751_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5751_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26591_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26591_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27086_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27086_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N12_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N12_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6673_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6673_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_C68_N19 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_3_CEMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2904 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N39 : STD_LOGIC; 
  signal Ucore_Uusb_syn26646_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26646_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26595_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26595_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27103_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27103_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23575_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23575_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27084_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N18_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N18_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N24_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N24_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5333_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5333_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27328_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27328_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_14_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udptr_C30_N6 : STD_LOGIC; 
  signal Ucore_Uusb_syn5301_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5301_GROM : STD_LOGIC; 
  signal Ucore_Uusb_CLK12I_FROM : STD_LOGIC; 
  signal Ucore_Uusb_CLK12I_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C23_N12 : STD_LOGIC; 
  signal Ucore_Uusb_syn26645_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26645_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26839_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26839_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26594_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26594_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N42_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N42_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N48_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N48_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5645_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5645_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6817_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6817_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_T1WR_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_8_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N74 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C69_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C69_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_9_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N81 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N572 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C345_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C345_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6158_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6158_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26650_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26650_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26989_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26989_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26647_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26647_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7732_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7732_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N54_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N54_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5316_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5316_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N59 : STD_LOGIC; 
  signal Ucore_Uusb_syn5315_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5315_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N81 : STD_LOGIC; 
  signal Ucore_Uusb_syn28539_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28539_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_high_temp2_fast_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C331_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C331_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23133_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23133_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26791_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26791_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26649_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26649_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N60_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C380_N60_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C0_N39_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C0_N39_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1434_N15 : STD_LOGIC; 
  signal Ucore_Uusb_syn5309_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5309_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C755_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C755_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5349_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5349_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5293_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5293_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C353_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C353_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26313_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26313_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26697_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26697_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26648_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26648_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26837_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26837_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27015_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27015_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6607_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6607_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C1434_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_C1_N11 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C333_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C333_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26696_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26696_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26788_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26788_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26698_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26698_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5190_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5190_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23519_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23519_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6805_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6805_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N15 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N48 : STD_LOGIC; 
  signal Ucore_Uusb_syn28551_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28551_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5664_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5664_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5342_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5342_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27492_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27492_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C339_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C339_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C325_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C325_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_4_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26757_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26757_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26932_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26932_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26980_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26980_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6106_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6106_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26931_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26931_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6527_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6527_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6519_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6519_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8001_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8001_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_C38_N40 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N27 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N20 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_cell17_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_cell17_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N12_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N12_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_high_temp2_fast_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_syn26700_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26700_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26578_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26578_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26812_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26812_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5191_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5191_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27014_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27151_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27151_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28418_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28418_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8044_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8079_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8079_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N42 : STD_LOGIC; 
  signal Ucore_Uusb_syn8331_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8331_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N36_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N36_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5659_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5659_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C683_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C683_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5917_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5917_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5341_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26579_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26579_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C319_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C319_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C327_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C327_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26651_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26651_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C661_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C661_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26736_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26736_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26699_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26699_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26994_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26994_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_0_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn24588_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn24588_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N24 : STD_LOGIC; 
  signal Ucore_Uusb_syn28427_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28427_GROM : STD_LOGIC; 
  signal Ucore_Uusb_N1553 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N22 : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N48_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N48_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26285_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26285_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26754_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6360_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6360_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26969_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26969_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6513_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6513_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_N484_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28409_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28409_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28445_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28445_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_C36_N24_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5624_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5624_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5338_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5338_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C690_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C690_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6257_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6257_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_5_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_5_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26734_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26734_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6524_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6524_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N36 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N34 : STD_LOGIC; 
  signal Ucore_Ufunc_high_temp2_fast_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_3_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_3_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27118_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27118_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5913_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5913_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5910_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5910_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C313_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Udmux_C313_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6073_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26758_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26758_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26953_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26953_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26947_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26947_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8011_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8011_GROM : STD_LOGIC; 
  signal Ucore_Uusb_N1514_FROM : STD_LOGIC; 
  signal Ucore_Uusb_N1514_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N18 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_GROM : STD_LOGIC; 
  signal vpo_p13_c_FROM : STD_LOGIC; 
  signal vpo_p13_c_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C10_N9 : STD_LOGIC; 
  signal Ucore_Uusb_syn28612_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28612_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N54 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS59_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5539_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5539_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26270_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26270_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5652_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5652_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5292_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5292_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5323_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5323_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C611_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C611_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6007_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6007_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26681_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26681_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26701_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26701_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26732_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26732_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26078_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26078_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27132_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn27132_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28193_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28193_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS67_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS67_7_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C458_C8_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C458_C8_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5320_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5320_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5868_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5868_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26575_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26575_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5298_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5298_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C681_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C681_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn23120_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26905_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N30 : STD_LOGIC; 
  signal Ucore_Uusb_syn8277_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS67_5_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS67_5_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10875_6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5161_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5161_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5294_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5294_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn20067_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn20067_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26678_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26678_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7962_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7962_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N12 : STD_LOGIC; 
  signal Ucore_Ufunc_high_temp2_fast_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5618_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5725_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5725_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26085_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26085_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5237_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5237_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_6_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_6_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26656_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26656_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26889_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26889_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26910_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26910_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26076_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26076_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5324_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5324_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26569_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26569_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn20383_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6071_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn6071_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28620_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28620_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5544_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5544_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26082_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26082_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C677_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26628_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26628_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5310_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5310_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26861_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26861_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26885_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26885_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N50 : STD_LOGIC; 
  signal Ucore_Uusb_syn5279_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5279_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N6 : STD_LOGIC; 
  signal Ucore_Uusb_syn28617_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_syn5686_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5686_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26072_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26072_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26860_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8151_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn8151_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_6_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N10 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_BUS67_1_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26859_GROM : STD_LOGIC; 
  signal Ucore_Uusb_N1540_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26461_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26461_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_7_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_7_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28225_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn28225_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5458_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5458_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C447_C18_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C447_C18_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ualu_C458_C13_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5750_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5750_GROM : STD_LOGIC; 
  signal Ucore_Uusb_syn7912_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N22 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_syn26596_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn26596_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N36 : STD_LOGIC; 
  signal Ucore_Uusb_syn20065_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn20065_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_syn5667_FROM : STD_LOGIC; 
  signal Ucore_Uusb_syn5667_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_ie_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_ie_GROM : STD_LOGIC; 
  signal un3_doingwrite1_n_GROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_GROM : STD_LOGIC; 
  signal Ucore_Uusb_DI_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_DI_1_BYMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_253_i_FROM : STD_LOGIC; 
  signal Ucore_Ufunc_N_253_i_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FROM : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C22_N11 : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_low_temp2_fast_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Ufunc_N_246_i_GROM : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_0_BXMUXNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N129 : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C22_N9 : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_11_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_12_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_13_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_15_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_14_FFX_RST : STD_LOGIC; 
  signal ram_ce_OFF_SET : STD_LOGIC; 
  signal a17_c_FFX_RST : STD_LOGIC; 
  signal a18_c_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_8_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_9_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_10_FFX_RST : STD_LOGIC; 
  signal a11_c_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFY_RST : STD_LOGIC; 
  signal a12_c_FFX_RST : STD_LOGIC; 
  signal a13_c_FFX_RST : STD_LOGIC; 
  signal a14_c_FFX_RST : STD_LOGIC; 
  signal a15_c_FFX_RST : STD_LOGIC; 
  signal a16_c_FFX_RST : STD_LOGIC; 
  signal a6_c_FFX_RST : STD_LOGIC; 
  signal a7_c_FFX_RST : STD_LOGIC; 
  signal a8_c_FFX_RST : STD_LOGIC; 
  signal a9_c_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_0_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_6_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PCO_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_0_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_8_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_14_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_10_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_INCO_12_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_13_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_13_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_15_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_15_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_presstate_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_relf_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FFY_RST : STD_LOGIC; 
  signal fse0_p17_c_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_in_en_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1039_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_14_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_8_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_9_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FFY_RST : STD_LOGIC; 
  signal fse0_p17_c_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_9_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_in_trac_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET2015_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_11_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_13_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_13_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_15_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_15_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_9_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1039_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_bytecount_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFY_RST : STD_LOGIC; 
  signal ram_oe_c_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_rxd_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_TG_0_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uglue_txen1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_11_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_11_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_13_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_15_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DPTRO_13_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_sel_FFX_RST : STD_LOGIC; 
  signal a0_c_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FFY_SET : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_11_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_11_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_6_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS126_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_9_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_writedatareg_9_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_6_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_8_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_8_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_12_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_12_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uport0_pad_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP2_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS10881_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_state_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BO_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS141_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS141_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS141_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_4_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_9_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_9_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFX_RST : STD_LOGIC; 
  signal Ucore_dout_15_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_NET1035_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_11_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_13_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_11_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_13_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_15_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_resize_write_data_15_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_14_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS1610_14_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_INI_FFY_SET : STD_LOGIC; 
  signal sr_3_FFY_RST : STD_LOGIC; 
  signal sr_5_FFY_RST : STD_LOGIC; 
  signal sr_3_FFX_RST : STD_LOGIC; 
  signal sr_6_FFY_RST : STD_LOGIC; 
  signal sr_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Ufunc_state_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_CLK24I_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_BUS131_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_DSEL_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_PO_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_ALUOP_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_CLK12I_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUFO8_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_0_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FFY_RST : STD_LOGIC; 
  signal vpo_p13_c_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_OP3_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_DI_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_BUS1153_10_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_6_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_2_FFY_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_SPO_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Ufunc_sram_presstate_2_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_FFY_RST : STD_LOGIC; 
  signal sl_1_FFY_RST : STD_LOGIC; 
  signal sl_1_FFX_RST : STD_LOGIC; 
  signal sl_3_FFY_RST : STD_LOGIC; 
  signal sl_3_FFX_RST : STD_LOGIC; 
  signal sl_5_FFY_RST : STD_LOGIC; 
  signal sl_5_FFX_RST : STD_LOGIC; 
  signal sl_6_FFY_RST : STD_LOGIC; 
  signal Ucore_dout_7_FFY_RST : STD_LOGIC; 
  signal sr_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_FFY_RST : STD_LOGIC; 
  signal sr_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Uctrl_CSP_0_FFX_SET : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_RAM_REG_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_Ubuf_rel_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_5_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_5_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_7_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_AO_7_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFY_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFX_RST : STD_LOGIC; 
  signal Ucore_Uusb_U1_CE : STD_LOGIC; 
  signal Ucore_Uusb_U2_CE : STD_LOGIC; 
  signal Udll_clk2xg_CE : STD_LOGIC; 
  signal Udll_clkg_CE : STD_LOGIC; 
  signal PWR_VCC_0_FROM : STD_LOGIC; 
  signal PWR_VCC_0_GROM : STD_LOGIC; 
  signal PWR_VCC_1_FROM : STD_LOGIC; 
  signal PWR_VCC_1_GROM : STD_LOGIC; 
  signal PWR_GND_0_GROM : STD_LOGIC; 
  signal PWR_GND_1_GROM : STD_LOGIC; 
  signal PWR_GND_2_GROM : STD_LOGIC; 
  signal PWR_GND_3_GROM : STD_LOGIC; 
  signal PWR_GND_4_GROM : STD_LOGIC; 
  signal PWR_GND_5_GROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Ucore_Uusb_Uuc_BUS12659 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Ucore_Uusb_Uuc_DBUS : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_RO : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_BUS59 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_BUS67 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_BUS63 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_ALUOP : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_AO : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_Utmp2_TMP2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_BUS10875 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_BUS10881 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal sr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Ucore_Ufunc_sram_writedatareg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal sl : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Ucore_Uusb_BUS1614 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_BUS206 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_in_trac : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Uusb_Uusb_BUS8585 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_BUS141 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Ufunc_i : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_ram_writeAddr : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_addr : STD_LOGIC_VECTOR ( 18 downto 1 ); 
  signal Ucore_Ufunc_ram_readAddr : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_CSP : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_ASEL : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Uusb_Uuc_INCO : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uuc_DPTRO : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uuc_PCO : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uuc_ABUS : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Ufunc_addr_offset : STD_LOGIC_VECTOR ( 18 downto 3 ); 
  signal Ucore_Ufunc_temp1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Ufunc_temp2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Ufunc_c : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Ucore_Ufunc_resize_state : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Ufunc_r : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Ucore_Uusb_Uuc_BUFO8 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uuc_Ubuf_rel : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Ufunc_s_cur_oldRow : STD_LOGIC_VECTOR ( 15 downto 6 ); 
  signal Ucore_Ufunc_s_prev_cur_oldRow : STD_LOGIC_VECTOR ( 15 downto 6 ); 
  signal Ucore_Ufunc_s_cur_oldCol : STD_LOGIC_VECTOR ( 15 downto 6 ); 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0_0 : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Ucore_Ufunc_state : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Ufunc_nextresize_state_m2 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Ufunc_nextresize_state_enl_0_0 : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Ucore_Ufunc_nextresize_state_enl_0_a2_0 : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Ucore_Ufunc_nextresize_state_enl_i_1 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Ufunc_ram_writeData : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Ufunc_resize_write_data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_BUS1153 : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Ufunc_nextresize_state : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uusb_Uep0ctrl_Sfifo : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_BUS131 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_BUS222 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uglue_bytecount : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_IT : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Urst_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_BUS15211 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uuc_PO : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_rxd : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Ufunc_sram_presstate : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Ufunc_sram_writeAddr : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_TG : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uport0_pad : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Ufunc_high_temp2_fast : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Ufunc_low_temp2_fast : STD_LOGIC_VECTOR ( 5 downto 2 ); 
  signal Ucore_Uusb_Uuc_BO : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_TI : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal Ucore_Uusb_Uuc_OP2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_din : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Uusb_Uuc_DSEL : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_Q : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Ucore_Uusb_Uuc_RAM_REG : STD_LOGIC_VECTOR ( 7 downto 7 ); 
  signal Ucore_Uusb_Uuc_OP3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uuc_SPO : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc : STD_LOGIC_VECTOR ( 15 downto 15 ); 
  signal Ucore_Uusb_DI : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal Ucore_Uusb_Uusb_Uep0ctrl_n : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Ucore_Ufunc_sram_addrreg_4_bm_n : STD_LOGIC_VECTOR ( 18 downto 1 ); 
  signal Ucore_Ufunc_sram_addrreg_4_am_n : STD_LOGIC_VECTOR ( 18 downto 1 ); 
  signal Ucore_Ufunc_sram_addrreg_4 : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_r_qxu : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Ucore_Ufunc_r_s : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Ucore_Ufunc_ram_writeAddr_qxu : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_ram_writeAddr_s : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_ram_readAddr_qxu : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_ram_readAddr_s : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_i_qxu : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_i_s : STD_LOGIC_VECTOR ( 18 downto 0 ); 
  signal Ucore_Ufunc_sram_writeData : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Ucore_Ufunc_addr_offset_5 : STD_LOGIC_VECTOR ( 18 downto 3 ); 
  signal Ucore_Ufunc_s_cur_oldCol_5 : STD_LOGIC_VECTOR ( 15 downto 7 ); 
  signal Ucore_Ufunc_s_cur_oldRow_5 : STD_LOGIC_VECTOR ( 15 downto 7 ); 
  signal Ucore_Ufunc_c_5 : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS1411 : STD_LOGIC_VECTOR ( 7 downto 7 ); 
begin
  Ucore_Uusb_Uuc_Uram_U1_BU19_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU19_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU19_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FWEAND_0 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GWEAND_1 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N313_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N313_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N313
    );
  Ucore_Uusb_Uuc_Uram_U1_BU11_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU11_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU11_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FWEAND_2 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GWEAND_3 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N230_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N230_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N230
    );
  Ucore_Uusb_Uuc_Uram_U1_BU35_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU35_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU35_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FWEAND_4 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GWEAND_5 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N479_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N479_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N479
    );
  Ucore_Uusb_Uuc_Uram_U1_BU27_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU27_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(7),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU27_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FWEAND_6 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GWEAND_7 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N396_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N396_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N396
    );
  Ucore_Uusb_Uuc_Uram_U1_BU59 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N1365,
      IB => Ucore_Uusb_Uuc_Uram_U1_N1367,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_7_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU58 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N396,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N479,
      O => Ucore_Uusb_Uuc_Uram_U1_N1367
    );
  Ucore_Uusb_Uuc_Uram_U1_BU57 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N313,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N230,
      O => Ucore_Uusb_Uuc_Uram_U1_N1365
    );
  Ucore_Uusb_Uuc_RO_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_7_F5MUX,
      O => Ucore_Uusb_Uuc_RO(7)
    );
  Ucore_Uusb_Uuc_Uram_U1_N312_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N312
    );
  Ucore_Uusb_Uuc_Uram_U1_N229_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N229
    );
  Ucore_Uusb_Uuc_Uram_U1_N478_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N478
    );
  Ucore_Uusb_Uuc_Uram_U1_N395_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N395
    );
  Ucore_Uusb_Uuc_Uram_U1_BU56 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N1262,
      IB => Ucore_Uusb_Uuc_Uram_U1_N1264,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_6_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU55 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N395,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N478,
      O => Ucore_Uusb_Uuc_Uram_U1_N1264
    );
  Ucore_Uusb_Uuc_Uram_U1_BU54 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N312,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N229,
      O => Ucore_Uusb_Uuc_Uram_U1_N1262
    );
  Ucore_Uusb_Uuc_RO_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_6_F5MUX,
      O => Ucore_Uusb_Uuc_RO(6)
    );
  Ucore_Uusb_Uuc_Uram_U1_N311_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N311
    );
  Ucore_Uusb_Uuc_Uram_U1_N228_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N228
    );
  Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GWEAND_8 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FWEAND_9 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU18_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU18_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU18_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N312_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU33_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU33_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU33_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FWEAND_10 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GWEAND_11 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N477_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N477_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N477
    );
  Ucore_Uusb_Uuc_Uram_U1_N394_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N394
    );
  Ucore_Uusb_Uuc_Uram_U1_BU53 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N1159,
      IB => Ucore_Uusb_Uuc_Uram_U1_N1161,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_5_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU52 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N477,
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N394,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_Uuc_Uram_U1_N1161
    );
  Ucore_Uusb_Uuc_Uram_U1_BU51 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N311,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N228,
      O => Ucore_Uusb_Uuc_Uram_U1_N1159
    );
  Ucore_Uusb_Uuc_RO_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_5_F5MUX,
      O => Ucore_Uusb_Uuc_RO(5)
    );
  Ucore_Uusb_Uuc_Uram_U1_N310_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N310
    );
  Ucore_Uusb_Uuc_Uram_U1_N227_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N227
    );
  Ucore_Uusb_Uuc_Uram_U1_N476_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N476
    );
  Ucore_Uusb_Uuc_Uram_U1_N393_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N393
    );
  Ucore_Uusb_Uuc_Uram_U1_BU50 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N1056,
      IB => Ucore_Uusb_Uuc_Uram_U1_N1058,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_4_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU49 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N393,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N476,
      O => Ucore_Uusb_Uuc_Uram_U1_N1058
    );
  Ucore_Uusb_Uuc_Uram_U1_BU48 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uram_U1_N310,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N227,
      O => Ucore_Uusb_Uuc_Uram_U1_N1056
    );
  Ucore_Uusb_Uuc_RO_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_4_F5MUX,
      O => Ucore_Uusb_Uuc_RO(4)
    );
  Ucore_Uusb_Uuc_Uram_U1_N309_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N309
    );
  Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GWEAND_12 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FWEAND_13 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU10_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU10_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU10_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N229_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_N226_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N226
    );
  Ucore_Uusb_Uuc_Uram_U1_N475_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N475
    );
  Ucore_Uusb_Uuc_Uram_U1_N392_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N392
    );
  Ucore_Uusb_Uuc_Uram_U1_BU47 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N953,
      IB => Ucore_Uusb_Uuc_Uram_U1_N955,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_3_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU46 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N392,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N475,
      O => Ucore_Uusb_Uuc_Uram_U1_N955
    );
  Ucore_Uusb_Uuc_Uram_U1_BU45 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N309,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N226,
      O => Ucore_Uusb_Uuc_Uram_U1_N953
    );
  Ucore_Uusb_Uuc_RO_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_3_F5MUX,
      O => Ucore_Uusb_Uuc_RO(3)
    );
  Ucore_Uusb_Uuc_Uram_U1_N308_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N308
    );
  Ucore_Uusb_Uuc_Uram_U1_N225_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N225
    );
  Ucore_Uusb_Uuc_Uram_U1_N474_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N474
    );
  Ucore_Uusb_Uuc_Uram_U1_N391_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N391
    );
  Ucore_Uusb_Uuc_Uram_U1_BU44 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N850,
      IB => Ucore_Uusb_Uuc_Uram_U1_N852,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_2_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU43 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N391,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N474,
      O => Ucore_Uusb_Uuc_Uram_U1_N852
    );
  Ucore_Uusb_Uuc_Uram_U1_BU42 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uram_U1_N225,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N308,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_Uuc_Uram_U1_N850
    );
  Ucore_Uusb_Uuc_RO_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_2_F5MUX,
      O => Ucore_Uusb_Uuc_RO(2)
    );
  Ucore_Uusb_Uuc_Uram_U1_N307_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N307
    );
  Ucore_Uusb_Uuc_Uram_U1_N224_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N224
    );
  Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GWEAND_14 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FWEAND_15 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU34_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU34_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU34_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N478_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU29_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU29_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU29_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FWEAND_16 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GWEAND_17 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N473_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N473_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N473
    );
  Ucore_Uusb_Uuc_Uram_U1_N390_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N390
    );
  Ucore_Uusb_Uuc_Uram_U1_BU41 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N747,
      IB => Ucore_Uusb_Uuc_Uram_U1_N749,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_1_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU40 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N390,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N473,
      O => Ucore_Uusb_Uuc_Uram_U1_N749
    );
  Ucore_Uusb_Uuc_Uram_U1_BU39 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N307,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uram_U1_N224,
      O => Ucore_Uusb_Uuc_Uram_U1_N747
    );
  Ucore_Uusb_Uuc_RO_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_1_F5MUX,
      O => Ucore_Uusb_Uuc_RO(1)
    );
  Ucore_Uusb_Uuc_Uram_U1_N306_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N306
    );
  Ucore_Uusb_Uuc_Uram_U1_N223_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N223
    );
  Ucore_Uusb_Uuc_Uram_U1_N472_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N472
    );
  Ucore_Uusb_Uuc_Uram_U1_N389_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1,
      O => Ucore_Uusb_Uuc_Uram_U1_N389
    );
  Ucore_Uusb_Uuc_Uram_U1_BU38 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N644,
      IB => Ucore_Uusb_Uuc_Uram_U1_N646,
      SEL => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_RO_0_F5MUX
    );
  Ucore_Uusb_Uuc_Uram_U1_BU37 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N389,
      ADR2 => Ucore_Uusb_Uuc_Uram_U1_N472,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_Uuc_Uram_U1_N646
    );
  Ucore_Uusb_Uuc_Uram_U1_BU36 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uram_U1_N223,
      ADR1 => Ucore_Uusb_Uuc_Uram_U1_N306,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_Uuc_Uram_U1_N644
    );
  Ucore_Uusb_Uuc_RO_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RO_0_F5MUX,
      O => Ucore_Uusb_Uuc_RO(0)
    );
  Ucore_Uusb_C3498 : X_LUT4
    generic map(
      INIT => X"DDFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR1 => Ucore_Uusb_syn5161,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_syn27130_FROM
    );
  Ucore_Uusb_Uuc_Uram_U1_BU1 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_RWR,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(6),
      ADR3 => VCC,
      O => Ucore_Uusb_syn27130_GROM
    );
  Ucore_Uusb_syn27130_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27130_FROM,
      O => Ucore_Uusb_syn27130
    );
  Ucore_Uusb_syn27130_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27130_GROM,
      O => Ucore_Uusb_Uuc_Uram_U1_N35
    );
  Ucore_Uusb_Uuc_Uram_U1_BU2 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(6),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_RWR,
      O => Ucore_Uusb_Uuc_Uram_U1_N36_GROM
    );
  Ucore_Uusb_Uuc_Uram_U1_N36_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N36_GROM,
      O => Ucore_Uusb_Uuc_Uram_U1_N36
    );
  Ucore_Uusb_Uuc_Uram_U1_BU3 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_RWR,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(6),
      O => Ucore_Uusb_Uuc_Uram_U1_N37_GROM
    );
  Ucore_Uusb_Uuc_Uram_U1_N37_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uram_U1_N37_GROM,
      O => Ucore_Uusb_Uuc_Uram_U1_N37
    );
  Ucore_Uusb_C3481 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6524,
      ADR1 => Ucore_Uusb_syn6527,
      ADR2 => Ucore_Uusb_syn6519,
      ADR3 => Ucore_Uusb_syn6514,
      O => Ucore_Uusb_Uuc_RWR_FROM
    );
  Ucore_Uusb_Uuc_Uram_U1_BU0 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(6),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_Uuc_RWR,
      O => Ucore_Uusb_Uuc_RWR_GROM
    );
  Ucore_Uusb_Uuc_RWR_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RWR_FROM,
      O => Ucore_Uusb_Uuc_RWR
    );
  Ucore_Uusb_Uuc_RWR_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_RWR_GROM,
      O => Ucore_Uusb_Uuc_Uram_U1_N34
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU7 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_3,
      I => Ucore_Uusb_Uusb_BUS67(7),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_7_FRAMS
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU6 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_3,
      I => Ucore_Uusb_Uusb_BUS67(6),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_7_GRAMS
    );
  Ucore_Uusb_Uusb_BUS63_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_7_FRAMS,
      O => Ucore_Uusb_Uusb_BUS63(7)
    );
  Ucore_Uusb_Uusb_BUS63_7_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_7_GRAMS,
      O => Ucore_Uusb_Uusb_BUS63(6)
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU5 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_2,
      I => Ucore_Uusb_Uusb_BUS67(5),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_5_FRAMS
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU4 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_2,
      I => Ucore_Uusb_Uusb_BUS67(4),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_5_GRAMS
    );
  Ucore_Uusb_Uusb_BUS63_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_5_FRAMS,
      O => Ucore_Uusb_Uusb_BUS63(5)
    );
  Ucore_Uusb_Uusb_BUS63_5_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_5_GRAMS,
      O => Ucore_Uusb_Uusb_BUS63(4)
    );
  Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GWEAND_18 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FWEAND_19 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU26_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU26_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU26_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(6),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N395_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU3 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_2,
      I => Ucore_Uusb_Uusb_BUS67(3),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_3_FRAMS
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU2 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_2,
      I => Ucore_Uusb_Uusb_BUS67(2),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_3_GRAMS
    );
  Ucore_Uusb_Uusb_BUS63_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_3_FRAMS,
      O => Ucore_Uusb_Uusb_BUS63(3)
    );
  Ucore_Uusb_Uusb_BUS63_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_3_GRAMS,
      O => Ucore_Uusb_Uusb_BUS63(2)
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU1 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_1,
      I => Ucore_Uusb_Uusb_BUS67(1),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_1_FRAMS
    );
  Ucore_Uusb_Uusb_Ufifox_U1_BU0 : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_BUS59(0),
      ADR1 => Ucore_Uusb_Uusb_BUS59(1),
      ADR2 => Ucore_Uusb_Uusb_BUS59(2),
      ADR3 => GLOBAL_LOGIC0_1,
      I => Ucore_Uusb_Uusb_BUS67(0),
      CLK => Ucore_Uusb_CLK12,
      WE => Ucore_Uusb_Uusb_NET71,
      O => Ucore_Uusb_Uusb_BUS63_1_GRAMS
    );
  Ucore_Uusb_Uusb_BUS63_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_1_FRAMS,
      O => Ucore_Uusb_Uusb_BUS63(1)
    );
  Ucore_Uusb_Uusb_BUS63_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS63_1_GRAMS,
      O => Ucore_Uusb_Uusb_BUS63(0)
    );
  Ucore_Uusb_C3772 : X_XOR2
    port map (
      I0 => BLK0_2_CYINIT,
      I1 => Ucore_Uusb_syn29043,
      O => BLK0_2_XORF
    );
  Ucore_Uusb_C3773 : X_LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5667,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_AO(4),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(4),
      O => Ucore_Uusb_syn29043
    );
  Ucore_Uusb_C3824 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_AO(4),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(4),
      O => BLK0_2_GROM
    );
  BLK0_2_XUSED : X_BUF
    port map (
      I => BLK0_2_XORF,
      O => Ucore_Uusb_syn26073
    );
  BLK0_2_YUSED : X_BUF
    port map (
      I => BLK0_2_GROM,
      O => Ucore_Uusb_Uuc_BUS10875(4)
    );
  BLK0_2_CYINIT_20 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP(0),
      O => BLK0_2_CYINIT
    );
  Ucore_Uusb_C3788 : X_XOR2
    port map (
      I0 => BLK1_2_CYINIT,
      I1 => Ucore_Uusb_syn29039,
      O => BLK1_2_XORF
    );
  Ucore_Uusb_C3789 : X_LUT4
    generic map(
      INIT => X"780F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_syn5686,
      ADR3 => Ucore_Uusb_Uuc_BUS10875(2),
      O => Ucore_Uusb_syn29039
    );
  Ucore_Uusb_C3751 : X_LUT4
    generic map(
      INIT => X"000C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn5293,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(1),
      O => BLK1_2_GROM
    );
  BLK1_2_XUSED : X_BUF
    port map (
      I => BLK1_2_XORF,
      O => Ucore_Uusb_syn20278
    );
  BLK1_2_YUSED : X_BUF
    port map (
      I => BLK1_2_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C597
    );
  BLK1_2_CYINIT_21 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10881(2),
      O => BLK1_2_CYINIT
    );
  Ucore_Uusb_C3743 : X_XOR2
    port map (
      I0 => BLK2_2_CYINIT,
      I1 => Ucore_Uusb_syn29047,
      O => BLK2_2_XORF
    );
  Ucore_Uusb_C3744 : X_LUT4
    generic map(
      INIT => X"BABF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(7),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_Uuc_AO(7),
      O => Ucore_Uusb_syn29047
    );
  Ucore_Uusb_C3827 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(7),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_AO(7),
      O => BLK2_2_GROM
    );
  BLK2_2_XUSED : X_BUF
    port map (
      I => BLK2_2_XORF,
      O => Ucore_Uusb_syn26088
    );
  BLK2_2_YUSED : X_BUF
    port map (
      I => BLK2_2_GROM,
      O => Ucore_Uusb_Uuc_BUS10875(7)
    );
  BLK2_2_CYINIT_22 : X_BUF
    port map (
      I => Ucore_Uusb_syn26076,
      O => BLK2_2_CYINIT
    );
  Ucore_Uusb_C3766 : X_XOR2
    port map (
      I0 => BLK3_2_CYINIT,
      I1 => Ucore_Uusb_syn29045,
      O => BLK3_2_XORF
    );
  Ucore_Uusb_C3767 : X_LUT4
    generic map(
      INIT => X"EFDC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5667,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_Uuc_BUS10875(5),
      ADR3 => Ucore_Uusb_syn5725,
      O => Ucore_Uusb_syn29045
    );
  Ucore_Uusb_C3739 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => Ucore_Uusb_syn5667,
      O => BLK3_2_GROM
    );
  BLK3_2_XUSED : X_BUF
    port map (
      I => BLK3_2_XORF,
      O => Ucore_Uusb_syn23094
    );
  BLK3_2_YUSED : X_BUF
    port map (
      I => BLK3_2_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C675
    );
  BLK3_2_CYINIT_23 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10881(5),
      O => BLK3_2_CYINIT
    );
  Ucore_Uusb_C3793 : X_XOR2
    port map (
      I0 => BLK4_2_CYINIT,
      I1 => Ucore_Uusb_syn29041,
      O => BLK4_2_XORF
    );
  Ucore_Uusb_C3794 : X_LUT4
    generic map(
      INIT => X"9C3C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C419_C0_C4,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(1),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_syn29041
    );
  Ucore_Uusb_C3799 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_syn5293,
      O => BLK4_2_GROM
    );
  BLK4_2_XUSED : X_BUF
    port map (
      I => BLK4_2_XORF,
      O => Ucore_Uusb_syn20137
    );
  BLK4_2_YUSED : X_BUF
    port map (
      I => BLK4_2_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C689
    );
  BLK4_2_CYINIT_24 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10881(1),
      O => BLK4_2_CYINIT
    );
  Ucore_Uusb_C3779 : X_XOR2
    port map (
      I0 => BLK5_2_CYINIT,
      I1 => Ucore_Uusb_syn29037,
      O => BLK5_2_XORF
    );
  Ucore_Uusb_C3780 : X_LUT4
    generic map(
      INIT => X"7A45"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26072,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(4),
      O => Ucore_Uusb_syn29037
    );
  Ucore_Uusb_C3775 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn26072,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(1),
      O => BLK5_2_GROM
    );
  BLK5_2_XUSED : X_BUF
    port map (
      I => BLK5_2_XORF,
      O => Ucore_Uusb_syn20364
    );
  BLK5_2_YUSED : X_BUF
    port map (
      I => BLK5_2_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C461_C0
    );
  BLK5_2_CYINIT_25 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10881(4),
      O => BLK5_2_CYINIT
    );
  sr0_p124_obuf : X_TRI
    port map (
      I => sr0_p124_OUTMUX,
      CTL => sr0_p124_ENABLE,
      O => sr0_p124
    );
  sr0_p124_ENABLEINV : X_INV
    port map (
      I => sr0_p124_TORGTS,
      O => sr0_p124_ENABLE
    );
  sr0_p124_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr0_p124_TORGTS
    );
  sr0_p124_OUTMUX_26 : X_BUF
    port map (
      I => sr(0),
      O => sr0_p124_OUTMUX
    );
  sr1_p132_obuf : X_TRI
    port map (
      I => sr1_p132_OUTMUX,
      CTL => sr1_p132_ENABLE,
      O => sr1_p132
    );
  sr1_p132_ENABLEINV : X_INV
    port map (
      I => sr1_p132_TORGTS,
      O => sr1_p132_ENABLE
    );
  sr1_p132_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr1_p132_TORGTS
    );
  sr1_p132_OUTMUX_27 : X_BUF
    port map (
      I => sr(1),
      O => sr1_p132_OUTMUX
    );
  vpo_p13_obuf : X_TRI
    port map (
      I => vpo_p13_OUTMUX,
      CTL => vpo_p13_ENABLE,
      O => vpo_p13
    );
  vpo_p13_ENABLEINV : X_INV
    port map (
      I => vpo_p13_TORGTS,
      O => vpo_p13_ENABLE
    );
  vpo_p13_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => vpo_p13_TORGTS
    );
  vpo_p13_OUTMUX_28 : X_BUF
    port map (
      I => vpo_p13_c,
      O => vpo_p13_OUTMUX
    );
  sr2_p133_obuf : X_TRI
    port map (
      I => sr2_p133_OUTMUX,
      CTL => sr2_p133_ENABLE,
      O => sr2_p133
    );
  sr2_p133_ENABLEINV : X_INV
    port map (
      I => sr2_p133_TORGTS,
      O => sr2_p133_ENABLE
    );
  sr2_p133_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr2_p133_TORGTS
    );
  sr2_p133_OUTMUX_29 : X_BUF
    port map (
      I => sr(2),
      O => sr2_p133_OUTMUX
    );
  sr3_p139_obuf : X_TRI
    port map (
      I => sr3_p139_OUTMUX,
      CTL => sr3_p139_ENABLE,
      O => sr3_p139
    );
  sr3_p139_ENABLEINV : X_INV
    port map (
      I => sr3_p139_TORGTS,
      O => sr3_p139_ENABLE
    );
  sr3_p139_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr3_p139_TORGTS
    );
  sr3_p139_OUTMUX_30 : X_BUF
    port map (
      I => sr(3),
      O => sr3_p139_OUTMUX
    );
  sr4_p141_obuf : X_TRI
    port map (
      I => sr4_p141_OUTMUX,
      CTL => sr4_p141_ENABLE,
      O => sr4_p141
    );
  sr4_p141_ENABLEINV : X_INV
    port map (
      I => sr4_p141_TORGTS,
      O => sr4_p141_ENABLE
    );
  sr4_p141_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr4_p141_TORGTS
    );
  sr4_p141_OUTMUX_31 : X_BUF
    port map (
      I => sr(4),
      O => sr4_p141_OUTMUX
    );
  a0_obuf : X_TRI
    port map (
      I => a0_OUTMUX,
      CTL => a0_ENABLE,
      O => a0
    );
  a0_ENABLEINV : X_INV
    port map (
      I => a0_TORGTS,
      O => a0_ENABLE
    );
  a0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a0_TORGTS
    );
  a0_OUTMUX_32 : X_BUF
    port map (
      I => a0_c,
      O => a0_OUTMUX
    );
  a1_obuf : X_TRI
    port map (
      I => a1_OUTMUX,
      CTL => a1_ENABLE,
      O => a1
    );
  a1_ENABLEINV : X_INV
    port map (
      I => a1_TORGTS,
      O => a1_ENABLE
    );
  a1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a1_TORGTS
    );
  a1_OUTMUX_33 : X_BUF
    port map (
      I => a1_c,
      O => a1_OUTMUX
    );
  a2_obuf : X_TRI
    port map (
      I => a2_OUTMUX,
      CTL => a2_ENABLE,
      O => a2
    );
  a2_ENABLEINV : X_INV
    port map (
      I => a2_TORGTS,
      O => a2_ENABLE
    );
  a2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a2_TORGTS
    );
  a2_OUTMUX_34 : X_BUF
    port map (
      I => a2_c,
      O => a2_OUTMUX
    );
  a3_obuf : X_TRI
    port map (
      I => a3_OUTMUX,
      CTL => a3_ENABLE,
      O => a3
    );
  a3_ENABLEINV : X_INV
    port map (
      I => a3_TORGTS,
      O => a3_ENABLE
    );
  a3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a3_TORGTS
    );
  a3_OUTMUX_35 : X_BUF
    port map (
      I => a3_c,
      O => a3_OUTMUX
    );
  a4_obuf : X_TRI
    port map (
      I => a4_OUTMUX,
      CTL => a4_ENABLE,
      O => a4
    );
  a4_ENABLEINV : X_INV
    port map (
      I => a4_TORGTS,
      O => a4_ENABLE
    );
  a4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a4_TORGTS
    );
  a4_OUTMUX_36 : X_BUF
    port map (
      I => a4_c,
      O => a4_OUTMUX
    );
  sr5_p144_obuf : X_TRI
    port map (
      I => sr5_p144_OUTMUX,
      CTL => sr5_p144_ENABLE,
      O => sr5_p144
    );
  sr5_p144_ENABLEINV : X_INV
    port map (
      I => sr5_p144_TORGTS,
      O => sr5_p144_ENABLE
    );
  sr5_p144_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr5_p144_TORGTS
    );
  sr5_p144_OUTMUX_37 : X_BUF
    port map (
      I => sr(5),
      O => sr5_p144_OUTMUX
    );
  a5_obuf : X_TRI
    port map (
      I => a5_OUTMUX,
      CTL => a5_ENABLE,
      O => a5
    );
  a5_ENABLEINV : X_INV
    port map (
      I => a5_TORGTS,
      O => a5_ENABLE
    );
  a5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a5_TORGTS
    );
  a5_OUTMUX_38 : X_BUF
    port map (
      I => a5_c,
      O => a5_OUTMUX
    );
  a6_obuf : X_TRI
    port map (
      I => a6_OUTMUX,
      CTL => a6_ENABLE,
      O => a6
    );
  a6_ENABLEINV : X_INV
    port map (
      I => a6_TORGTS,
      O => a6_ENABLE
    );
  a6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a6_TORGTS
    );
  a6_OUTMUX_39 : X_BUF
    port map (
      I => a6_c,
      O => a6_OUTMUX
    );
  Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GWEAND_40 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FWEAND_41 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU17_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU17_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU17_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N311_RAM32X1_GRAMS
    );
  d0_iobuf_OBUFT : X_TRI
    port map (
      I => d0_OUTMUX,
      CTL => d0_ENABLE,
      O => d0
    );
  d0_ENABLEINV : X_INV
    port map (
      I => d0_TORGTS,
      O => d0_ENABLE
    );
  d0_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d0_TORGTS
    );
  d0_OUTMUX_42 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(0),
      O => d0_OUTMUX
    );
  d0_IMUX : X_BUF
    port map (
      I => d0_IBUF,
      O => d0_in
    );
  d0_iobuf_IBUF : X_BUF
    port map (
      I => d0,
      O => d0_IBUF
    );
  a7_obuf : X_TRI
    port map (
      I => a7_OUTMUX,
      CTL => a7_ENABLE,
      O => a7
    );
  a7_ENABLEINV : X_INV
    port map (
      I => a7_TORGTS,
      O => a7_ENABLE
    );
  a7_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a7_TORGTS
    );
  a7_OUTMUX_43 : X_BUF
    port map (
      I => a7_c,
      O => a7_OUTMUX
    );
  d1_iobuf_OBUFT : X_TRI
    port map (
      I => d1_OUTMUX,
      CTL => d1_ENABLE,
      O => d1
    );
  d1_ENABLEINV : X_INV
    port map (
      I => d1_TORGTS,
      O => d1_ENABLE
    );
  d1_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d1_TORGTS
    );
  d1_OUTMUX_44 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(1),
      O => d1_OUTMUX
    );
  d1_IMUX : X_BUF
    port map (
      I => d1_IBUF,
      O => d1_in
    );
  d1_iobuf_IBUF : X_BUF
    port map (
      I => d1,
      O => d1_IBUF
    );
  a8_obuf : X_TRI
    port map (
      I => a8_OUTMUX,
      CTL => a8_ENABLE,
      O => a8
    );
  a8_ENABLEINV : X_INV
    port map (
      I => a8_TORGTS,
      O => a8_ENABLE
    );
  a8_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a8_TORGTS
    );
  a8_OUTMUX_45 : X_BUF
    port map (
      I => a8_c,
      O => a8_OUTMUX
    );
  d2_iobuf_OBUFT : X_TRI
    port map (
      I => d2_OUTMUX,
      CTL => d2_ENABLE,
      O => d2
    );
  d2_ENABLEINV : X_INV
    port map (
      I => d2_TORGTS,
      O => d2_ENABLE
    );
  d2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d2_TORGTS
    );
  d2_OUTMUX_46 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(2),
      O => d2_OUTMUX
    );
  d2_IMUX : X_BUF
    port map (
      I => d2_IBUF,
      O => d2_in
    );
  d2_iobuf_IBUF : X_BUF
    port map (
      I => d2,
      O => d2_IBUF
    );
  a9_obuf : X_TRI
    port map (
      I => a9_OUTMUX,
      CTL => a9_ENABLE,
      O => a9
    );
  a9_ENABLEINV : X_INV
    port map (
      I => a9_TORGTS,
      O => a9_ENABLE
    );
  a9_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a9_TORGTS
    );
  a9_OUTMUX_47 : X_BUF
    port map (
      I => a9_c,
      O => a9_OUTMUX
    );
  d3_iobuf_OBUFT : X_TRI
    port map (
      I => d3_OUTMUX,
      CTL => d3_ENABLE,
      O => d3
    );
  d3_ENABLEINV : X_INV
    port map (
      I => d3_TORGTS,
      O => d3_ENABLE
    );
  d3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d3_TORGTS
    );
  d3_OUTMUX_48 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(3),
      O => d3_OUTMUX
    );
  d3_IMUX : X_BUF
    port map (
      I => d3_IBUF,
      O => d3_in
    );
  d3_iobuf_IBUF : X_BUF
    port map (
      I => d3,
      O => d3_IBUF
    );
  d4_iobuf_OBUFT : X_TRI
    port map (
      I => d4_OUTMUX,
      CTL => d4_ENABLE,
      O => d4
    );
  d4_ENABLEINV : X_INV
    port map (
      I => d4_TORGTS,
      O => d4_ENABLE
    );
  d4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d4_TORGTS
    );
  d4_OUTMUX_49 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(4),
      O => d4_OUTMUX
    );
  d4_IMUX : X_BUF
    port map (
      I => d4_IBUF,
      O => d4_in
    );
  d4_iobuf_IBUF : X_BUF
    port map (
      I => d4,
      O => d4_IBUF
    );
  d5_iobuf_OBUFT : X_TRI
    port map (
      I => d5_OUTMUX,
      CTL => d5_ENABLE,
      O => d5
    );
  d5_ENABLEINV : X_INV
    port map (
      I => d5_TORGTS,
      O => d5_ENABLE
    );
  d5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d5_TORGTS
    );
  d5_OUTMUX_50 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(5),
      O => d5_OUTMUX
    );
  d5_IMUX : X_BUF
    port map (
      I => d5_IBUF,
      O => d5_in
    );
  d5_iobuf_IBUF : X_BUF
    port map (
      I => d5,
      O => d5_IBUF
    );
  d6_iobuf_OBUFT : X_TRI
    port map (
      I => d6_OUTMUX,
      CTL => d6_ENABLE,
      O => d6
    );
  d6_ENABLEINV : X_INV
    port map (
      I => d6_TORGTS,
      O => d6_ENABLE
    );
  d6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d6_TORGTS
    );
  d6_OUTMUX_51 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(6),
      O => d6_OUTMUX
    );
  d6_IMUX : X_BUF
    port map (
      I => d6_IBUF,
      O => d6_in
    );
  d6_iobuf_IBUF : X_BUF
    port map (
      I => d6,
      O => d6_IBUF
    );
  d7_iobuf_OBUFT : X_TRI
    port map (
      I => d7_OUTMUX,
      CTL => d7_ENABLE,
      O => d7
    );
  d7_ENABLEINV : X_INV
    port map (
      I => d7_TORGTS,
      O => d7_ENABLE
    );
  d7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d7_TORGTS
    );
  d7_OUTMUX_52 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(7),
      O => d7_OUTMUX
    );
  d7_IMUX : X_BUF
    port map (
      I => d7_IBUF,
      O => d7_in
    );
  d7_iobuf_IBUF : X_BUF
    port map (
      I => d7,
      O => d7_IBUF
    );
  d8_iobuf_OBUFT : X_TRI
    port map (
      I => d8_OUTMUX,
      CTL => d8_ENABLE,
      O => d8
    );
  d8_ENABLEINV : X_INV
    port map (
      I => d8_TORGTS,
      O => d8_ENABLE
    );
  d8_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d8_TORGTS
    );
  d8_OUTMUX_53 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(8),
      O => d8_OUTMUX
    );
  d8_IMUX : X_BUF
    port map (
      I => d8_IBUF,
      O => d8_in
    );
  d8_iobuf_IBUF : X_BUF
    port map (
      I => d8,
      O => d8_IBUF
    );
  d9_iobuf_OBUFT : X_TRI
    port map (
      I => d9_OUTMUX,
      CTL => d9_ENABLE,
      O => d9
    );
  d9_ENABLEINV : X_INV
    port map (
      I => d9_TORGTS,
      O => d9_ENABLE
    );
  d9_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d9_TORGTS
    );
  d9_OUTMUX_54 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(9),
      O => d9_OUTMUX
    );
  d9_IMUX : X_BUF
    port map (
      I => d9_IBUF,
      O => d9_in
    );
  d9_iobuf_IBUF : X_BUF
    port map (
      I => d9,
      O => d9_IBUF
    );
  sr6_p147_obuf : X_TRI
    port map (
      I => sr6_p147_OUTMUX,
      CTL => sr6_p147_ENABLE,
      O => sr6_p147
    );
  sr6_p147_ENABLEINV : X_INV
    port map (
      I => sr6_p147_TORGTS,
      O => sr6_p147_ENABLE
    );
  sr6_p147_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sr6_p147_TORGTS
    );
  sr6_p147_OUTMUX_55 : X_BUF
    port map (
      I => sr(6),
      O => sr6_p147_OUTMUX
    );
  suspnd_p176_LOGIC_ZERO_56 : X_ZERO
    port map (
      O => suspnd_p176_LOGIC_ZERO
    );
  suspnd_p176_obuf : X_TRI
    port map (
      I => suspnd_p176_OUTMUX,
      CTL => suspnd_p176_ENABLE,
      O => suspnd_p176
    );
  suspnd_p176_ENABLEINV : X_INV
    port map (
      I => suspnd_p176_TORGTS,
      O => suspnd_p176_ENABLE
    );
  suspnd_p176_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => suspnd_p176_TORGTS
    );
  suspnd_p176_OUTMUX_57 : X_BUF
    port map (
      I => suspnd_p176_LOGIC_ZERO,
      O => suspnd_p176_OUTMUX
    );
  vm_p9_IMUX : X_BUF
    port map (
      I => vm_p9_IBUF,
      O => vm_p9_c
    );
  vm_p9_ibuf_58 : X_BUF
    port map (
      I => vm_p9,
      O => vm_p9_IBUF
    );
  sw1_p174_IMUX : X_BUF
    port map (
      I => sw1_p174_IBUF,
      O => sw1_p174_c
    );
  sw1_p174_ibuf_59 : X_BUF
    port map (
      I => sw1_p174,
      O => sw1_p174_IBUF
    );
  oe_p12_obuf : X_TRI
    port map (
      I => oe_p12_OUTMUX,
      CTL => oe_p12_ENABLE,
      O => oe_p12
    );
  oe_p12_ENABLEINV : X_INV
    port map (
      I => oe_p12_TORGTS,
      O => oe_p12_ENABLE
    );
  oe_p12_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_p12_TORGTS
    );
  oe_p12_OUTMUX_60 : X_BUF
    port map (
      I => oe_p12_ODNOT,
      O => oe_p12_OUTMUX
    );
  oe_p12_OMUX : X_INV
    port map (
      I => Ucore_utxoe,
      O => oe_p12_ODNOT
    );
  a10_obuf : X_TRI
    port map (
      I => a10_OUTMUX,
      CTL => a10_ENABLE,
      O => a10
    );
  a10_ENABLEINV : X_INV
    port map (
      I => a10_TORGTS,
      O => a10_ENABLE
    );
  a10_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a10_TORGTS
    );
  a10_OUTMUX_61 : X_BUF
    port map (
      I => a10_c,
      O => a10_OUTMUX
    );
  a11_obuf : X_TRI
    port map (
      I => a11_OUTMUX,
      CTL => a11_ENABLE,
      O => a11
    );
  a11_ENABLEINV : X_INV
    port map (
      I => a11_TORGTS,
      O => a11_ENABLE
    );
  a11_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a11_TORGTS
    );
  a11_OUTMUX_62 : X_BUF
    port map (
      I => a11_c,
      O => a11_OUTMUX
    );
  a12_obuf : X_TRI
    port map (
      I => a12_OUTMUX,
      CTL => a12_ENABLE,
      O => a12
    );
  a12_ENABLEINV : X_INV
    port map (
      I => a12_TORGTS,
      O => a12_ENABLE
    );
  a12_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a12_TORGTS
    );
  a12_OUTMUX_63 : X_BUF
    port map (
      I => a12_c,
      O => a12_OUTMUX
    );
  a13_obuf : X_TRI
    port map (
      I => a13_OUTMUX,
      CTL => a13_ENABLE,
      O => a13
    );
  a13_ENABLEINV : X_INV
    port map (
      I => a13_TORGTS,
      O => a13_ENABLE
    );
  a13_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a13_TORGTS
    );
  a13_OUTMUX_64 : X_BUF
    port map (
      I => a13_c,
      O => a13_OUTMUX
    );
  a14_obuf : X_TRI
    port map (
      I => a14_OUTMUX,
      CTL => a14_ENABLE,
      O => a14
    );
  a14_ENABLEINV : X_INV
    port map (
      I => a14_TORGTS,
      O => a14_ENABLE
    );
  a14_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a14_TORGTS
    );
  a14_OUTMUX_65 : X_BUF
    port map (
      I => a14_c,
      O => a14_OUTMUX
    );
  a15_obuf : X_TRI
    port map (
      I => a15_OUTMUX,
      CTL => a15_ENABLE,
      O => a15
    );
  a15_ENABLEINV : X_INV
    port map (
      I => a15_TORGTS,
      O => a15_ENABLE
    );
  a15_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a15_TORGTS
    );
  a15_OUTMUX_66 : X_BUF
    port map (
      I => a15_c,
      O => a15_OUTMUX
    );
  a16_obuf : X_TRI
    port map (
      I => a16_OUTMUX,
      CTL => a16_ENABLE,
      O => a16
    );
  a16_ENABLEINV : X_INV
    port map (
      I => a16_TORGTS,
      O => a16_ENABLE
    );
  a16_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a16_TORGTS
    );
  a16_OUTMUX_67 : X_BUF
    port map (
      I => a16_c,
      O => a16_OUTMUX
    );
  a17_obuf : X_TRI
    port map (
      I => a17_OUTMUX,
      CTL => a17_ENABLE,
      O => a17
    );
  a17_ENABLEINV : X_INV
    port map (
      I => a17_TORGTS,
      O => a17_ENABLE
    );
  a17_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a17_TORGTS
    );
  a17_OUTMUX_68 : X_BUF
    port map (
      I => a17_c,
      O => a17_OUTMUX
    );
  Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GWEAND_69 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FWEAND_70 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU9_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU9_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU9_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N228_RAM32X1_GRAMS
    );
  a18_obuf : X_TRI
    port map (
      I => a18_OUTMUX,
      CTL => a18_ENABLE,
      O => a18
    );
  a18_ENABLEINV : X_INV
    port map (
      I => a18_TORGTS,
      O => a18_ENABLE
    );
  a18_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => a18_TORGTS
    );
  a18_OUTMUX_71 : X_BUF
    port map (
      I => a18_c,
      O => a18_OUTMUX
    );
  d10_iobuf_OBUFT : X_TRI
    port map (
      I => d10_OUTMUX,
      CTL => d10_ENABLE,
      O => d10
    );
  d10_ENABLEINV : X_INV
    port map (
      I => d10_TORGTS,
      O => d10_ENABLE
    );
  d10_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d10_TORGTS
    );
  d10_OUTMUX_72 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(10),
      O => d10_OUTMUX
    );
  d10_IMUX : X_BUF
    port map (
      I => d10_IBUF,
      O => d10_in
    );
  d10_iobuf_IBUF : X_BUF
    port map (
      I => d10,
      O => d10_IBUF
    );
  d11_iobuf_OBUFT : X_TRI
    port map (
      I => d11_OUTMUX,
      CTL => d11_ENABLE,
      O => d11
    );
  d11_ENABLEINV : X_INV
    port map (
      I => d11_TORGTS,
      O => d11_ENABLE
    );
  d11_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d11_TORGTS
    );
  d11_OUTMUX_73 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(11),
      O => d11_OUTMUX
    );
  d11_IMUX : X_BUF
    port map (
      I => d11_IBUF,
      O => d11_in
    );
  d11_iobuf_IBUF : X_BUF
    port map (
      I => d11,
      O => d11_IBUF
    );
  d12_iobuf_OBUFT : X_TRI
    port map (
      I => d12_OUTMUX,
      CTL => d12_ENABLE,
      O => d12
    );
  d12_ENABLEINV : X_INV
    port map (
      I => d12_TORGTS,
      O => d12_ENABLE
    );
  d12_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d12_TORGTS
    );
  d12_OUTMUX_74 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(12),
      O => d12_OUTMUX
    );
  d12_IMUX : X_BUF
    port map (
      I => d12_IBUF,
      O => d12_in
    );
  d12_iobuf_IBUF : X_BUF
    port map (
      I => d12,
      O => d12_IBUF
    );
  d13_iobuf_OBUFT : X_TRI
    port map (
      I => d13_OUTMUX,
      CTL => d13_ENABLE,
      O => d13
    );
  d13_ENABLEINV : X_INV
    port map (
      I => d13_TORGTS,
      O => d13_ENABLE
    );
  d13_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d13_TORGTS
    );
  d13_OUTMUX_75 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(13),
      O => d13_OUTMUX
    );
  d13_IMUX : X_BUF
    port map (
      I => d13_IBUF,
      O => d13_in
    );
  d13_iobuf_IBUF : X_BUF
    port map (
      I => d13,
      O => d13_IBUF
    );
  d14_iobuf_OBUFT : X_TRI
    port map (
      I => d14_OUTMUX,
      CTL => d14_ENABLE,
      O => d14
    );
  d14_ENABLEINV : X_INV
    port map (
      I => d14_TORGTS,
      O => d14_ENABLE
    );
  d14_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d14_TORGTS
    );
  d14_OUTMUX_76 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(14),
      O => d14_OUTMUX
    );
  d14_IMUX : X_BUF
    port map (
      I => d14_IBUF,
      O => d14_in
    );
  d14_iobuf_IBUF : X_BUF
    port map (
      I => d14,
      O => d14_IBUF
    );
  d15_iobuf_OBUFT : X_TRI
    port map (
      I => d15_OUTMUX,
      CTL => d15_ENABLE,
      O => d15
    );
  d15_ENABLEINV : X_INV
    port map (
      I => d15_TORGTS,
      O => d15_ENABLE
    );
  d15_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => un3_doingwrite1_n,
      O => d15_TORGTS
    );
  d15_OUTMUX_77 : X_BUF
    port map (
      I => Ucore_Ufunc_sram_writedatareg(15),
      O => d15_OUTMUX
    );
  d15_IMUX : X_BUF
    port map (
      I => d15_IBUF,
      O => d15_in
    );
  d15_iobuf_IBUF : X_BUF
    port map (
      I => d15,
      O => d15_IBUF
    );
  fse0_p17_obuf : X_TRI
    port map (
      I => fse0_p17_OUTMUX,
      CTL => fse0_p17_ENABLE,
      O => fse0_p17
    );
  fse0_p17_ENABLEINV : X_INV
    port map (
      I => fse0_p17_TORGTS,
      O => fse0_p17_ENABLE
    );
  fse0_p17_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => fse0_p17_TORGTS
    );
  fse0_p17_OUTMUX_78 : X_BUF
    port map (
      I => fse0_p17_c,
      O => fse0_p17_OUTMUX
    );
  ram_ce_LOGIC_ZERO_79 : X_ZERO
    port map (
      O => ram_ce_LOGIC_ZERO
    );
  ram_ce_obuf : X_TRI
    port map (
      I => ram_ce_OUTMUX,
      CTL => ram_ce_ENABLE,
      O => ram_ce
    );
  ram_ce_ENABLEINV : X_INV
    port map (
      I => ram_ce_TORGTS,
      O => ram_ce_ENABLE
    );
  ram_ce_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ram_ce_TORGTS
    );
  ram_ce_OUTMUX_80 : X_BUF
    port map (
      I => ram_ce_c,
      O => ram_ce_OUTMUX
    );
  ram_ce_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => ram_ce_SRMUXNOT
    );
  sl0_p177_obuf : X_TRI
    port map (
      I => sl0_p177_OUTMUX,
      CTL => sl0_p177_ENABLE,
      O => sl0_p177
    );
  sl0_p177_ENABLEINV : X_INV
    port map (
      I => sl0_p177_TORGTS,
      O => sl0_p177_ENABLE
    );
  sl0_p177_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl0_p177_TORGTS
    );
  sl0_p177_OUTMUX_81 : X_BUF
    port map (
      I => sl(0),
      O => sl0_p177_OUTMUX
    );
  ram_oe_obuf : X_TRI
    port map (
      I => ram_oe_OUTMUX,
      CTL => ram_oe_ENABLE,
      O => ram_oe
    );
  ram_oe_ENABLEINV : X_INV
    port map (
      I => ram_oe_TORGTS,
      O => ram_oe_ENABLE
    );
  ram_oe_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ram_oe_TORGTS
    );
  ram_oe_OUTMUX_82 : X_BUF
    port map (
      I => ram_oe_c,
      O => ram_oe_OUTMUX
    );
  ram_we_obuf : X_TRI
    port map (
      I => ram_we_OUTMUX,
      CTL => ram_we_ENABLE,
      O => ram_we
    );
  ram_we_ENABLEINV : X_INV
    port map (
      I => ram_we_TORGTS,
      O => ram_we_ENABLE
    );
  ram_we_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ram_we_TORGTS
    );
  ram_we_OUTMUX_83 : X_BUF
    port map (
      I => ram_we_c,
      O => ram_we_OUTMUX
    );
  sl1_p167_obuf : X_TRI
    port map (
      I => sl1_p167_OUTMUX,
      CTL => sl1_p167_ENABLE,
      O => sl1_p167
    );
  sl1_p167_ENABLEINV : X_INV
    port map (
      I => sl1_p167_TORGTS,
      O => sl1_p167_ENABLE
    );
  sl1_p167_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl1_p167_TORGTS
    );
  sl1_p167_OUTMUX_84 : X_BUF
    port map (
      I => sl(1),
      O => sl1_p167_OUTMUX
    );
  sl2_p163_obuf : X_TRI
    port map (
      I => sl2_p163_OUTMUX,
      CTL => sl2_p163_ENABLE,
      O => sl2_p163
    );
  sl2_p163_ENABLEINV : X_INV
    port map (
      I => sl2_p163_TORGTS,
      O => sl2_p163_ENABLE
    );
  sl2_p163_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl2_p163_TORGTS
    );
  sl2_p163_OUTMUX_85 : X_BUF
    port map (
      I => sl(2),
      O => sl2_p163_OUTMUX
    );
  sl3_p156_obuf : X_TRI
    port map (
      I => sl3_p156_OUTMUX,
      CTL => sl3_p156_ENABLE,
      O => sl3_p156
    );
  sl3_p156_ENABLEINV : X_INV
    port map (
      I => sl3_p156_TORGTS,
      O => sl3_p156_ENABLE
    );
  sl3_p156_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl3_p156_TORGTS
    );
  sl3_p156_OUTMUX_86 : X_BUF
    port map (
      I => sl(3),
      O => sl3_p156_OUTMUX
    );
  sl4_p145_obuf : X_TRI
    port map (
      I => sl4_p145_OUTMUX,
      CTL => sl4_p145_ENABLE,
      O => sl4_p145
    );
  sl4_p145_ENABLEINV : X_INV
    port map (
      I => sl4_p145_TORGTS,
      O => sl4_p145_ENABLE
    );
  sl4_p145_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl4_p145_TORGTS
    );
  sl4_p145_OUTMUX_87 : X_BUF
    port map (
      I => sl(4),
      O => sl4_p145_OUTMUX
    );
  vp_p10_IMUX : X_BUF
    port map (
      I => vp_p10_IBUF,
      O => vp_p10_c
    );
  vp_p10_ibuf_88 : X_BUF
    port map (
      I => vp_p10,
      O => vp_p10_IBUF
    );
  sl5_p138_obuf : X_TRI
    port map (
      I => sl5_p138_OUTMUX,
      CTL => sl5_p138_ENABLE,
      O => sl5_p138
    );
  sl5_p138_ENABLEINV : X_INV
    port map (
      I => sl5_p138_TORGTS,
      O => sl5_p138_ENABLE
    );
  sl5_p138_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl5_p138_TORGTS
    );
  sl5_p138_OUTMUX_89 : X_BUF
    port map (
      I => sl(5),
      O => sl5_p138_OUTMUX
    );
  sl6_p134_obuf : X_TRI
    port map (
      I => sl6_p134_OUTMUX,
      CTL => sl6_p134_ENABLE,
      O => sl6_p134
    );
  sl6_p134_ENABLEINV : X_INV
    port map (
      I => sl6_p134_TORGTS,
      O => sl6_p134_ENABLE
    );
  sl6_p134_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sl6_p134_TORGTS
    );
  sl6_p134_OUTMUX_90 : X_BUF
    port map (
      I => sl(6),
      O => sl6_p134_OUTMUX
    );
  Udll_dll_RSTMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Udll_dll_RST_INTERNALNOT
    );
  Udll_dll : X_CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0,
      DUTY_CYCLE_CORRECTION => TRUE,
      MAXPERCLKIN => 40000 ps
    )
    port map (
      RST => Udll_dll_RST_INTERNALNOT,
      CLK0 => Udll_CLK0_dll,
      CLK180 => Udll_dll_CLK180,
      CLK270 => Udll_dll_CLK270,
      CLK2X => Udll_dll_CLK2X,
      CLK90 => Udll_CLK2X_dll,
      CLKDV => Udll_dll_CLKDV,
      CLKFB => clk48,
      CLKIN => Udll_CLKIN_w,
      LOCKED => Udll_dll_LOCKED
    );
  Ucore_Uusb_C2630_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2630 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(4),
      CTL => Ucore_Uusb_C2630_TINV,
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2630_TINV_91 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2630_TINV
    );
  Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GWEAND_92 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FWEAND_93 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU25_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU25_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU25_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(5),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N394_RAM32X1_GRAMS
    );
  Ucore_Uusb_C2631_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2631 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(6),
      CTL => Ucore_Uusb_C2631_TINV,
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2631_TINV_94 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2631_TINV
    );
  Ucore_Uusb_C2640_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2640 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(4),
      CTL => Ucore_Uusb_C2640_TINV,
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2640_TINV_95 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2640_TINV
    );
  Ucore_Uusb_C2632_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2632 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(2),
      CTL => Ucore_Uusb_C2632_TINV,
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2632_TINV_96 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2632_TINV
    );
  Ucore_Uusb_C2641_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2641 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_0_Q,
      CTL => Ucore_Uusb_C2641_TINV,
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2641_TINV_97 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2641_TINV
    );
  Ucore_Uusb_C2633_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2633 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_6_Q,
      CTL => Ucore_Uusb_C2633_TINV,
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2633_TINV_98 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2633_TINV
    );
  Ucore_Uusb_C2650_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2650 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(5),
      CTL => Ucore_Uusb_C2650_TINV,
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2650_TINV_99 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2650_TINV
    );
  Ucore_Uusb_C2642_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2642 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N24,
      CTL => Ucore_Uusb_C2642_TINV,
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2642_TINV_100 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2642_TINV
    );
  Ucore_Uusb_C2634_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2634 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(2),
      CTL => Ucore_Uusb_C2634_TINV,
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2634_TINV_101 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2634_TINV
    );
  Ucore_Uusb_C2651_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2651 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(7),
      CTL => Ucore_Uusb_C2651_TINV,
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2651_TINV_102 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2651_TINV
    );
  Ucore_Uusb_C2643_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2643 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(0),
      CTL => Ucore_Uusb_C2643_TINV,
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2643_TINV_103 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2643_TINV
    );
  Ucore_Uusb_C2635_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2635 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N12,
      CTL => Ucore_Uusb_C2635_TINV,
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2635_TINV_104 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2635_TINV
    );
  Ucore_Uusb_C2660_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2660 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(1),
      CTL => Ucore_Uusb_C2660_TINV,
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2660_TINV_105 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2660_TINV
    );
  Ucore_Uusb_C2652_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2652 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_3_Q,
      CTL => Ucore_Uusb_C2652_TINV,
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2652_TINV_106 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2652_TINV
    );
  Ucore_Uusb_C2644_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2644 : X_TRI
    port map (
      I => GLOBAL_LOGIC0_4,
      CTL => Ucore_Uusb_C2644_TINV,
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2644_TINV_107 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2644_TINV
    );
  Ucore_Uusb_C2636_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2636 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(6),
      CTL => Ucore_Uusb_C2636_TINV,
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2636_TINV_108 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2636_TINV
    );
  Ucore_Uusb_C2661_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(4)
    );
  Ucore_Uusb_C2661 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(4),
      CTL => Ucore_Uusb_C2661_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(4)
    );
  Ucore_Uusb_C2661_TINV_109 : X_INV
    port map (
      I => Ucore_Uusb_C2661_TMUXNOT,
      O => Ucore_Uusb_C2661_TINV
    );
  Ucore_Uusb_C2661_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2661_TMUXNOT
    );
  Ucore_Uusb_C2653_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2653 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N30,
      CTL => Ucore_Uusb_C2653_TINV,
      O => Ucore_Uusb_BUS1614(4)
    );
  Ucore_Uusb_C2653_TINV_110 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2653_TINV
    );
  Ucore_Uusb_C2645_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2645 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N18,
      CTL => Ucore_Uusb_C2645_TINV,
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2645_TINV_111 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2645_TINV
    );
  Ucore_Uusb_C2637_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2637 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_2_Q,
      CTL => Ucore_Uusb_C2637_TINV,
      O => Ucore_Uusb_BUS1614(2)
    );
  Ucore_Uusb_C2637_TINV_112 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2637_TINV
    );
  Ucore_Uusb_C2629_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2629 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(0),
      CTL => Ucore_Uusb_C2629_TINV,
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2629_TINV_113 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2629_TINV
    );
  Ucore_Uusb_C2662_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(0)
    );
  Ucore_Uusb_C2662 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(0),
      CTL => Ucore_Uusb_C2662_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(0)
    );
  Ucore_Uusb_C2662_TINV_114 : X_INV
    port map (
      I => Ucore_Uusb_C2662_TMUXNOT,
      O => Ucore_Uusb_C2662_TINV
    );
  Ucore_Uusb_C2662_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2662_TMUXNOT
    );
  Ucore_Uusb_C2654_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2654 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_7_Q,
      CTL => Ucore_Uusb_C2654_TINV,
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2654_TINV_115 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2654_TINV
    );
  Ucore_Uusb_C2646_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2646 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(1),
      CTL => Ucore_Uusb_C2646_TINV,
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2646_TINV_116 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2646_TINV
    );
  Ucore_Uusb_C2638_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2638 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N36,
      CTL => Ucore_Uusb_C2638_TINV,
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2638_TINV_117 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2638_TINV
    );
  Ucore_Uusb_C2663_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(2)
    );
  Ucore_Uusb_C2663 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(2),
      CTL => Ucore_Uusb_C2663_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(2)
    );
  Ucore_Uusb_C2663_TINV_118 : X_INV
    port map (
      I => Ucore_Uusb_C2663_TMUXNOT,
      O => Ucore_Uusb_C2663_TINV
    );
  Ucore_Uusb_C2663_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2663_TMUXNOT
    );
  Ucore_Uusb_C2655_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2655 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(3),
      CTL => Ucore_Uusb_C2655_TINV,
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2655_TINV_119 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N31,
      O => Ucore_Uusb_C2655_TINV
    );
  Ucore_Uusb_C2647_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2647 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_5_Q,
      CTL => Ucore_Uusb_C2647_TINV,
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2647_TINV_120 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2647_TINV
    );
  Ucore_Uusb_C2639_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2639 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N48,
      CTL => Ucore_Uusb_C2639_TINV,
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2639_TINV_121 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2639_TINV
    );
  Ucore_Uusb_C2664_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(6)
    );
  Ucore_Uusb_C2664 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(6),
      CTL => Ucore_Uusb_C2664_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(6)
    );
  Ucore_Uusb_C2664_TINV_122 : X_INV
    port map (
      I => Ucore_Uusb_C2664_TMUXNOT,
      O => Ucore_Uusb_C2664_TINV
    );
  Ucore_Uusb_C2664_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2664_TMUXNOT
    );
  Ucore_Uusb_C2656_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2656 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N6,
      CTL => Ucore_Uusb_C2656_TINV,
      O => Ucore_Uusb_BUS1614(0)
    );
  Ucore_Uusb_C2656_TINV_123 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2656_TINV
    );
  Ucore_Uusb_C2648_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2648 : X_TRI
    port map (
      I => Ucore_Uusb_Uglue_C36_N42,
      CTL => Ucore_Uusb_C2648_TINV,
      O => Ucore_Uusb_BUS1614(6)
    );
  Ucore_Uusb_C2648_TINV_124 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N101,
      O => Ucore_Uusb_C2648_TINV
    );
  Ucore_Uusb_C2665_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(7)
    );
  Ucore_Uusb_C2665 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(7),
      CTL => Ucore_Uusb_C2665_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(7)
    );
  Ucore_Uusb_C2665_TINV_125 : X_INV
    port map (
      I => Ucore_Uusb_C2665_TMUXNOT,
      O => Ucore_Uusb_C2665_TINV
    );
  Ucore_Uusb_C2665_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2665_TMUXNOT
    );
  Ucore_Uusb_C2657_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2657 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(3),
      CTL => Ucore_Uusb_C2657_TINV,
      O => Ucore_Uusb_BUS1614(3)
    );
  Ucore_Uusb_C2657_TINV_126 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2657_TINV
    );
  Ucore_Uusb_C2649_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2649 : X_TRI
    port map (
      I => Ucore_Uusb_BUS126_1_Q,
      CTL => Ucore_Uusb_C2649_TINV,
      O => Ucore_Uusb_BUS1614(1)
    );
  Ucore_Uusb_C2649_TINV_127 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N33,
      O => Ucore_Uusb_C2649_TINV
    );
  Ucore_Uusb_C2666_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(3)
    );
  Ucore_Uusb_C2666 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(3),
      CTL => Ucore_Uusb_C2666_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(3)
    );
  Ucore_Uusb_C2666_TINV_128 : X_INV
    port map (
      I => Ucore_Uusb_C2666_TMUXNOT,
      O => Ucore_Uusb_C2666_TINV
    );
  Ucore_Uusb_C2666_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2666_TMUXNOT
    );
  Ucore_Uusb_C2658_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2658 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(7),
      CTL => Ucore_Uusb_C2658_TINV,
      O => Ucore_Uusb_BUS1614(7)
    );
  Ucore_Uusb_C2658_TINV_129 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2658_TINV
    );
  Ucore_Uusb_C2667_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(1)
    );
  Ucore_Uusb_C2667 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(1),
      CTL => Ucore_Uusb_C2667_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(1)
    );
  Ucore_Uusb_C2667_TINV_130 : X_INV
    port map (
      I => Ucore_Uusb_C2667_TMUXNOT,
      O => Ucore_Uusb_C2667_TINV
    );
  Ucore_Uusb_C2667_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2667_TMUXNOT
    );
  Ucore_Uusb_C2659_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2659 : X_TRI
    port map (
      I => Ucore_Uusb_BUS206(5),
      CTL => Ucore_Uusb_C2659_TINV,
      O => Ucore_Uusb_BUS1614(5)
    );
  Ucore_Uusb_C2659_TINV_131 : X_INV
    port map (
      I => Ucore_Uusb_Uglue_N37,
      O => Ucore_Uusb_C2659_TINV
    );
  Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GWEAND_132 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FWEAND_133 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU16_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU16_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU16_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N310_RAM32X1_GRAMS
    );
  Ucore_Uusb_C2668_PULLUP : X_PU
    port map (
      O => Ucore_Uusb_Uusb_BUS8585(5)
    );
  Ucore_Uusb_C2668 : X_TRI
    port map (
      I => Ucore_Uusb_Uusb_BUS63(5),
      CTL => Ucore_Uusb_C2668_TINV,
      O => Ucore_Uusb_Uusb_BUS8585(5)
    );
  Ucore_Uusb_C2668_TINV_134 : X_INV
    port map (
      I => Ucore_Uusb_C2668_TMUXNOT,
      O => Ucore_Uusb_C2668_TINV
    );
  Ucore_Uusb_C2668_TMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_in_trac(0),
      O => Ucore_Uusb_C2668_TMUXNOT
    );
  Ucore_Uusb_Urom_Urom_BU0_LOGIC_ONE_135 : X_ONE
    port map (
      O => Ucore_Uusb_Urom_Urom_BU0_LOGIC_ONE
    );
  Ucore_Uusb_Urom_Urom_BU0_LOGIC_ZERO_136 : X_ZERO
    port map (
      O => Ucore_Uusb_Urom_Urom_BU0_LOGIC_ZERO
    );
  Ucore_Uusb_Urom_Urom_BU0 : X_RAMB4_S4
    generic map(
      INIT_00 => X"F0280015F4031543434250201202090C42272000020702A04040000000004015",
      INIT_01 => X"8888880F888888888288888A888888FA8548888523520252501223020F028000",
      INIT_02 => X"214012D04804304030041214085000B120950200888888488888881888888888",
      INIT_03 => X"4000D22012B04601430300B121950200B12850200B1200000200E1295E1204E1",
      INIT_04 => X"4920904B20F0492050520020091224D2091224B202004000522F04B004000000",
      INIT_05 => X"25841525401532525025600F42007004353251591264F2091294F209120B2030",
      INIT_06 => X"0D02542563552530365255435325303452356355250007525150425156025315",
      INIT_07 => X"000D12004000D120040004122400430000622412046015904B00400000047500",
      INIT_08 => X"01012B002530150002503150000F024025301500025031500002004000A04040",
      INIT_09 => X"50F60529191119F06408315706210101940031004920311022910211010B0800",
      INIT_0A => X"5043E03090E0F020403050C05000A0E05020432493402125850F605291921258",
      INIT_0B => X"C000D010805000409083805040F0E000E0F09040103090C000001320203050D0",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000050",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      CLK => Ucore_Uusb_CLK24,
      EN => Ucore_Uusb_Urom_Urom_BU0_LOGIC_ONE,
      RST => Ucore_Uusb_Urom_Urom_BU0_LOGIC_ZERO,
      WE => Ucore_Uusb_Urom_Urom_BU0_LOGIC_ZERO,
      GSR => GSR,
      ADDR(9) => Ucore_Uusb_BUS1610_9_Q,
      ADDR(8) => Ucore_Uusb_BUS1610_8_Q,
      ADDR(7) => Ucore_Uusb_BUS1610_7_Q,
      ADDR(6) => Ucore_Uusb_BUS1610_6_Q,
      ADDR(5) => Ucore_Uusb_BUS1610_5_Q,
      ADDR(4) => Ucore_Uusb_BUS1610_4_Q,
      ADDR(3) => Ucore_Uusb_BUS1610_3_Q,
      ADDR(2) => Ucore_Uusb_BUS141(2),
      ADDR(1) => Ucore_Uusb_BUS141(1),
      ADDR(0) => Ucore_Uusb_BUS141(0),
      DI(3) => GLOBAL_LOGIC0_0,
      DI(2) => GLOBAL_LOGIC0,
      DI(1) => GLOBAL_LOGIC0_0,
      DI(0) => GLOBAL_LOGIC0,
      DO(3) => Ucore_Uusb_BUS206(3),
      DO(2) => Ucore_Uusb_BUS206(2),
      DO(1) => Ucore_Uusb_BUS206(1),
      DO(0) => Ucore_Uusb_BUS206(0)
    );
  Ucore_Uusb_Urom_Urom_BU1_LOGIC_ONE_137 : X_ONE
    port map (
      O => Ucore_Uusb_Urom_Urom_BU1_LOGIC_ONE
    );
  Ucore_Uusb_Urom_Urom_BU1_LOGIC_ZERO_138 : X_ZERO
    port map (
      O => Ucore_Uusb_Urom_Urom_BU1_LOGIC_ZERO
    );
  Ucore_Uusb_Urom_Urom_BU1 : X_RAMB4_S4
    generic map(
      INIT_00 => X"4015092405EA2FC05070E324E8EAE275509EAE0E9F8101F8BE5E0D9F0C907787",
      INIT_01 => X"BBBB8B46BBBBBBBBB9BBBBB6BBBBBB74B57BBBB6280058F8210028C8C401509E",
      INIT_02 => X"007100661661661E0E9F0007F2E0E9E00027E0E9BBBBBBABBBBBBBABBBBBBBBB",
      INIT_03 => X"70D90001005615629CE0E9E00027E0E9E002FE0E9E00F0C9E0E9D002ED0007D0",
      INIT_04 => X"1C09061B0906190916909E0E950027409500173092F170D9200E2BF6E5E0D9F4",
      INIT_05 => X"2F072F2E0529C2F24E2F0E9F706E0E92882882F5002760950007509500EE0906",
      INIT_06 => X"9D72F12E288288AF828828288288AE8288282882880E92F2E2F072F2E0529C2E",
      INIT_07 => X"0D9F00F840D9F00F470D9F0007F07AF0E9000F0007A72E04BF6E5E0D9F842E0D",
      INIT_08 => X"00101C8F2EAF2E0F92FEA2FE0E9C807F2EAF2E0E92FEA2FE0F92F270D9F2BE5E",
      INIT_09 => X"70F20102010A00F006000800022000020000000000380000200000000000D000",
      INIT_0A => X"4050006060606070706060604020706060705020000C0909070F201020108090",
      INIT_0B => X"6070606070402040404010607060402060606070606060607070402040505020",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000060",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      CLK => Ucore_Uusb_CLK24,
      EN => Ucore_Uusb_Urom_Urom_BU1_LOGIC_ONE,
      RST => Ucore_Uusb_Urom_Urom_BU1_LOGIC_ZERO,
      WE => Ucore_Uusb_Urom_Urom_BU1_LOGIC_ZERO,
      GSR => GSR,
      ADDR(9) => Ucore_Uusb_BUS1610_9_Q,
      ADDR(8) => Ucore_Uusb_BUS1610_8_Q,
      ADDR(7) => Ucore_Uusb_BUS1610_7_Q,
      ADDR(6) => Ucore_Uusb_BUS1610_6_Q,
      ADDR(5) => Ucore_Uusb_BUS1610_5_Q,
      ADDR(4) => Ucore_Uusb_BUS1610_4_Q,
      ADDR(3) => Ucore_Uusb_BUS1610_3_Q,
      ADDR(2) => Ucore_Uusb_BUS141(2),
      ADDR(1) => Ucore_Uusb_BUS141(1),
      ADDR(0) => Ucore_Uusb_BUS141(0),
      DI(3) => GLOBAL_LOGIC0,
      DI(2) => GLOBAL_LOGIC0,
      DI(1) => GLOBAL_LOGIC0,
      DI(0) => GLOBAL_LOGIC0,
      DO(3) => Ucore_Uusb_BUS206(7),
      DO(2) => Ucore_Uusb_BUS206(6),
      DO(1) => Ucore_Uusb_BUS206(5),
      DO(0) => Ucore_Uusb_BUS206(4)
    );
  a10_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a10_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a10_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(10),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a10_c_FFX_RST,
      O => a10_c
    );
  Ucore_Ufunc_sram_addrreg_4_10_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(10),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(10),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(10)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_10_Q : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => Ucore_Ufunc_i(10),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(10),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(10)
    );
  Ucore_Ufunc_sram_addrreg_4_am_10_Q : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded_rep1,
      ADR1 => Ucore_Ufunc_addr(10),
      ADR2 => Ucore_Ufunc_ram_readAddr(10),
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(10)
    );
  a10_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a10_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_11_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(11),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(11),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(11)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_11_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(11),
      ADR2 => Ucore_Ufunc_i(11),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(11)
    );
  Ucore_Ufunc_sram_addrreg_4_am_11_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(11),
      ADR2 => Ucore_Ufunc_addr(11),
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(11)
    );
  a11_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a11_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_12_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(12),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(12),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(12)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_12_Q : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(12),
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => Ucore_Ufunc_i(12),
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(12)
    );
  Ucore_Ufunc_sram_addrreg_4_am_12_Q : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(12),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => Ucore_Ufunc_addr(12),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(12)
    );
  a12_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a12_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_13_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(13),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(13),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(13)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_13_Q : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Ufunc_i(13),
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(13),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(13)
    );
  Ucore_Ufunc_sram_addrreg_4_am_13_Q : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_imageloaded_rep1,
      ADR2 => Ucore_Ufunc_ram_readAddr(13),
      ADR3 => Ucore_Ufunc_addr(13),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(13)
    );
  a13_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a13_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_14_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(14),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(14),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(14)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_14_Q : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => Ucore_Ufunc_ram_writeAddr(14),
      ADR3 => Ucore_Ufunc_i(14),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(14)
    );
  Ucore_Ufunc_sram_addrreg_4_am_14_Q : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(14),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => Ucore_Ufunc_addr(14),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(14)
    );
  a14_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a14_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_15_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(15),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(15),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(15)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_15_Q : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Ufunc_i(15),
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(15),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(15)
    );
  Ucore_Ufunc_sram_addrreg_4_am_15_Q : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(15),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(15),
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(15)
    );
  a15_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a15_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_16_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(16),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(16),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(16)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_16_Q : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(16),
      ADR1 => Ucore_Ufunc_i(16),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(16)
    );
  Ucore_Ufunc_sram_addrreg_4_am_16_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(16),
      ADR2 => Ucore_Ufunc_addr(16),
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(16)
    );
  a16_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a16_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GWEAND_139 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FWEAND_140 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU8_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU8_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU8_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N227_RAM32X1_GRAMS
    );
  Ucore_Ufunc_sram_addrreg_4_17_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(17),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(17),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(17)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_17_Q : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(17),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(17),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(17)
    );
  Ucore_Ufunc_sram_addrreg_4_am_17_Q : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(17),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr(17),
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(17)
    );
  a17_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a17_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_18_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(18),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(18),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(18)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_18_Q : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_i(18),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_ram_writeAddr(18),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(18)
    );
  Ucore_Ufunc_sram_addrreg_4_am_18_Q : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(18),
      ADR1 => Ucore_Ufunc_ram_readAddr(18),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(18)
    );
  a18_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a18_c_SRMUX_OUTPUTNOT
    );
  g0 : X_MUX2
    port map (
      IA => g0_x0_n,
      IB => g0_x1_n,
      SEL => Ucore_Ufunc_un1_temp2_2_8_0,
      O => Ucore_Ufunc_N_249_F5MUX
    );
  g0_x1 : X_LUT4
    generic map(
      INIT => X"070F"
    )
    port map (
      ADR0 => g0_L5_O,
      ADR1 => g0_L3_n,
      ADR2 => Ucore_Ufunc_imageloaded_fast,
      ADR3 => g0_L1_n,
      O => g0_x1_n
    );
  g0_x0 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded_fast,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => g0_x0_n
    );
  Ucore_Ufunc_N_249_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_249_F5MUX,
      O => Ucore_Ufunc_N_249
    );
  Ucore_Uusb_Uuc_Uamux_C332_C10_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C10_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C10_N7,
      SEL => Ucore_Uusb_Uuc_PCO_8_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_8_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C10_C0_C0 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_C380_N54,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_INCO(8),
      O => Ucore_Uusb_Uuc_Uamux_C332_C10_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C10_C1_C0 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_PCO(8),
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => Ucore_Uusb_Uuc_DPTRO(8),
      O => Ucore_Uusb_Uuc_Uamux_C332_C10_N8
    );
  Ucore_Uusb_Uuc_PCO_8_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_8_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_8_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_8_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(8)
    );
  Ucore_Uusb_Uuc_PCO_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_8_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GWEAND_141 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FWEAND_142 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU24_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU24_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU24_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N393_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uamux_C332_C11_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C11_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C11_N7,
      SEL => Ucore_Uusb_Uuc_PCO_9_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_9_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C11_C0_C0 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_C380_N60,
      ADR1 => Ucore_Uusb_Uuc_INCO(9),
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C11_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C11_C1_C0 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_DPTRO(9),
      ADR3 => Ucore_Uusb_Uuc_PCO(9),
      O => Ucore_Uusb_Uuc_Uamux_C332_C11_N8
    );
  Ucore_Uusb_Uuc_PCO_9_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_9_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_9_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_9_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(9)
    );
  Ucore_Uusb_Uuc_PCO_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C12_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C12_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C12_N7,
      SEL => Ucore_Uusb_Uuc_PCO_10_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_10_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C12_C0_C0 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(10),
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_C380_N66,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C12_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C12_C1_C0 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(10),
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => Ucore_Uusb_Uuc_PCO(10),
      O => Ucore_Uusb_Uuc_Uamux_C332_C12_N8
    );
  Ucore_Uusb_Uuc_PCO_10_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_10_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_10_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_10_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(10)
    );
  Ucore_Uusb_Uuc_PCO_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_10_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C13_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C13_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C13_N7,
      SEL => Ucore_Uusb_Uuc_PCO_11_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_11_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C13_C0_C0 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(11),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_C380_N72,
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C13_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C13_C1_C0 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(11),
      ADR2 => Ucore_Uusb_Uuc_PCO(11),
      ADR3 => Ucore_Uusb_Uuc_ASEL(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C13_N8
    );
  Ucore_Uusb_Uuc_PCO_11_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_11_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_11_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_11_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(11)
    );
  Ucore_Uusb_Uuc_PCO_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_11_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C14_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C14_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C14_N7,
      SEL => Ucore_Uusb_Uuc_PCO_12_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_12_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C14_C0_C0 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_C380_N78,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_INCO(12),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C14_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C14_C1_C0 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(12),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => Ucore_Uusb_Uuc_PCO(12),
      O => Ucore_Uusb_Uuc_Uamux_C332_C14_N8
    );
  Ucore_Uusb_Uuc_PCO_12_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_12_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_12_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_12_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(12)
    );
  Ucore_Uusb_Uuc_PCO_12_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_12_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C15_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C15_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C15_N7,
      SEL => Ucore_Uusb_Uuc_PCO_13_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_13_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C15_C0_C0 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_INCO(13),
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C380_N84,
      O => Ucore_Uusb_Uuc_Uamux_C332_C15_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C15_C1_C0 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_PCO(13),
      ADR3 => Ucore_Uusb_Uuc_DPTRO(13),
      O => Ucore_Uusb_Uuc_Uamux_C332_C15_N8
    );
  Ucore_Uusb_Uuc_PCO_13_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_13_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_13_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_13_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(13)
    );
  Ucore_Uusb_Uuc_PCO_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_13_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C16_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C16_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C16_N7,
      SEL => Ucore_Uusb_Uuc_PCO_14_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_14_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C16_C0_C0 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_C380_N90,
      ADR3 => Ucore_Uusb_Uuc_INCO(14),
      O => Ucore_Uusb_Uuc_Uamux_C332_C16_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C16_C1_C0 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_PCO(14),
      ADR2 => Ucore_Uusb_Uuc_DPTRO(14),
      ADR3 => Ucore_Uusb_Uuc_ASEL(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C16_N8
    );
  Ucore_Uusb_Uuc_PCO_14_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_14_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_14_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_14_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(14)
    );
  Ucore_Uusb_Uuc_PCO_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_14_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GWEAND_143 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FWEAND_144 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU32_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU32_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU32_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(4),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N476_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uuc_Uamux_C332_C17_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C17_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C17_N7,
      SEL => Ucore_Uusb_Uuc_PCO_15_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_15_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C17_C0_C0 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(15),
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C380_N96,
      O => Ucore_Uusb_Uuc_Uamux_C332_C17_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C17_C1_C0 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_DPTRO(15),
      ADR3 => Ucore_Uusb_Uuc_PCO(15),
      O => Ucore_Uusb_Uuc_Uamux_C332_C17_N8
    );
  Ucore_Uusb_Uuc_PCO_15_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_15_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_15_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_15_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(15)
    );
  Ucore_Uusb_Uuc_PCO_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_15_SRMUX_OUTPUTNOT
    );
  a1_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a1_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a1_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(1),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a1_c_FFX_RST,
      O => a1_c
    );
  Ucore_Ufunc_sram_addrreg_4_1_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(1),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(1),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(1)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_1_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(1),
      ADR2 => Ucore_Ufunc_i(1),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(1)
    );
  Ucore_Ufunc_sram_addrreg_4_am_1_Q : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(1),
      ADR1 => Ucore_Ufunc_addr(1),
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(1)
    );
  a1_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a1_c_SRMUX_OUTPUTNOT
    );
  a2_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a2_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a2_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(2),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a2_c_FFX_RST,
      O => a2_c
    );
  Ucore_Ufunc_sram_addrreg_4_2_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(2),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(2),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(2)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_2_Q : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(2),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_i(2),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(2)
    );
  Ucore_Ufunc_sram_addrreg_4_am_2_Q : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(2),
      ADR1 => Ucore_Ufunc_addr(2),
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(2)
    );
  a2_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a2_c_SRMUX_OUTPUTNOT
    );
  a3_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a3_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a3_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(3),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a3_c_FFX_RST,
      O => a3_c
    );
  Ucore_Ufunc_sram_addrreg_4_3_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(3),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(3),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(3)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_3_Q : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(3),
      ADR1 => Ucore_Ufunc_i(3),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(3)
    );
  Ucore_Ufunc_sram_addrreg_4_am_3_Q : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(3),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => Ucore_Ufunc_addr(3),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(3)
    );
  a3_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a3_c_SRMUX_OUTPUTNOT
    );
  a4_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a4_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a4_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(4),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a4_c_FFX_RST,
      O => a4_c
    );
  Ucore_Ufunc_sram_addrreg_4_4_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(4),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(4),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(4)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_4_Q : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(4),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(4),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(4)
    );
  Ucore_Ufunc_sram_addrreg_4_am_4_Q : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(4),
      ADR1 => Ucore_Ufunc_ram_readAddr(4),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(4)
    );
  a4_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a4_c_SRMUX_OUTPUTNOT
    );
  a5_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a5_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a5_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(5),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a5_c_FFX_RST,
      O => a5_c
    );
  Ucore_Ufunc_sram_addrreg_4_5_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(5),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(5),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(5)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_5_Q : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Ufunc_i(5),
      ADR1 => Ucore_Ufunc_ram_writeAddr(5),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(5)
    );
  Ucore_Ufunc_sram_addrreg_4_am_5_Q : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(5),
      ADR1 => Ucore_Ufunc_imageloaded_rep1,
      ADR2 => Ucore_Ufunc_ram_readAddr(5),
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(5)
    );
  a5_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a5_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_6_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(6),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(6),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(6)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_6_Q : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Ufunc_i(6),
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(6),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(6)
    );
  Ucore_Ufunc_sram_addrreg_4_am_6_Q : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(6),
      ADR1 => Ucore_Ufunc_ram_readAddr(6),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(6)
    );
  a6_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a6_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_7_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(7),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(7),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(7)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_7_Q : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(7),
      ADR3 => Ucore_Ufunc_ram_writeAddr(7),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(7)
    );
  Ucore_Ufunc_sram_addrreg_4_am_7_Q : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded_rep1,
      ADR1 => Ucore_Ufunc_ram_readAddr(7),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr(7),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(7)
    );
  a7_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a7_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_8_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(8),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(8),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(8)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_8_Q : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(8),
      ADR3 => Ucore_Ufunc_ram_writeAddr(8),
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(8)
    );
  Ucore_Ufunc_sram_addrreg_4_am_8_Q : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr(8),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(8),
      ADR3 => Ucore_Ufunc_imageloaded_rep1,
      O => Ucore_Ufunc_sram_addrreg_4_am_n(8)
    );
  a8_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a8_c_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_9_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_sram_addrreg_4_am_n(9),
      IB => Ucore_Ufunc_sram_addrreg_4_bm_n(9),
      SEL => Ucore_Ufunc_sram_doWrite,
      O => Ucore_Ufunc_sram_addrreg_4(9)
    );
  Ucore_Ufunc_sram_addrreg_4_bm_9_Q : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(9),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(9),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_addrreg_4_bm_n(9)
    );
  Ucore_Ufunc_sram_addrreg_4_am_9_Q : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(9),
      ADR1 => Ucore_Ufunc_imageloaded_rep1,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr(9),
      O => Ucore_Ufunc_sram_addrreg_4_am_n(9)
    );
  a9_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a9_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C2_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C2_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C2_N7,
      SEL => Ucore_Uusb_Uuc_PCO_0_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_0_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C2_C0_C0 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_C380_N6,
      ADR3 => Ucore_Uusb_Uuc_INCO(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C2_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C2_C1_C0 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_PCO(0),
      ADR3 => Ucore_Uusb_Uuc_DPTRO(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C2_N8
    );
  Ucore_Uusb_Uuc_PCO_0_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_0_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_0_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(0)
    );
  Ucore_Uusb_Uuc_PCO_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_PCO_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_1_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_1_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(1)
    );
  Ucore_Uusb_Uuc_Uamux_C332_C3_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C3_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C3_N7,
      SEL => Ucore_Uusb_Uuc_PCO_1_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_1_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C3_C0_C0 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_INCO(1),
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C380_N12,
      O => Ucore_Uusb_Uuc_Uamux_C332_C3_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C3_C1_C0 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(1),
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_PCO(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C3_N8
    );
  Ucore_Uusb_Uuc_PCO_1_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_1_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_1_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(1)
    );
  Ucore_Uusb_Uuc_PCO_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_PCO_2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_2_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_2_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_2_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(2)
    );
  Ucore_Uusb_Uuc_Uamux_C332_C4_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C4_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C4_N7,
      SEL => Ucore_Uusb_Uuc_PCO_2_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_2_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C4_C0_C0 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_C380_N18,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_INCO(2),
      ADR3 => Ucore_Uusb_Uuc_ASEL(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C4_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C4_C1_C0 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_PCO(2),
      ADR3 => Ucore_Uusb_Uuc_DPTRO(2),
      O => Ucore_Uusb_Uuc_Uamux_C332_C4_N8
    );
  Ucore_Uusb_Uuc_PCO_2_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_2_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_2_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(2)
    );
  Ucore_Uusb_Uuc_PCO_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_PCO_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_3_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_3_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(3)
    );
  Ucore_Uusb_Uuc_Uamux_C332_C5_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C5_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C5_N7,
      SEL => Ucore_Uusb_Uuc_PCO_3_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_3_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C5_C0_C0 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_C380_N24,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_INCO(3),
      O => Ucore_Uusb_Uuc_Uamux_C332_C5_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C5_C1_C0 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_DPTRO(3),
      ADR3 => Ucore_Uusb_Uuc_PCO(3),
      O => Ucore_Uusb_Uuc_Uamux_C332_C5_N8
    );
  Ucore_Uusb_Uuc_PCO_3_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_3_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_3_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(3)
    );
  Ucore_Uusb_Uuc_PCO_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_PCO_4_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_4_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_4_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_4_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(4)
    );
  Ucore_Uusb_Uuc_Uamux_C332_C6_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C6_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C6_N7,
      SEL => Ucore_Uusb_Uuc_PCO_4_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_4_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C6_C0_C0 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(4),
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C380_N30,
      O => Ucore_Uusb_Uuc_Uamux_C332_C6_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C6_C1_C0 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_DPTRO(4),
      ADR3 => Ucore_Uusb_Uuc_PCO(4),
      O => Ucore_Uusb_Uuc_Uamux_C332_C6_N8
    );
  Ucore_Uusb_Uuc_PCO_4_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_4_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_4_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(4)
    );
  Ucore_Uusb_Uuc_PCO_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_PCO_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_5_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_5_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(5)
    );
  Ucore_Uusb_Uuc_Uamux_C332_C7_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C7_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C7_N7,
      SEL => Ucore_Uusb_Uuc_PCO_5_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_5_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C7_C0_C0 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_INCO(5),
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C380_N36,
      O => Ucore_Uusb_Uuc_Uamux_C332_C7_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C7_C1_C0 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ASEL(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_DPTRO(5),
      ADR3 => Ucore_Uusb_Uuc_PCO(5),
      O => Ucore_Uusb_Uuc_Uamux_C332_C7_N8
    );
  Ucore_Uusb_Uuc_PCO_5_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_5_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_5_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(5)
    );
  Ucore_Uusb_Uuc_PCO_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C8_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C8_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C8_N7,
      SEL => Ucore_Uusb_Uuc_PCO_6_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_6_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C8_C0_C0 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(6),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_C380_N42,
      ADR2 => Ucore_Uusb_Uuc_ASEL(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C8_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C8_C1_C0 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(6),
      ADR2 => Ucore_Uusb_Uuc_PCO(6),
      ADR3 => Ucore_Uusb_Uuc_ASEL(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C8_N8
    );
  Ucore_Uusb_Uuc_PCO_6_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_6_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_6_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(6)
    );
  Ucore_Uusb_Uuc_PCO_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uamux_C332_C9_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uamux_C332_C9_N8,
      IB => Ucore_Uusb_Uuc_Uamux_C332_C9_N7,
      SEL => Ucore_Uusb_Uuc_PCO_7_BXMUXNOT,
      O => Ucore_Uusb_Uuc_PCO_7_F5MUX
    );
  Ucore_Uusb_Uuc_Uamux_C332_C9_C0_C0 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_INCO(7),
      ADR1 => Ucore_Uusb_Uuc_ASEL(0),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_C380_N48,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uamux_C332_C9_N7
    );
  Ucore_Uusb_Uuc_Uamux_C332_C9_C1_C0 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_PCO(7),
      ADR2 => Ucore_Uusb_Uuc_DPTRO(7),
      ADR3 => Ucore_Uusb_Uuc_ASEL(0),
      O => Ucore_Uusb_Uuc_Uamux_C332_C9_N8
    );
  Ucore_Uusb_Uuc_PCO_7_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_PCO_7_BXMUXNOT
    );
  Ucore_Uusb_Uuc_PCO_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PCO_7_F5MUX,
      O => Ucore_Uusb_Uuc_ABUS(7)
    );
  Ucore_Uusb_Uuc_PCO_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PCO_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ZERO_145 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ONE_146 : X_ONE
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ONE
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ZERO,
      SEL => Ucore_Ufunc_N_171_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_0_O
    );
  Ucore_Ufunc_N_171_i_147 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_171_i
    );
  Ucore_Ufunc_N_172_i_148 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_172_i
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_1_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_1_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_1_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_1_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_0_O,
      SEL => Ucore_Ufunc_N_172_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_0_O,
      I1 => Ucore_Ufunc_N_172_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_1_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2_n_LOGIC_ONE_149 : X_ONE
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_LOGIC_ONE
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_N_173_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_2_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_N_173_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORF
    );
  Ucore_Ufunc_N_173_i_150 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_173_i
    );
  Ucore_Ufunc_N_174_i_151 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_174_i
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_3_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_3_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_2_O,
      SEL => Ucore_Ufunc_N_174_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_2_O,
      I1 => Ucore_Ufunc_N_174_i,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYINIT_152 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_1_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_2_n_CYINIT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_LOGIC_ZERO_153 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_4_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORF
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_FROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_GROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_5_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_5_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_4_O,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_4_O,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYINIT_154 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_3_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_4_n_CYINIT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_LOGIC_ZERO_155 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_6_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORF
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(11),
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_FROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(12),
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_GROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_7_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_7_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_6_O,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_6_O,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYINIT_156 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_5_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_6_n_CYINIT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_LOGIC_ZERO_157 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYINIT,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_8_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORF
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_FROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_GROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_9_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_9_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_8_O,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_8_O,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYINIT_158 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_7_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_8_n_CYINIT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_LOGIC_ZERO_159 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYINIT,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_10_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYINIT,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORF
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_FROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_GROM
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYMUXG,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_11_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_11_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_11 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_cry_10_O,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYMUXG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_10_O,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYINIT_160 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_9_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_10_n_CYINIT
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12_n_LOGIC_ZERO_161 : X_ZERO
    port map (
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un19_nextaddr_offset_cry_12 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_CYINIT,
      SEL => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_cry_12_O
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_CYINIT,
      I1 => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORF
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(17),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_FROM
    );
  Ucore_Ufunc_addr_offset_18_rt_162 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(18),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_addr_offset_18_rt
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORF,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORG,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_13_n
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_13 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un19_nextaddr_offset_cry_12_O,
      I1 => Ucore_Ufunc_addr_offset_18_rt,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_XORG
    );
  Ucore_Ufunc_un19_nextaddr_offset_s_12_n_CYINIT_163 : X_BUF
    port map (
      I => Ucore_Ufunc_un19_nextaddr_offset_cry_11_O,
      O => Ucore_Ufunc_un19_nextaddr_offset_s_12_n_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_0_LOGIC_ONE_164 : X_ONE
    port map (
      O => Ucore_Uusb_Uuc_INCO_0_LOGIC_ONE
    );
  Ucore_Uusb_Uuc_INCO_0_LOGIC_ZERO_165 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_0_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C3_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_0_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_0_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_0_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C3_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C3_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_0_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_0_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N240
    );
  Ucore_Uusb_Uuc_INCO_0_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_0_FROM
    );
  Ucore_Uusb_Uuc_INCO_0_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_0_GROM
    );
  Ucore_Uusb_Uuc_INCO_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_0_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C4_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C4_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_0_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C3_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_0_GROM,
      O => Ucore_Uusb_Uuc_INCO_0_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C4_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C3_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_0_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N241
    );
  Ucore_Uusb_Uuc_INCO_0_CYINIT_166 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_0_LOGIC_ONE,
      O => Ucore_Uusb_Uuc_INCO_0_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_2_LOGIC_ZERO_167 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_2_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C5_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_2_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_2_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_2_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C5_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C5_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_2_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_2_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N242
    );
  Ucore_Uusb_Uuc_INCO_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ABUS(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_2_FROM
    );
  Ucore_Uusb_Uuc_INCO_2_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_2_GROM
    );
  Ucore_Uusb_Uuc_INCO_2_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_2_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C6_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C6_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_2_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C5_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_2_GROM,
      O => Ucore_Uusb_Uuc_INCO_2_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C6_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C5_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_2_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N243
    );
  Ucore_Uusb_Uuc_INCO_2_CYINIT_168 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C4_C1_O,
      O => Ucore_Uusb_Uuc_INCO_2_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_4_LOGIC_ZERO_169 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_4_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C7_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_4_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_4_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_4_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C7_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C7_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_4_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_4_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N244
    );
  Ucore_Uusb_Uuc_INCO_4_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_4_FROM
    );
  Ucore_Uusb_Uuc_INCO_4_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_4_GROM
    );
  Ucore_Uusb_Uuc_INCO_4_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_4_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C8_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C8_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_4_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C7_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_4_GROM,
      O => Ucore_Uusb_Uuc_INCO_4_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C8_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C7_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_4_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N245
    );
  Ucore_Uusb_Uuc_INCO_4_CYINIT_170 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C6_C1_O,
      O => Ucore_Uusb_Uuc_INCO_4_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_6_LOGIC_ZERO_171 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_6_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C9_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_6_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_6_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_6_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C9_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C9_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_6_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_6_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N246
    );
  Ucore_Uusb_Uuc_INCO_6_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_6_FROM
    );
  Ucore_Uusb_Uuc_INCO_6_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_6_GROM
    );
  Ucore_Uusb_Uuc_INCO_6_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_6_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C10_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C10_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_6_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C9_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_6_GROM,
      O => Ucore_Uusb_Uuc_INCO_6_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C10_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C9_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_6_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N247
    );
  Ucore_Uusb_Uuc_INCO_6_CYINIT_172 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C8_C1_O,
      O => Ucore_Uusb_Uuc_INCO_6_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_8_LOGIC_ZERO_173 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_8_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C11_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_8_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_8_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_8_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C11_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C11_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_8_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_8_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N248
    );
  Ucore_Uusb_Uuc_INCO_8_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_8_FROM
    );
  Ucore_Uusb_Uuc_INCO_8_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_8_GROM
    );
  Ucore_Uusb_Uuc_INCO_8_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_8_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C12_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C12_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_8_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C11_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_8_GROM,
      O => Ucore_Uusb_Uuc_INCO_8_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C12_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C11_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_8_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N249
    );
  Ucore_Uusb_Uuc_INCO_8_CYINIT_174 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C10_C1_O,
      O => Ucore_Uusb_Uuc_INCO_8_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_10_LOGIC_ZERO_175 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_10_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C13_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_10_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_10_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_10_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C13_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C13_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_10_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_10_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N250
    );
  Ucore_Uusb_Uuc_INCO_10_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_10_FROM
    );
  Ucore_Uusb_Uuc_INCO_10_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_10_GROM
    );
  Ucore_Uusb_Uuc_INCO_10_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_10_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C14_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C14_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_10_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C13_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_10_GROM,
      O => Ucore_Uusb_Uuc_INCO_10_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C14_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C13_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_10_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N251
    );
  Ucore_Uusb_Uuc_INCO_10_CYINIT_176 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C12_C1_O,
      O => Ucore_Uusb_Uuc_INCO_10_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_12_LOGIC_ZERO_177 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_12_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C15_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_12_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_12_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_12_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C15_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C15_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_12_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_12_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N252
    );
  Ucore_Uusb_Uuc_INCO_12_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_12_FROM
    );
  Ucore_Uusb_Uuc_INCO_12_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_12_GROM
    );
  Ucore_Uusb_Uuc_INCO_12_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_INCO_12_CYMUXG,
      O => Ucore_Uusb_Uuc_Uinc_C141_C16_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C16_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_12_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_Uinc_C141_C15_C1_O,
      SEL => Ucore_Uusb_Uuc_INCO_12_GROM,
      O => Ucore_Uusb_Uuc_INCO_12_CYMUXG
    );
  Ucore_Uusb_Uuc_Uinc_C141_C16_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C15_C1_O,
      I1 => Ucore_Uusb_Uuc_INCO_12_GROM,
      O => Ucore_Uusb_Uuc_Uinc_N253
    );
  Ucore_Uusb_Uuc_INCO_12_CYINIT_178 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C14_C1_O,
      O => Ucore_Uusb_Uuc_INCO_12_CYINIT
    );
  Ucore_Uusb_Uuc_INCO_14_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_14_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N254,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_14_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(14)
    );
  Ucore_Uusb_Uuc_INCO_14_LOGIC_ZERO_179 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_INCO_14_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uinc_C141_C17_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_INCO_14_LOGIC_ZERO,
      IB => Ucore_Uusb_Uuc_INCO_14_CYINIT,
      SEL => Ucore_Uusb_Uuc_INCO_14_FROM,
      O => Ucore_Uusb_Uuc_Uinc_C141_C17_C1_O
    );
  Ucore_Uusb_Uuc_Uinc_C141_C17_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_INCO_14_CYINIT,
      I1 => Ucore_Uusb_Uuc_INCO_14_FROM,
      O => Ucore_Uusb_Uuc_Uinc_N254
    );
  Ucore_Uusb_Uuc_INCO_14_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_INCO_14_FROM
    );
  Ucore_Uusb_Uuc_ABUS_15_rt_180 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ABUS(15),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_ABUS_15_rt
    );
  Ucore_Uusb_Uuc_Uinc_C141_C18_C0 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uinc_C141_C17_C1_O,
      I1 => Ucore_Uusb_Uuc_ABUS_15_rt,
      O => Ucore_Uusb_Uuc_Uinc_N255
    );
  Ucore_Uusb_Uuc_INCO_14_CYINIT_181 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uinc_C141_C16_C1_O,
      O => Ucore_Uusb_Uuc_INCO_14_CYINIT
    );
  Ucore_Ufunc_N_59_LOGIC_ONE_182 : X_ONE
    port map (
      O => Ucore_Ufunc_N_59_LOGIC_ONE
    );
  Ucore_Ufunc_N_59_LOGIC_ZERO_183 : X_ZERO
    port map (
      O => Ucore_Ufunc_N_59_LOGIC_ZERO
    );
  Ucore_Ufunc_next_state36_0_I_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_59_LOGIC_ZERO,
      IB => Ucore_Ufunc_N_59_LOGIC_ONE,
      SEL => Ucore_Ufunc_N_59_FROM,
      O => Ucore_Ufunc_next_state36_0_I_1_O
    );
  Ucore_Ufunc_un1_low_temp2_0_I_9 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(1),
      ADR1 => Ucore_Ufunc_temp2(0),
      ADR2 => Ucore_Ufunc_temp1(1),
      ADR3 => Ucore_Ufunc_temp1(0),
      O => Ucore_Ufunc_N_59_FROM
    );
  Ucore_Ufunc_un1_low_temp2_0_I_36 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(3),
      ADR1 => Ucore_Ufunc_temp1(3),
      ADR2 => Ucore_Ufunc_temp2(2),
      ADR3 => Ucore_Ufunc_temp1(2),
      O => Ucore_Ufunc_N_59_GROM
    );
  Ucore_Ufunc_N_59_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_59_CYMUXG,
      O => Ucore_Ufunc_next_state36_0_I_55_O
    );
  Ucore_Ufunc_N_59_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_59_FROM,
      O => Ucore_Ufunc_N_59
    );
  Ucore_Ufunc_N_59_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_59_GROM,
      O => Ucore_Ufunc_N_11_0
    );
  Ucore_Ufunc_next_state36_0_I_55 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_59_LOGIC_ZERO,
      IB => Ucore_Ufunc_next_state36_0_I_1_O,
      SEL => Ucore_Ufunc_N_59_GROM,
      O => Ucore_Ufunc_N_59_CYMUXG
    );
  Ucore_Ufunc_N_19_LOGIC_ZERO_184 : X_ZERO
    port map (
      O => Ucore_Ufunc_N_19_LOGIC_ZERO
    );
  Ucore_Ufunc_next_state36_0_I_46 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_19_LOGIC_ZERO,
      IB => Ucore_Ufunc_N_19_CYINIT,
      SEL => Ucore_Ufunc_N_19_FROM,
      O => Ucore_Ufunc_next_state36_0_I_46_O
    );
  Ucore_Ufunc_un1_low_temp2_0_I_27 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(5),
      ADR1 => Ucore_Ufunc_temp2(4),
      ADR2 => Ucore_Ufunc_temp1(5),
      ADR3 => Ucore_Ufunc_temp1(4),
      O => Ucore_Ufunc_N_19_FROM
    );
  Ucore_Ufunc_un1_low_temp2_0_I_18 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(6),
      ADR1 => Ucore_Ufunc_temp1(7),
      ADR2 => Ucore_Ufunc_temp1(6),
      ADR3 => Ucore_Ufunc_temp2(7),
      O => Ucore_Ufunc_N_19_GROM
    );
  Ucore_Ufunc_N_19_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_19_CYMUXG,
      O => Ucore_Ufunc_next_state36_0_I_28_O
    );
  Ucore_Ufunc_N_19_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_19_FROM,
      O => Ucore_Ufunc_N_19
    );
  Ucore_Ufunc_N_19_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_19_GROM,
      O => Ucore_Ufunc_N_35
    );
  Ucore_Ufunc_next_state36_0_I_28 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_19_LOGIC_ZERO,
      IB => Ucore_Ufunc_next_state36_0_I_46_O,
      SEL => Ucore_Ufunc_N_19_GROM,
      O => Ucore_Ufunc_N_19_CYMUXG
    );
  Ucore_Ufunc_N_19_CYINIT_185 : X_BUF
    port map (
      I => Ucore_Ufunc_next_state36_0_I_55_O,
      O => Ucore_Ufunc_N_19_CYINIT
    );
  Ucore_Ufunc_N_27_0_LOGIC_ZERO_186 : X_ZERO
    port map (
      O => Ucore_Ufunc_N_27_0_LOGIC_ZERO
    );
  Ucore_Ufunc_next_state36_0_I_37 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_27_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_N_27_0_CYINIT,
      SEL => Ucore_Ufunc_N_27_0_FROM,
      O => Ucore_Ufunc_next_state36_0_I_37_O
    );
  Ucore_Ufunc_next_state36_0_I_45 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(8),
      ADR1 => Ucore_Ufunc_temp1(9),
      ADR2 => Ucore_Ufunc_temp2(9),
      ADR3 => Ucore_Ufunc_temp1(8),
      O => Ucore_Ufunc_N_27_0_FROM
    );
  Ucore_Ufunc_next_state36_0_I_27 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(10),
      ADR1 => Ucore_Ufunc_temp1(10),
      ADR2 => Ucore_Ufunc_temp1(11),
      ADR3 => Ucore_Ufunc_temp2(11),
      O => Ucore_Ufunc_N_27_0_GROM
    );
  Ucore_Ufunc_N_27_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_27_0_CYMUXG,
      O => Ucore_Ufunc_next_state36_0_I_19_O
    );
  Ucore_Ufunc_N_27_0_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_27_0_FROM,
      O => Ucore_Ufunc_N_27_0
    );
  Ucore_Ufunc_N_27_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_27_0_GROM,
      O => Ucore_Ufunc_N_43
    );
  Ucore_Ufunc_next_state36_0_I_19 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_27_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_next_state36_0_I_37_O,
      SEL => Ucore_Ufunc_N_27_0_GROM,
      O => Ucore_Ufunc_N_27_0_CYMUXG
    );
  Ucore_Ufunc_N_27_0_CYINIT_187 : X_BUF
    port map (
      I => Ucore_Ufunc_next_state36_0_I_28_O,
      O => Ucore_Ufunc_N_27_0_CYINIT
    );
  Ucore_Ufunc_N_51_LOGIC_ZERO_188 : X_ZERO
    port map (
      O => Ucore_Ufunc_N_51_LOGIC_ZERO
    );
  Ucore_Ufunc_next_state36_0_I_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_51_LOGIC_ZERO,
      IB => Ucore_Ufunc_N_51_CYINIT,
      SEL => Ucore_Ufunc_N_51_FROM,
      O => Ucore_Ufunc_next_state36_0_I_10_O
    );
  Ucore_Ufunc_next_state36_0_I_18 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(12),
      ADR1 => Ucore_Ufunc_temp2(13),
      ADR2 => Ucore_Ufunc_temp1(12),
      ADR3 => Ucore_Ufunc_temp1(13),
      O => Ucore_Ufunc_N_51_FROM
    );
  Ucore_Ufunc_next_state36_0_I_72 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(15),
      ADR1 => Ucore_Ufunc_temp2(14),
      ADR2 => Ucore_Ufunc_temp1(15),
      ADR3 => Ucore_Ufunc_temp1(14),
      O => Ucore_Ufunc_N_51_GROM
    );
  Ucore_Ufunc_N_51_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_51_CYMUXG,
      O => Ucore_Ufunc_next_state36
    );
  Ucore_Ufunc_N_51_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_51_FROM,
      O => Ucore_Ufunc_N_51
    );
  Ucore_Ufunc_N_51_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_51_GROM,
      O => Ucore_Ufunc_N_3_0
    );
  Ucore_Ufunc_next_state36_0_I_64 : X_MUX2
    port map (
      IA => Ucore_Ufunc_N_51_LOGIC_ZERO,
      IB => Ucore_Ufunc_next_state36_0_I_10_O,
      SEL => Ucore_Ufunc_N_51_GROM,
      O => Ucore_Ufunc_N_51_CYMUXG
    );
  Ucore_Ufunc_N_51_CYINIT_189 : X_BUF
    port map (
      I => Ucore_Ufunc_next_state36_0_I_19_O,
      O => Ucore_Ufunc_N_51_CYINIT
    );
  Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GWEAND_190 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FWEAND_191 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU15_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU15_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU15_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N309_RAM32X1_GRAMS
    );
  Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ONE_192 : X_ONE
    port map (
      O => Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ONE
    );
  Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ZERO_193 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextc_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_s_0_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextc_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nextc_cry_0_O
    );
  Ucore_Ufunc_un4_nextc_s_0 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_s_0_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextc_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nextc_s_0_n_XORF
    );
  Ucore_Ufunc_un4_nextc_s_0_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_c(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_0_n_FROM
    );
  Ucore_Ufunc_un4_nextc_s_0_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_c(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_0_n_GROM
    );
  Ucore_Ufunc_un4_nextc_s_0_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_0_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextc_cry_1_O
    );
  Ucore_Ufunc_un4_nextc_s_0_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_0_n_XORF,
      O => Ucore_Ufunc_un4_nextc_s_0_n
    );
  Ucore_Ufunc_un4_nextc_s_0_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_0_n_XORG,
      O => Ucore_Ufunc_un4_nextc_s_1_n
    );
  Ucore_Ufunc_un4_nextc_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_cry_0_O,
      SEL => Ucore_Ufunc_un4_nextc_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_0_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextc_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_cry_0_O,
      I1 => Ucore_Ufunc_un4_nextc_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_0_n_XORG
    );
  Ucore_Ufunc_un4_nextc_s_0_n_CYINIT_194 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_0_n_LOGIC_ONE,
      O => Ucore_Ufunc_un4_nextc_s_0_n_CYINIT
    );
  Ucore_Ufunc_un4_nextc_s_2_n_LOGIC_ZERO_195 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextc_s_2_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextc_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextc_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nextc_cry_2_O
    );
  Ucore_Ufunc_un4_nextc_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextc_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nextc_s_2_n_XORF
    );
  Ucore_Ufunc_un4_nextc_s_2_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_c(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_2_n_FROM
    );
  Ucore_Ufunc_un4_nextc_s_2_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_c(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_2_n_GROM
    );
  Ucore_Ufunc_un4_nextc_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextc_cry_3_O
    );
  Ucore_Ufunc_un4_nextc_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_2_n_XORF,
      O => Ucore_Ufunc_un4_nextc_s_2_n
    );
  Ucore_Ufunc_un4_nextc_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_2_n_XORG,
      O => Ucore_Ufunc_un4_nextc_s_3_n
    );
  Ucore_Ufunc_un4_nextc_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_cry_2_O,
      SEL => Ucore_Ufunc_un4_nextc_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextc_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_cry_2_O,
      I1 => Ucore_Ufunc_un4_nextc_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_2_n_XORG
    );
  Ucore_Ufunc_un4_nextc_s_2_n_CYINIT_196 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_cry_1_O,
      O => Ucore_Ufunc_un4_nextc_s_2_n_CYINIT
    );
  Ucore_Ufunc_un4_nextc_s_4_n_LOGIC_ZERO_197 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextc_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextc_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextc_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nextc_cry_4_O
    );
  Ucore_Ufunc_un4_nextc_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextc_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nextc_s_4_n_XORF
    );
  Ucore_Ufunc_un4_nextc_s_4_n_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_c(4),
      O => Ucore_Ufunc_un4_nextc_s_4_n_FROM
    );
  Ucore_Ufunc_un4_nextc_s_4_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_c(5),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_4_n_GROM
    );
  Ucore_Ufunc_un4_nextc_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextc_cry_5_O
    );
  Ucore_Ufunc_un4_nextc_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_4_n_XORF,
      O => Ucore_Ufunc_un4_nextc_s_4_n
    );
  Ucore_Ufunc_un4_nextc_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_4_n_XORG,
      O => Ucore_Ufunc_un4_nextc_s_5_n
    );
  Ucore_Ufunc_un4_nextc_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_cry_4_O,
      SEL => Ucore_Ufunc_un4_nextc_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextc_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_cry_4_O,
      I1 => Ucore_Ufunc_un4_nextc_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_4_n_XORG
    );
  Ucore_Ufunc_un4_nextc_s_4_n_CYINIT_198 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_cry_3_O,
      O => Ucore_Ufunc_un4_nextc_s_4_n_CYINIT
    );
  Ucore_Ufunc_un4_nextc_s_6_n_LOGIC_ZERO_199 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextc_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextc_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextc_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nextc_cry_6_O
    );
  Ucore_Ufunc_un4_nextc_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextc_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nextc_s_6_n_XORF
    );
  Ucore_Ufunc_un4_nextc_s_6_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_c(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_6_n_FROM
    );
  Ucore_Ufunc_un4_nextc_s_6_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_c(7),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_6_n_GROM
    );
  Ucore_Ufunc_un4_nextc_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextc_cry_7_O
    );
  Ucore_Ufunc_un4_nextc_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_6_n_XORF,
      O => Ucore_Ufunc_un4_nextc_s_6_n
    );
  Ucore_Ufunc_un4_nextc_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_6_n_XORG,
      O => Ucore_Ufunc_un4_nextc_s_7_n
    );
  Ucore_Ufunc_un4_nextc_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_cry_6_O,
      SEL => Ucore_Ufunc_un4_nextc_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextc_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_cry_6_O,
      I1 => Ucore_Ufunc_un4_nextc_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nextc_s_6_n_XORG
    );
  Ucore_Ufunc_un4_nextc_s_6_n_CYINIT_200 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_cry_5_O,
      O => Ucore_Ufunc_un4_nextc_s_6_n_CYINIT
    );
  Ucore_Ufunc_un4_nextc_s_8_n_LOGIC_ZERO_201 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextc_s_8_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextc_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextc_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextc_s_8_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextc_s_8_n_FROM,
      O => Ucore_Ufunc_un4_nextc_cry_8_O
    );
  Ucore_Ufunc_un4_nextc_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextc_s_8_n_FROM,
      O => Ucore_Ufunc_un4_nextc_s_8_n_XORF
    );
  Ucore_Ufunc_un4_nextc_s_8_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_c(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextc_s_8_n_FROM
    );
  Ucore_Ufunc_c_9_rt_202 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_c(9),
      ADR3 => VCC,
      O => Ucore_Ufunc_c_9_rt
    );
  Ucore_Ufunc_un4_nextc_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_8_n_XORF,
      O => Ucore_Ufunc_un4_nextc_s_8_n
    );
  Ucore_Ufunc_un4_nextc_s_8_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_s_8_n_XORG,
      O => Ucore_Ufunc_un4_nextc_s_9_n
    );
  Ucore_Ufunc_un4_nextc_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextc_cry_8_O,
      I1 => Ucore_Ufunc_c_9_rt,
      O => Ucore_Ufunc_un4_nextc_s_8_n_XORG
    );
  Ucore_Ufunc_un4_nextc_s_8_n_CYINIT_203 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextc_cry_7_O,
      O => Ucore_Ufunc_un4_nextc_s_8_n_CYINIT
    );
  Ucore_Ufunc_r_0_LOGIC_ZERO_204 : X_ZERO
    port map (
      O => Ucore_Ufunc_r_0_LOGIC_ZERO
    );
  Ucore_Ufunc_r_cry_0_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_0_CYINIT,
      SEL => Ucore_Ufunc_r_qxu(0),
      O => Ucore_Ufunc_r_cry_0_O
    );
  Ucore_Ufunc_r_s_0_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_0_CYINIT,
      I1 => Ucore_Ufunc_r_qxu(0),
      O => Ucore_Ufunc_r_s(0)
    );
  Ucore_Ufunc_r_qxu_0_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_r(0),
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(0)
    );
  Ucore_Ufunc_r_qxu_1_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_r(1),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(1)
    );
  Ucore_Ufunc_r_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_r_0_CYMUXG,
      O => Ucore_Ufunc_r_cry_1_O
    );
  Ucore_Ufunc_r_cry_1_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_cry_0_O,
      SEL => Ucore_Ufunc_r_qxu(1),
      O => Ucore_Ufunc_r_0_CYMUXG
    );
  Ucore_Ufunc_r_s_1_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_cry_0_O,
      I1 => Ucore_Ufunc_r_qxu(1),
      O => Ucore_Ufunc_r_s(1)
    );
  Ucore_Ufunc_r_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_r_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_r_0_CYINIT_205 : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_r_0_CYINIT
    );
  Ucore_Ufunc_r_2_LOGIC_ZERO_206 : X_ZERO
    port map (
      O => Ucore_Ufunc_r_2_LOGIC_ZERO
    );
  Ucore_Ufunc_r_cry_2_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_2_CYINIT,
      SEL => Ucore_Ufunc_r_qxu(2),
      O => Ucore_Ufunc_r_cry_2_O
    );
  Ucore_Ufunc_r_s_2_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_2_CYINIT,
      I1 => Ucore_Ufunc_r_qxu(2),
      O => Ucore_Ufunc_r_s(2)
    );
  Ucore_Ufunc_r_qxu_2_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_r(2),
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(2)
    );
  Ucore_Ufunc_r_qxu_3_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_r(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(3)
    );
  Ucore_Ufunc_r_2_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_r_2_CYMUXG,
      O => Ucore_Ufunc_r_cry_3_O
    );
  Ucore_Ufunc_r_cry_3_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_cry_2_O,
      SEL => Ucore_Ufunc_r_qxu(3),
      O => Ucore_Ufunc_r_2_CYMUXG
    );
  Ucore_Ufunc_r_s_3_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_cry_2_O,
      I1 => Ucore_Ufunc_r_qxu(3),
      O => Ucore_Ufunc_r_s(3)
    );
  Ucore_Ufunc_r_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_r_2_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_r_2_CYINIT_207 : X_BUF
    port map (
      I => Ucore_Ufunc_r_cry_1_O,
      O => Ucore_Ufunc_r_2_CYINIT
    );
  Ucore_Ufunc_r_4_LOGIC_ZERO_208 : X_ZERO
    port map (
      O => Ucore_Ufunc_r_4_LOGIC_ZERO
    );
  Ucore_Ufunc_r_cry_4_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_4_CYINIT,
      SEL => Ucore_Ufunc_r_qxu(4),
      O => Ucore_Ufunc_r_cry_4_O
    );
  Ucore_Ufunc_r_s_4_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_4_CYINIT,
      I1 => Ucore_Ufunc_r_qxu(4),
      O => Ucore_Ufunc_r_s(4)
    );
  Ucore_Ufunc_r_qxu_4_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_r(4),
      O => Ucore_Ufunc_r_qxu(4)
    );
  Ucore_Ufunc_r_qxu_5_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_r(5),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(5)
    );
  Ucore_Ufunc_r_4_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_r_4_CYMUXG,
      O => Ucore_Ufunc_r_cry_5_O
    );
  Ucore_Ufunc_r_cry_5_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_cry_4_O,
      SEL => Ucore_Ufunc_r_qxu(5),
      O => Ucore_Ufunc_r_4_CYMUXG
    );
  Ucore_Ufunc_r_s_5_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_cry_4_O,
      I1 => Ucore_Ufunc_r_qxu(5),
      O => Ucore_Ufunc_r_s(5)
    );
  Ucore_Ufunc_r_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_r_4_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_r_4_CYINIT_209 : X_BUF
    port map (
      I => Ucore_Ufunc_r_cry_3_O,
      O => Ucore_Ufunc_r_4_CYINIT
    );
  Ucore_Ufunc_r_6_LOGIC_ZERO_210 : X_ZERO
    port map (
      O => Ucore_Ufunc_r_6_LOGIC_ZERO
    );
  Ucore_Ufunc_r_cry_6_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_6_CYINIT,
      SEL => Ucore_Ufunc_r_qxu(6),
      O => Ucore_Ufunc_r_cry_6_O
    );
  Ucore_Ufunc_r_s_6_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_6_CYINIT,
      I1 => Ucore_Ufunc_r_qxu(6),
      O => Ucore_Ufunc_r_s(6)
    );
  Ucore_Ufunc_r_qxu_6_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_r(6),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_r_qxu(6)
    );
  Ucore_Ufunc_r_qxu_7_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => Ucore_Ufunc_r(7),
      O => Ucore_Ufunc_r_qxu(7)
    );
  Ucore_Ufunc_r_6_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_r_6_CYMUXG,
      O => Ucore_Ufunc_r_cry_7_O
    );
  Ucore_Ufunc_r_cry_7_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_cry_6_O,
      SEL => Ucore_Ufunc_r_qxu(7),
      O => Ucore_Ufunc_r_6_CYMUXG
    );
  Ucore_Ufunc_r_s_7_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_cry_6_O,
      I1 => Ucore_Ufunc_r_qxu(7),
      O => Ucore_Ufunc_r_s(7)
    );
  Ucore_Ufunc_r_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_r_6_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_r_6_CYINIT_211 : X_BUF
    port map (
      I => Ucore_Ufunc_r_cry_5_O,
      O => Ucore_Ufunc_r_6_CYINIT
    );
  Ucore_Ufunc_r_8_LOGIC_ZERO_212 : X_ZERO
    port map (
      O => Ucore_Ufunc_r_8_LOGIC_ZERO
    );
  Ucore_Ufunc_r_cry_8_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_r_8_LOGIC_ZERO,
      IB => Ucore_Ufunc_r_8_CYINIT,
      SEL => Ucore_Ufunc_r_qxu(8),
      O => Ucore_Ufunc_r_cry_8_O
    );
  Ucore_Ufunc_r_s_8_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_8_CYINIT,
      I1 => Ucore_Ufunc_r_qxu(8),
      O => Ucore_Ufunc_r_s(8)
    );
  Ucore_Ufunc_r_qxu_8_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_r(8),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_r_qxu(8)
    );
  Ucore_Ufunc_r_qxu_0_9_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_r(9),
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_r_qxu(9)
    );
  Ucore_Ufunc_r_s_9_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_r_cry_8_O,
      I1 => Ucore_Ufunc_r_qxu(9),
      O => Ucore_Ufunc_r_s(9)
    );
  Ucore_Ufunc_r_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_r_8_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_r_8_CYINIT_213 : X_BUF
    port map (
      I => Ucore_Ufunc_r_cry_7_O,
      O => Ucore_Ufunc_r_8_CYINIT
    );
  Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ONE_214 : X_ONE
    port map (
      O => Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ONE
    );
  Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ZERO_215 : X_ZERO
    port map (
      O => Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_high_temp2_0_I_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ONE,
      SEL => Ucore_Ufunc_N_27_0_rt,
      O => Ucore_Ufunc_un1_high_temp2_0_I_1_O
    );
  Ucore_Ufunc_N_27_0_rt_216 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_27_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_27_0_rt
    );
  Ucore_Ufunc_N_43_rt_217 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_43,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_43_rt
    );
  Ucore_Ufunc_un1_high_temp2_0_I_28_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_high_temp2_0_I_28_O_CYMUXG,
      O => Ucore_Ufunc_un1_high_temp2_0_I_28_O
    );
  Ucore_Ufunc_un1_high_temp2_0_I_28 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_high_temp2_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_0_I_1_O,
      SEL => Ucore_Ufunc_N_43_rt,
      O => Ucore_Ufunc_un1_high_temp2_0_I_28_O_CYMUXG
    );
  I_10_n_0_LOGIC_ZERO_218 : X_ZERO
    port map (
      O => I_10_n_0_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_high_temp2_0_I_19 : X_MUX2
    port map (
      IA => I_10_n_0_LOGIC_ZERO,
      IB => I_10_n_0_CYINIT,
      SEL => Ucore_Ufunc_N_51_rt,
      O => Ucore_Ufunc_un1_high_temp2_0_I_19_O
    );
  Ucore_Ufunc_N_51_rt_219 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_51,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_51_rt
    );
  Ucore_Ufunc_N_3_0_rt_220 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_3_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_3_0_rt
    );
  I_10_n_0_COUTUSED : X_BUF
    port map (
      I => I_10_n_0_CYMUXG,
      O => I_10_n_0
    );
  Ucore_Ufunc_un1_high_temp2_0_I_10 : X_MUX2
    port map (
      IA => I_10_n_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_0_I_19_O,
      SEL => Ucore_Ufunc_N_3_0_rt,
      O => I_10_n_0_CYMUXG
    );
  I_10_n_0_CYINIT_221 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_high_temp2_0_I_28_O,
      O => I_10_n_0_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_N372_LOGIC_ZERO_222 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_Ubuf_N372_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C2_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(0),
      IB => Ucore_Uusb_Uuc_Ubuf_N372_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C2_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C2_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C2_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N372_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C2_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N372_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C2_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C2_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C3_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(1),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C3_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N372_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N372_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C3_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N372_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N372_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N372
    );
  Ucore_Uusb_Uuc_Ubuf_N372_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N372_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N373
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C3_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(1),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C2_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C3_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N372_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C3_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C2_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C3_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N372_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N372_CYINIT_223 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N372_LOGIC_ZERO,
      O => Ucore_Uusb_Uuc_Ubuf_N372_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C4_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(2),
      IB => Ucore_Uusb_Uuc_Ubuf_N374_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C4_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C4_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C4_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N374_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C4_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N374_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C4_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(2),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C4_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C5_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(3),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C5_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N374_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N374_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C5_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N374_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N374_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N374
    );
  Ucore_Uusb_Uuc_Ubuf_N374_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N374_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N375
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C5_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(3),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C4_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C5_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N374_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C5_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C4_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C5_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N374_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N374_CYINIT_224 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C3_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N374_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C6_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(4),
      IB => Ucore_Uusb_Uuc_Ubuf_N376_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C6_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C6_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C6_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N376_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C6_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N376_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C6_C0 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(4),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_rel(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C6_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C7_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(5),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C7_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N376_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N376_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C7_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N376_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N376_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N376
    );
  Ucore_Uusb_Uuc_Ubuf_N376_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N376_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N377
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C7_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(5),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C6_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C7_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N376_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C7_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C6_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C7_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N376_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N376_CYINIT_225 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C5_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N376_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C8_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(6),
      IB => Ucore_Uusb_Uuc_Ubuf_N378_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C8_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C8_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C8_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N378_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C8_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N378_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C8_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(6),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C8_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C9_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(7),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C9_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N378_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N378_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C9_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N378_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N378_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N378
    );
  Ucore_Uusb_Uuc_Ubuf_N378_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N378_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N379
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C9_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(7),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C8_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C9_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N378_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C9_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C8_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C9_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N378_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N378_CYINIT_226 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C7_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N378_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C10_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(8),
      IB => Ucore_Uusb_Uuc_Ubuf_N380_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C10_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C10_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C10_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N380_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C10_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N380_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C10_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C10_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C11_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C11_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N380_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N380_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C11_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N380_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N380_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N380
    );
  Ucore_Uusb_Uuc_Ubuf_N380_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N380_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N381
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C11_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(9),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C10_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C11_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N380_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C11_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C10_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C11_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N380_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N380_CYINIT_227 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C9_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N380_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C12_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(10),
      IB => Ucore_Uusb_Uuc_Ubuf_N382_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C12_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C12_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C12_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N382_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C12_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N382_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C12_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(10),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C12_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C13_C0 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      O => Ucore_Uusb_Uuc_Ubuf_C379_C13_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N382_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N382_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C13_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N382_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N382_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N382
    );
  Ucore_Uusb_Uuc_Ubuf_N382_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N382_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N383
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C13_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(11),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C12_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C13_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N382_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C13_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C12_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C13_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N382_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N382_CYINIT_228 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C11_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N382_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C14_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(12),
      IB => Ucore_Uusb_Uuc_Ubuf_N384_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C14_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C14_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C14_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N384_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C14_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N384_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C14_C0 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(12),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C14_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C15_C0 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(13),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C15_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N384_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N384_CYMUXG,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C15_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_N384_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N384_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N384
    );
  Ucore_Uusb_Uuc_Ubuf_N384_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N384_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N385
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C15_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(13),
      IB => Ucore_Uusb_Uuc_Ubuf_C379_C14_C2_O,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C15_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N384_CYMUXG
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C15_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C14_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C15_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N384_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N384_CYINIT_229 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C13_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N384_CYINIT
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C16_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUFO8(14),
      IB => Ucore_Uusb_Uuc_Ubuf_N386_CYINIT,
      SEL => Ucore_Uusb_Uuc_Ubuf_C379_C16_N5,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C16_C2_O
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C16_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_N386_CYINIT,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C16_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N386_XORF
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C16_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(14),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C16_N5
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C17_C0 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(15),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_rel(7),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C379_C17_N5
    );
  Ucore_Uusb_Uuc_Ubuf_N386_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N386_XORF,
      O => Ucore_Uusb_Uuc_Ubuf_N386
    );
  Ucore_Uusb_Uuc_Ubuf_N386_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_N386_XORG,
      O => Ucore_Uusb_Uuc_Ubuf_N387
    );
  Ucore_Uusb_Uuc_Ubuf_C379_C17_C1 : X_XOR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_C379_C16_C2_O,
      I1 => Ucore_Uusb_Uuc_Ubuf_C379_C17_N5,
      O => Ucore_Uusb_Uuc_Ubuf_N386_XORG
    );
  Ucore_Uusb_Uuc_Ubuf_N386_CYINIT_230 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C379_C15_C2_O,
      O => Ucore_Uusb_Uuc_Ubuf_N386_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_LOGIC_ONE_231 : X_ONE
    port map (
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_LOGIC_ONE
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(6),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYINIT,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_1,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_1_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_1,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_1_232 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(6),
      ADR1 => Ucore_Ufunc_s_prev_cur_oldRow(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_1
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_2_233 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(7),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_prev_cur_oldRow(7),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_2
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYMUXG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_2_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_2_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(7),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_cry_1_O,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_2,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYMUXG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_cry_1_O,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_2,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_XORG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYINIT_234 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_LOGIC_ONE,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(8),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYINIT,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_3,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_3_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_3,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_3_235 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(8),
      ADR1 => Ucore_Ufunc_s_prev_cur_oldRow(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_3
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_4_236 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(9),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_prev_cur_oldRow(9),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_4
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYMUXG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_4_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_4_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(9),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_cry_3_O,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_4,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYMUXG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_cry_3_O,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_4,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_XORG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYINIT_237 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_cry_2_O,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(10),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYINIT,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_5,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_5_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_5,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_5_238 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(10),
      ADR1 => Ucore_Ufunc_s_prev_cur_oldRow(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_5
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_6_239 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(11),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_prev_cur_oldRow(11),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_6
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYMUXG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_6_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_6_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(11),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_cry_5_O,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_6,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYMUXG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_cry_5_O,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_6,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_XORG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYINIT_240 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_cry_4_O,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(12),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYINIT,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_7,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_7_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_7,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_7_241 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(12),
      ADR1 => Ucore_Ufunc_s_prev_cur_oldRow(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_7
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_8_242 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(13),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_prev_cur_oldRow(13),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_8
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYMUXG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_8_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(13),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_cry_7_O,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_8,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYMUXG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_cry_7_O,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_8,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_XORG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYINIT_243 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_cry_6_O,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(14),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYINIT,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_9,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_9_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_9,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_9_244 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(14),
      ADR1 => Ucore_Ufunc_s_prev_cur_oldRow(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_9
    );
  Ucore_Ufunc_un1_s_cur_oldRow_axb_10_245 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldRow(15),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_prev_cur_oldRow(15),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_axb_10
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYMUXG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_cry_10_O
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORG,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_10_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_s_cur_oldRow(15),
      IB => Ucore_Ufunc_un1_s_cur_oldRow_cry_9_O,
      SEL => Ucore_Ufunc_un1_s_cur_oldRow_axb_10,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYMUXG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_cry_9_O,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_axb_10,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_XORG
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYINIT_246 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_cry_8_O,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n_CYINIT
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_CYINIT,
      I1 => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_FROM,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_XORF
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_FROM
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_XORF,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n
    );
  Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_CYINIT_247 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_s_cur_oldRow_cry_10_O,
      O => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n_CYINIT
    );
  Ucore_Ufunc_addr_3_LOGIC_ZERO_248 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_3_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(3),
      IB => Ucore_Ufunc_addr_3_LOGIC_ZERO,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_3,
      O => Ucore_Ufunc_un1_nextaddr_cry_3_O
    );
  Ucore_Ufunc_un1_nextaddr_axb_3_249 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(8),
      O => Ucore_Ufunc_un1_nextaddr_axb_3
    );
  Ucore_Ufunc_un1_nextaddr_axb_4_250 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(4),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_cur_oldCol(9),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_nextaddr_axb_4
    );
  Ucore_Ufunc_addr_3_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_3_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_4_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(4),
      IB => Ucore_Ufunc_un1_nextaddr_cry_3_O,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_4,
      O => Ucore_Ufunc_addr_3_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_3_O,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_4,
      O => Ucore_Ufunc_un1_nextaddr_s_4_n
    );
  Ucore_Ufunc_addr_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GWEAND_251 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FWEAND_252 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU7_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU7_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU7_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N226_RAM32X1_GRAMS
    );
  Ucore_Ufunc_un1_nextaddr_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(5),
      IB => Ucore_Ufunc_addr_5_CYINIT,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_5,
      O => Ucore_Ufunc_un1_nextaddr_cry_5_O
    );
  Ucore_Ufunc_un1_nextaddr_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_5_CYINIT,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_5,
      O => Ucore_Ufunc_un1_nextaddr_s_5_n
    );
  Ucore_Ufunc_un1_nextaddr_axb_5_253 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(10),
      O => Ucore_Ufunc_un1_nextaddr_axb_5
    );
  Ucore_Ufunc_un1_nextaddr_axb_6_254 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(6),
      ADR1 => Ucore_Ufunc_s_cur_oldCol(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_nextaddr_axb_6
    );
  Ucore_Ufunc_addr_5_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_5_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_6_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(6),
      IB => Ucore_Ufunc_un1_nextaddr_cry_5_O,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_6,
      O => Ucore_Ufunc_addr_5_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_5_O,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_6,
      O => Ucore_Ufunc_un1_nextaddr_s_6_n
    );
  Ucore_Ufunc_addr_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_5_CYINIT_255 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_4_O,
      O => Ucore_Ufunc_addr_5_CYINIT
    );
  Ucore_Ufunc_un1_nextaddr_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(7),
      IB => Ucore_Ufunc_addr_7_CYINIT,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_7,
      O => Ucore_Ufunc_un1_nextaddr_cry_7_O
    );
  Ucore_Ufunc_un1_nextaddr_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_7_CYINIT,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_7,
      O => Ucore_Ufunc_un1_nextaddr_s_7_n
    );
  Ucore_Ufunc_un1_nextaddr_axb_7_256 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(7),
      ADR1 => Ucore_Ufunc_s_cur_oldCol(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_nextaddr_axb_7
    );
  Ucore_Ufunc_un1_nextaddr_axb_8_257 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(13),
      O => Ucore_Ufunc_un1_nextaddr_axb_8
    );
  Ucore_Ufunc_addr_7_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_7_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_8_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(8),
      IB => Ucore_Ufunc_un1_nextaddr_cry_7_O,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_8,
      O => Ucore_Ufunc_addr_7_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_7_O,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_8,
      O => Ucore_Ufunc_un1_nextaddr_s_8_n
    );
  Ucore_Ufunc_addr_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_7_CYINIT_258 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_6_O,
      O => Ucore_Ufunc_addr_7_CYINIT
    );
  Ucore_Ufunc_un1_nextaddr_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(9),
      IB => Ucore_Ufunc_addr_9_CYINIT,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_9,
      O => Ucore_Ufunc_un1_nextaddr_cry_9_O
    );
  Ucore_Ufunc_un1_nextaddr_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_9_CYINIT,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_9,
      O => Ucore_Ufunc_un1_nextaddr_s_9_n
    );
  Ucore_Ufunc_un1_nextaddr_axb_9_259 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(9),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_cur_oldCol(14),
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_nextaddr_axb_9
    );
  Ucore_Ufunc_un1_nextaddr_axb_10_260 : X_LUT4
    generic map(
      INIT => X"55AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(15),
      O => Ucore_Ufunc_un1_nextaddr_axb_10
    );
  Ucore_Ufunc_addr_9_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_9_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_10_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_offset(10),
      IB => Ucore_Ufunc_un1_nextaddr_cry_9_O,
      SEL => Ucore_Ufunc_un1_nextaddr_axb_10,
      O => Ucore_Ufunc_addr_9_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_9_O,
      I1 => Ucore_Ufunc_un1_nextaddr_axb_10,
      O => Ucore_Ufunc_un1_nextaddr_s_10_n
    );
  Ucore_Ufunc_addr_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_9_CYINIT_261 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_8_O,
      O => Ucore_Ufunc_addr_9_CYINIT
    );
  Ucore_Ufunc_addr_11_LOGIC_ZERO_262 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_11_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_cry_11 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_11_LOGIC_ZERO,
      IB => Ucore_Ufunc_addr_11_CYINIT,
      SEL => Ucore_Ufunc_addr_11_FROM,
      O => Ucore_Ufunc_un1_nextaddr_cry_11_O
    );
  Ucore_Ufunc_un1_nextaddr_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_11_CYINIT,
      I1 => Ucore_Ufunc_addr_11_FROM,
      O => Ucore_Ufunc_un1_nextaddr_s_11_n
    );
  Ucore_Ufunc_addr_11_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(11),
      O => Ucore_Ufunc_addr_11_FROM
    );
  Ucore_Ufunc_addr_11_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_addr_11_GROM
    );
  Ucore_Ufunc_addr_11_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_11_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_12_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_12 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_11_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_nextaddr_cry_11_O,
      SEL => Ucore_Ufunc_addr_11_GROM,
      O => Ucore_Ufunc_addr_11_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_12 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_11_O,
      I1 => Ucore_Ufunc_addr_11_GROM,
      O => Ucore_Ufunc_un1_nextaddr_s_12_n
    );
  Ucore_Ufunc_addr_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_11_CYINIT_263 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_10_O,
      O => Ucore_Ufunc_addr_11_CYINIT
    );
  Ucore_Ufunc_addr_13_LOGIC_ZERO_264 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_13_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_cry_13 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_13_LOGIC_ZERO,
      IB => Ucore_Ufunc_addr_13_CYINIT,
      SEL => Ucore_Ufunc_addr_13_FROM,
      O => Ucore_Ufunc_un1_nextaddr_cry_13_O
    );
  Ucore_Ufunc_un1_nextaddr_s_13 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_13_CYINIT,
      I1 => Ucore_Ufunc_addr_13_FROM,
      O => Ucore_Ufunc_un1_nextaddr_s_13_n
    );
  Ucore_Ufunc_addr_13_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(13),
      O => Ucore_Ufunc_addr_13_FROM
    );
  Ucore_Ufunc_addr_13_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(14),
      ADR3 => VCC,
      O => Ucore_Ufunc_addr_13_GROM
    );
  Ucore_Ufunc_addr_13_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_13_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_14_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_14 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_13_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_nextaddr_cry_13_O,
      SEL => Ucore_Ufunc_addr_13_GROM,
      O => Ucore_Ufunc_addr_13_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_14 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_13_O,
      I1 => Ucore_Ufunc_addr_13_GROM,
      O => Ucore_Ufunc_un1_nextaddr_s_14_n
    );
  Ucore_Ufunc_addr_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_13_CYINIT_265 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_12_O,
      O => Ucore_Ufunc_addr_13_CYINIT
    );
  Ucore_Ufunc_addr_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_15_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(15)
    );
  Ucore_Ufunc_addr_15_LOGIC_ZERO_266 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_15_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_cry_15 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_15_LOGIC_ZERO,
      IB => Ucore_Ufunc_addr_15_CYINIT,
      SEL => Ucore_Ufunc_addr_15_FROM,
      O => Ucore_Ufunc_un1_nextaddr_cry_15_O
    );
  Ucore_Ufunc_un1_nextaddr_s_15 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_15_CYINIT,
      I1 => Ucore_Ufunc_addr_15_FROM,
      O => Ucore_Ufunc_un1_nextaddr_s_15_n
    );
  Ucore_Ufunc_addr_15_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(15),
      O => Ucore_Ufunc_addr_15_FROM
    );
  Ucore_Ufunc_addr_15_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_addr_15_GROM
    );
  Ucore_Ufunc_addr_15_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_15_CYMUXG,
      O => Ucore_Ufunc_un1_nextaddr_cry_16_O
    );
  Ucore_Ufunc_un1_nextaddr_cry_16 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_15_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_nextaddr_cry_15_O,
      SEL => Ucore_Ufunc_addr_15_GROM,
      O => Ucore_Ufunc_addr_15_CYMUXG
    );
  Ucore_Ufunc_un1_nextaddr_s_16 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_15_O,
      I1 => Ucore_Ufunc_addr_15_GROM,
      O => Ucore_Ufunc_un1_nextaddr_s_16_n
    );
  Ucore_Ufunc_addr_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_15_CYINIT_267 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_14_O,
      O => Ucore_Ufunc_addr_15_CYINIT
    );
  Ucore_Ufunc_addr_17_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_17_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_17_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(17)
    );
  Ucore_Ufunc_addr_17_LOGIC_ZERO_268 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_17_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_cry_17 : X_MUX2
    port map (
      IA => Ucore_Ufunc_addr_17_LOGIC_ZERO,
      IB => Ucore_Ufunc_addr_17_CYINIT,
      SEL => Ucore_Ufunc_addr_17_FROM,
      O => Ucore_Ufunc_un1_nextaddr_cry_17_O
    );
  Ucore_Ufunc_un1_nextaddr_s_17 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_17_CYINIT,
      I1 => Ucore_Ufunc_addr_17_FROM,
      O => Ucore_Ufunc_un1_nextaddr_s_17_n
    );
  Ucore_Ufunc_addr_17_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(17),
      O => Ucore_Ufunc_addr_17_FROM
    );
  Ucore_Ufunc_BEL_7 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(18),
      O => Ucore_Ufunc_SIG_7
    );
  Ucore_Ufunc_un1_nextaddr_s_18 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un1_nextaddr_cry_17_O,
      I1 => Ucore_Ufunc_SIG_7,
      O => Ucore_Ufunc_un1_nextaddr_s_18_n
    );
  Ucore_Ufunc_addr_17_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_17_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_17_CYINIT_269 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_nextaddr_cry_16_O,
      O => Ucore_Ufunc_addr_17_CYINIT
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ONE_270 : X_ONE
    port map (
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ONE
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ZERO_271 : X_ZERO
    port map (
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ONE,
      SEL => Ucore_Ufunc_N_27,
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_1_O
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_9 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(1),
      ADR1 => Ucore_Ufunc_temp2(8),
      ADR2 => Ucore_Ufunc_temp2(0),
      ADR3 => Ucore_Ufunc_temp2(9),
      O => Ucore_Ufunc_N_27
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_36 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(11),
      ADR1 => Ucore_Ufunc_temp2(10),
      ADR2 => Ucore_Ufunc_temp2(3),
      ADR3 => Ucore_Ufunc_temp2(2),
      O => Ucore_Ufunc_N_3
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_CYMUXG,
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_28 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_1_0_I_1_O,
      SEL => Ucore_Ufunc_N_3,
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O_CYMUXG
    );
  I_10_n_LOGIC_ZERO_272 : X_ZERO
    port map (
      O => I_10_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_19 : X_MUX2
    port map (
      IA => I_10_n_LOGIC_ZERO,
      IB => I_10_n_CYINIT,
      SEL => Ucore_Ufunc_N_11,
      O => Ucore_Ufunc_un1_high_temp2_1_0_I_19_O
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_27 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(12),
      ADR1 => Ucore_Ufunc_temp2(5),
      ADR2 => Ucore_Ufunc_temp2(4),
      ADR3 => Ucore_Ufunc_temp2(13),
      O => Ucore_Ufunc_N_11
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_18 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(6),
      ADR1 => Ucore_Ufunc_temp2(14),
      ADR2 => Ucore_Ufunc_temp2(15),
      ADR3 => Ucore_Ufunc_temp2(7),
      O => Ucore_Ufunc_N_19_0
    );
  I_10_n_COUTUSED : X_BUF
    port map (
      I => I_10_n_CYMUXG,
      O => I_10_n
    );
  Ucore_Ufunc_un1_high_temp2_1_0_I_10 : X_MUX2
    port map (
      IA => I_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_high_temp2_1_0_I_19_O,
      SEL => Ucore_Ufunc_N_19_0,
      O => I_10_n_CYMUXG
    );
  I_10_n_CYINIT_273 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_high_temp2_1_0_I_28_O,
      O => I_10_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ONE_274 : X_ONE
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ONE
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ZERO_275 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_0_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_s_cur_oldRow(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldRow(8),
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_1_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_1_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_0_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_0_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYINIT_276 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_LOGIC_ONE,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n_CYINIT
    );
  Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GWEAND_277 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FWEAND_278 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU31_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU31_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU31_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N475_RAM32X1_GRAMS
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_LOGIC_ZERO_279 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_2_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_s_cur_oldRow(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldRow(10),
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_3_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_3_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_2_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_2_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYINIT_280 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_1_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_LOGIC_ZERO_281 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_4_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_s_cur_oldRow(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldRow(12),
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_5_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_5_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_4_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_4_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYINIT_282 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_3_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_LOGIC_ZERO_283 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_6_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_s_cur_oldRow(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldRow(14),
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_7_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_7_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_6_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_6_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYINIT_284 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_5_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_s_cur_oldRow_15_rt,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_XORF
    );
  Ucore_Ufunc_s_cur_oldRow_15_rt_285 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_s_cur_oldRow(15),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_15_rt
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_CYINIT_286 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldRow_cry_7_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_0_LOGIC_ZERO_287 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_0_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_0_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_0_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(0),
      O => Ucore_Ufunc_ram_writeAddr_cry_0_O
    );
  Ucore_Ufunc_ram_writeAddr_s_0_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_0_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(0),
      O => Ucore_Ufunc_ram_writeAddr_s(0)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_0_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(0)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_1_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_writeAddr(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(1)
    );
  Ucore_Ufunc_ram_writeAddr_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_0_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_1_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_1_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_0_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(1),
      O => Ucore_Ufunc_ram_writeAddr_0_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_1_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_0_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(1),
      O => Ucore_Ufunc_ram_writeAddr_s(1)
    );
  Ucore_Ufunc_ram_writeAddr_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_0_CYINIT_288 : X_BUF
    port map (
      I => Ucore_Ufunc_N_218,
      O => Ucore_Ufunc_ram_writeAddr_0_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_2_LOGIC_ZERO_289 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_2_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_2_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_2_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(2),
      O => Ucore_Ufunc_ram_writeAddr_cry_2_O
    );
  Ucore_Ufunc_ram_writeAddr_s_2_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_2_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(2),
      O => Ucore_Ufunc_ram_writeAddr_s(2)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_2_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(2),
      ADR2 => Ucore_Ufunc_N_218,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(2)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_3_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(3),
      ADR2 => Ucore_Ufunc_N_218,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(3)
    );
  Ucore_Ufunc_ram_writeAddr_2_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_2_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_3_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_3_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_2_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(3),
      O => Ucore_Ufunc_ram_writeAddr_2_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_3_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_2_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(3),
      O => Ucore_Ufunc_ram_writeAddr_s(3)
    );
  Ucore_Ufunc_ram_writeAddr_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_2_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_2_CYINIT_290 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_1_O,
      O => Ucore_Ufunc_ram_writeAddr_2_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_4_LOGIC_ZERO_291 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_4_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_4_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_4_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(4),
      O => Ucore_Ufunc_ram_writeAddr_cry_4_O
    );
  Ucore_Ufunc_ram_writeAddr_s_4_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_4_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(4),
      O => Ucore_Ufunc_ram_writeAddr_s(4)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_4_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(4),
      ADR2 => Ucore_Ufunc_N_218,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(4)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_5_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(5),
      ADR2 => Ucore_Ufunc_N_218,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(5)
    );
  Ucore_Ufunc_ram_writeAddr_4_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_4_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_5_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_5_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_4_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(5),
      O => Ucore_Ufunc_ram_writeAddr_4_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_5_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_4_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(5),
      O => Ucore_Ufunc_ram_writeAddr_s(5)
    );
  Ucore_Ufunc_ram_writeAddr_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_4_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_4_CYINIT_292 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_3_O,
      O => Ucore_Ufunc_ram_writeAddr_4_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_6_LOGIC_ZERO_293 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_6_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_6_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_6_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(6),
      O => Ucore_Ufunc_ram_writeAddr_cry_6_O
    );
  Ucore_Ufunc_ram_writeAddr_s_6_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_6_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(6),
      O => Ucore_Ufunc_ram_writeAddr_s(6)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_6_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(6)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_7_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(7)
    );
  Ucore_Ufunc_ram_writeAddr_6_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_6_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_7_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_7_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_6_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(7),
      O => Ucore_Ufunc_ram_writeAddr_6_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_7_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_6_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(7),
      O => Ucore_Ufunc_ram_writeAddr_s(7)
    );
  Ucore_Ufunc_ram_writeAddr_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_6_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_6_CYINIT_294 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_5_O,
      O => Ucore_Ufunc_ram_writeAddr_6_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_8_LOGIC_ZERO_295 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_8_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_8_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_8_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_8_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(8),
      O => Ucore_Ufunc_ram_writeAddr_cry_8_O
    );
  Ucore_Ufunc_ram_writeAddr_s_8_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_8_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(8),
      O => Ucore_Ufunc_ram_writeAddr_s(8)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_8_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(8)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_9_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(9)
    );
  Ucore_Ufunc_ram_writeAddr_8_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_8_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_9_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_9_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_8_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_8_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(9),
      O => Ucore_Ufunc_ram_writeAddr_8_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_9_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_8_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(9),
      O => Ucore_Ufunc_ram_writeAddr_s(9)
    );
  Ucore_Ufunc_ram_writeAddr_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_8_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_8_CYINIT_296 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_7_O,
      O => Ucore_Ufunc_ram_writeAddr_8_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_10_LOGIC_ZERO_297 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_10_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_10_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_10_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_10_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(10),
      O => Ucore_Ufunc_ram_writeAddr_cry_10_O
    );
  Ucore_Ufunc_ram_writeAddr_s_10_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_10_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(10),
      O => Ucore_Ufunc_ram_writeAddr_s(10)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_10_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(10),
      ADR1 => Ucore_Ufunc_N_218,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(10)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_11_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_218,
      ADR2 => Ucore_Ufunc_ram_writeAddr(11),
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(11)
    );
  Ucore_Ufunc_ram_writeAddr_10_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_10_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_11_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_11_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_10_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_10_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(11),
      O => Ucore_Ufunc_ram_writeAddr_10_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_11_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_10_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(11),
      O => Ucore_Ufunc_ram_writeAddr_s(11)
    );
  Ucore_Ufunc_ram_writeAddr_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_10_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_10_CYINIT_298 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_9_O,
      O => Ucore_Ufunc_ram_writeAddr_10_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_12_LOGIC_ZERO_299 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_12_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_12_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_12_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_12_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(12),
      O => Ucore_Ufunc_ram_writeAddr_cry_12_O
    );
  Ucore_Ufunc_ram_writeAddr_s_12_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_12_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(12),
      O => Ucore_Ufunc_ram_writeAddr_s(12)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_12_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(12),
      O => Ucore_Ufunc_ram_writeAddr_qxu(12)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_13_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_writeAddr(13),
      ADR3 => Ucore_Ufunc_N_218,
      O => Ucore_Ufunc_ram_writeAddr_qxu(13)
    );
  Ucore_Ufunc_ram_writeAddr_12_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_12_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_13_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_13_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_12_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_12_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(13),
      O => Ucore_Ufunc_ram_writeAddr_12_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_13_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_12_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(13),
      O => Ucore_Ufunc_ram_writeAddr_s(13)
    );
  Ucore_Ufunc_ram_writeAddr_12_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_12_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_12_CYINIT_300 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_11_O,
      O => Ucore_Ufunc_ram_writeAddr_12_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_14_LOGIC_ZERO_301 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_14_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_14_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_14_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_14_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(14),
      O => Ucore_Ufunc_ram_writeAddr_cry_14_O
    );
  Ucore_Ufunc_ram_writeAddr_s_14_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_14_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(14),
      O => Ucore_Ufunc_ram_writeAddr_s(14)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_14_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(14),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_218,
      O => Ucore_Ufunc_ram_writeAddr_qxu(14)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_15_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(15),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(15)
    );
  Ucore_Ufunc_ram_writeAddr_14_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_14_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_15_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_15_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_14_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_14_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(15),
      O => Ucore_Ufunc_ram_writeAddr_14_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_15_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_14_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(15),
      O => Ucore_Ufunc_ram_writeAddr_s(15)
    );
  Ucore_Ufunc_ram_writeAddr_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_14_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_14_CYINIT_302 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_13_O,
      O => Ucore_Ufunc_ram_writeAddr_14_CYINIT
    );
  Ucore_Ufunc_ram_writeAddr_16_LOGIC_ZERO_303 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_writeAddr_16_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_writeAddr_cry_16_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_16_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_16_CYINIT,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(16),
      O => Ucore_Ufunc_ram_writeAddr_cry_16_O
    );
  Ucore_Ufunc_ram_writeAddr_s_16_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_16_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(16),
      O => Ucore_Ufunc_ram_writeAddr_s(16)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_16_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_218,
      ADR1 => Ucore_Ufunc_ram_writeAddr(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(16)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_17_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(17),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_218,
      O => Ucore_Ufunc_ram_writeAddr_qxu(17)
    );
  Ucore_Ufunc_ram_writeAddr_16_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_16_CYMUXG,
      O => Ucore_Ufunc_ram_writeAddr_cry_17_O
    );
  Ucore_Ufunc_ram_writeAddr_cry_17_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_writeAddr_16_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_writeAddr_cry_16_O,
      SEL => Ucore_Ufunc_ram_writeAddr_qxu(17),
      O => Ucore_Ufunc_ram_writeAddr_16_CYMUXG
    );
  Ucore_Ufunc_ram_writeAddr_s_17_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_cry_16_O,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(17),
      O => Ucore_Ufunc_ram_writeAddr_s(17)
    );
  Ucore_Ufunc_ram_writeAddr_16_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_16_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_16_CYINIT_304 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_15_O,
      O => Ucore_Ufunc_ram_writeAddr_16_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ZERO_305 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ONE_306 : X_ONE
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ONE
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ZERO,
      SEL => Ucore_Ufunc_N_166_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_0_O
    );
  Ucore_Ufunc_N_166_i_307 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_166_i
    );
  Ucore_Ufunc_N_167_i_308 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(5),
      ADR3 => VCC,
      O => Ucore_Ufunc_N_167_i
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_1_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_1_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_1_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_1_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_0_O,
      SEL => Ucore_Ufunc_N_167_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_0_O,
      I1 => Ucore_Ufunc_N_167_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_1_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2_n_LOGIC_ONE_309 : X_ONE
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_LOGIC_ONE
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_N_168_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_2_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_N_168_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORF
    );
  Ucore_Ufunc_N_168_i_310 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_168_i
    );
  Ucore_Ufunc_N_169_i_311 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_169_i
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_3_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_3_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_2_O,
      SEL => Ucore_Ufunc_N_169_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_2_O,
      I1 => Ucore_Ufunc_N_169_i,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYINIT_312 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_1_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_2_n_CYINIT
    );
  Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GWEAND_313 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FWEAND_314 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU23_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU23_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU23_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(3),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N392_RAM32X1_GRAMS
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_LOGIC_ZERO_315 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_4_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORF
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_FROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_GROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_5_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_5_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_4_O,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_4_O,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYINIT_316 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_3_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_4_n_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_LOGIC_ZERO_317 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_6_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORF
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_FROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_GROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_7_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_7_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_6_O,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_6_O,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYINIT_318 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_5_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_6_n_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_LOGIC_ZERO_319 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYINIT,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_8_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORF
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_FROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_GROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_9_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_9_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_8_O,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_8_O,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYINIT_320 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_7_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_8_n_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_LOGIC_ZERO_321 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYINIT,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_10_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYINIT,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORF
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_FROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_GROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_11_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_11_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_11 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_10_O,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_10_O,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYINIT_322 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_9_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_10_n_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_LOGIC_ZERO_323 : X_ZERO
    port map (
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_12 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYINIT,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_12_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYINIT,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORF
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(16),
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_FROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(17),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_GROM
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYMUXG,
      O => Ucore_Ufunc_un9_nextaddr_offset_cry_13_O
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORG,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_13_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_cry_13 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un9_nextaddr_offset_cry_12_O,
      SEL => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYMUXG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_13 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_cry_12_O,
      I1 => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_XORG
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYINIT_324 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_11_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_12_n_CYINIT
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_14 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un9_nextaddr_offset_s_14_n_CYINIT,
      I1 => Ucore_Ufunc_SIG_17,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_14_n_XORF
    );
  Ucore_Ufunc_BEL_17 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(18),
      ADR3 => VCC,
      O => Ucore_Ufunc_SIG_17
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_14_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_s_14_n_XORF,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_14_n
    );
  Ucore_Ufunc_un9_nextaddr_offset_s_14_n_CYINIT_325 : X_BUF
    port map (
      I => Ucore_Ufunc_un9_nextaddr_offset_cry_13_O,
      O => Ucore_Ufunc_un9_nextaddr_offset_s_14_n_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_0_LOGIC_ZERO_326 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_0_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_lcry : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_0_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_0_FROM,
      O => Ucore_Ufunc_ram_readAddr_lcry_O
    );
  Ucore_Ufunc_N_259_i_327 : X_LUT4
    generic map(
      INIT => X"BFBF"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_1,
      ADR1 => Ucore_Ufunc_N_249,
      ADR2 => Ucore_Ufunc_un1_temp2_3,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_0_FROM
    );
  Ucore_Ufunc_ram_readAddr_qxu_0_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(0),
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(0)
    );
  Ucore_Ufunc_ram_readAddr_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_0_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_0_O
    );
  Ucore_Ufunc_ram_readAddr_0_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_0_FROM,
      O => Ucore_Ufunc_N_259_i
    );
  Ucore_Ufunc_ram_readAddr_cry_0_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_lcry_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(0),
      O => Ucore_Ufunc_ram_readAddr_0_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_0_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_lcry_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(0),
      O => Ucore_Ufunc_ram_readAddr_s(0)
    );
  Ucore_Ufunc_ram_readAddr_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_0_CYINIT_328 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_next_write_data37_8_16_n,
      O => Ucore_Ufunc_ram_readAddr_0_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_1_LOGIC_ZERO_329 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_1_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_1_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_1_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_1_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(1),
      O => Ucore_Ufunc_ram_readAddr_cry_1_O
    );
  Ucore_Ufunc_ram_readAddr_s_1_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_1_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(1),
      O => Ucore_Ufunc_ram_readAddr_s(1)
    );
  Ucore_Ufunc_ram_readAddr_qxu_1_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(1),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(1)
    );
  Ucore_Ufunc_ram_readAddr_qxu_2_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_259_i,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(2),
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_qxu(2)
    );
  Ucore_Ufunc_ram_readAddr_1_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_1_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_2_O
    );
  Ucore_Ufunc_ram_readAddr_cry_2_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_1_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_1_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(2),
      O => Ucore_Ufunc_ram_readAddr_1_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_2_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_1_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(2),
      O => Ucore_Ufunc_ram_readAddr_s(2)
    );
  Ucore_Ufunc_ram_readAddr_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_1_CYINIT_330 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_0_O,
      O => Ucore_Ufunc_ram_readAddr_1_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_3_LOGIC_ZERO_331 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_3_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_3_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_3_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_3_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(3),
      O => Ucore_Ufunc_ram_readAddr_cry_3_O
    );
  Ucore_Ufunc_ram_readAddr_s_3_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_3_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(3),
      O => Ucore_Ufunc_ram_readAddr_s(3)
    );
  Ucore_Ufunc_ram_readAddr_qxu_3_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_259_i,
      ADR1 => Ucore_Ufunc_ram_readAddr(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_qxu(3)
    );
  Ucore_Ufunc_ram_readAddr_qxu_4_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_N_259_i,
      ADR3 => Ucore_Ufunc_ram_readAddr(4),
      O => Ucore_Ufunc_ram_readAddr_qxu(4)
    );
  Ucore_Ufunc_ram_readAddr_3_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_3_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_4_O
    );
  Ucore_Ufunc_ram_readAddr_cry_4_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_3_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_3_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(4),
      O => Ucore_Ufunc_ram_readAddr_3_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_4_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_3_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(4),
      O => Ucore_Ufunc_ram_readAddr_s(4)
    );
  Ucore_Ufunc_ram_readAddr_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_3_CYINIT_332 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_2_O,
      O => Ucore_Ufunc_ram_readAddr_3_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_5_LOGIC_ZERO_333 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_5_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_5_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_5_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_5_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(5),
      O => Ucore_Ufunc_ram_readAddr_cry_5_O
    );
  Ucore_Ufunc_ram_readAddr_s_5_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_5_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(5),
      O => Ucore_Ufunc_ram_readAddr_s(5)
    );
  Ucore_Ufunc_ram_readAddr_qxu_5_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(5),
      ADR2 => Ucore_Ufunc_N_259_i,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_qxu(5)
    );
  Ucore_Ufunc_ram_readAddr_qxu_6_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_259_i,
      ADR2 => Ucore_Ufunc_ram_readAddr(6),
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_qxu(6)
    );
  Ucore_Ufunc_ram_readAddr_5_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_5_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_6_O
    );
  Ucore_Ufunc_ram_readAddr_cry_6_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_5_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_5_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(6),
      O => Ucore_Ufunc_ram_readAddr_5_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_6_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_5_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(6),
      O => Ucore_Ufunc_ram_readAddr_s(6)
    );
  Ucore_Ufunc_ram_readAddr_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_5_CYINIT_334 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_4_O,
      O => Ucore_Ufunc_ram_readAddr_5_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_7_LOGIC_ZERO_335 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_7_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_7_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_7_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_7_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(7),
      O => Ucore_Ufunc_ram_readAddr_cry_7_O
    );
  Ucore_Ufunc_ram_readAddr_s_7_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_7_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(7),
      O => Ucore_Ufunc_ram_readAddr_s(7)
    );
  Ucore_Ufunc_ram_readAddr_qxu_7_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(7),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(7)
    );
  Ucore_Ufunc_ram_readAddr_qxu_8_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_N_259_i,
      ADR3 => Ucore_Ufunc_ram_readAddr(8),
      O => Ucore_Ufunc_ram_readAddr_qxu(8)
    );
  Ucore_Ufunc_ram_readAddr_7_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_7_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_8_O
    );
  Ucore_Ufunc_ram_readAddr_cry_8_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_7_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_7_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(8),
      O => Ucore_Ufunc_ram_readAddr_7_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_8_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_7_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(8),
      O => Ucore_Ufunc_ram_readAddr_s(8)
    );
  Ucore_Ufunc_ram_readAddr_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_7_CYINIT_336 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_6_O,
      O => Ucore_Ufunc_ram_readAddr_7_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_9_LOGIC_ZERO_337 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_9_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_9_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_9_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_9_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(9),
      O => Ucore_Ufunc_ram_readAddr_cry_9_O
    );
  Ucore_Ufunc_ram_readAddr_s_9_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_9_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(9),
      O => Ucore_Ufunc_ram_readAddr_s(9)
    );
  Ucore_Ufunc_ram_readAddr_qxu_9_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_259_i,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_readAddr(9),
      O => Ucore_Ufunc_ram_readAddr_qxu(9)
    );
  Ucore_Ufunc_ram_readAddr_qxu_10_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_259_i,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(10),
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_readAddr_qxu(10)
    );
  Ucore_Ufunc_ram_readAddr_9_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_9_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_10_O
    );
  Ucore_Ufunc_ram_readAddr_cry_10_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_9_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_9_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(10),
      O => Ucore_Ufunc_ram_readAddr_9_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_10_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_9_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(10),
      O => Ucore_Ufunc_ram_readAddr_s(10)
    );
  Ucore_Ufunc_ram_readAddr_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_9_CYINIT_338 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_8_O,
      O => Ucore_Ufunc_ram_readAddr_9_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_11_LOGIC_ZERO_339 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_11_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_11_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_11_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_11_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(11),
      O => Ucore_Ufunc_ram_readAddr_cry_11_O
    );
  Ucore_Ufunc_ram_readAddr_s_11_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_11_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(11),
      O => Ucore_Ufunc_ram_readAddr_s(11)
    );
  Ucore_Ufunc_ram_readAddr_qxu_11_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_readAddr(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(11)
    );
  Ucore_Ufunc_ram_readAddr_qxu_12_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_259_i,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_readAddr(12),
      O => Ucore_Ufunc_ram_readAddr_qxu(12)
    );
  Ucore_Ufunc_ram_readAddr_11_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_11_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_12_O
    );
  Ucore_Ufunc_ram_readAddr_cry_12_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_11_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_11_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(12),
      O => Ucore_Ufunc_ram_readAddr_11_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_12_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_11_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(12),
      O => Ucore_Ufunc_ram_readAddr_s(12)
    );
  Ucore_Ufunc_ram_readAddr_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_11_CYINIT_340 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_10_O,
      O => Ucore_Ufunc_ram_readAddr_11_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_13_LOGIC_ZERO_341 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_13_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_13_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_13_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_13_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(13),
      O => Ucore_Ufunc_ram_readAddr_cry_13_O
    );
  Ucore_Ufunc_ram_readAddr_s_13_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_13_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(13),
      O => Ucore_Ufunc_ram_readAddr_s(13)
    );
  Ucore_Ufunc_ram_readAddr_qxu_13_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(13),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(13)
    );
  Ucore_Ufunc_ram_readAddr_qxu_14_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(14),
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(14)
    );
  Ucore_Ufunc_ram_readAddr_13_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_13_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_14_O
    );
  Ucore_Ufunc_ram_readAddr_cry_14_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_13_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_13_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(14),
      O => Ucore_Ufunc_ram_readAddr_13_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_14_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_13_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(14),
      O => Ucore_Ufunc_ram_readAddr_s(14)
    );
  Ucore_Ufunc_ram_readAddr_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_13_CYINIT_342 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_12_O,
      O => Ucore_Ufunc_ram_readAddr_13_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_15_LOGIC_ZERO_343 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_15_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_15_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_15_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_15_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(15),
      O => Ucore_Ufunc_ram_readAddr_cry_15_O
    );
  Ucore_Ufunc_ram_readAddr_s_15_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_15_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(15),
      O => Ucore_Ufunc_ram_readAddr_s(15)
    );
  Ucore_Ufunc_ram_readAddr_qxu_15_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_readAddr(15),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(15)
    );
  Ucore_Ufunc_ram_readAddr_qxu_16_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(16),
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(16)
    );
  Ucore_Ufunc_ram_readAddr_15_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_15_CYMUXG,
      O => Ucore_Ufunc_ram_readAddr_cry_16_O
    );
  Ucore_Ufunc_ram_readAddr_cry_16_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_15_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_cry_15_O,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(16),
      O => Ucore_Ufunc_ram_readAddr_15_CYMUXG
    );
  Ucore_Ufunc_ram_readAddr_s_16_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_15_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(16),
      O => Ucore_Ufunc_ram_readAddr_s(16)
    );
  Ucore_Ufunc_ram_readAddr_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_15_CYINIT_344 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_14_O,
      O => Ucore_Ufunc_ram_readAddr_15_CYINIT
    );
  Ucore_Ufunc_ram_readAddr_17_LOGIC_ZERO_345 : X_ZERO
    port map (
      O => Ucore_Ufunc_ram_readAddr_17_LOGIC_ZERO
    );
  Ucore_Ufunc_ram_readAddr_cry_17_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_ram_readAddr_17_LOGIC_ZERO,
      IB => Ucore_Ufunc_ram_readAddr_17_CYINIT,
      SEL => Ucore_Ufunc_ram_readAddr_qxu(17),
      O => Ucore_Ufunc_ram_readAddr_cry_17_O
    );
  Ucore_Ufunc_ram_readAddr_s_17_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_17_CYINIT,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(17),
      O => Ucore_Ufunc_ram_readAddr_s(17)
    );
  Ucore_Ufunc_ram_readAddr_qxu_17_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(17),
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(17)
    );
  Ucore_Ufunc_ram_readAddr_qxu_0_18_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_readAddr(18),
      ADR3 => Ucore_Ufunc_N_259_i,
      O => Ucore_Ufunc_ram_readAddr_qxu(18)
    );
  Ucore_Ufunc_ram_readAddr_s_18_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_readAddr_cry_17_O,
      I1 => Ucore_Ufunc_ram_readAddr_qxu(18),
      O => Ucore_Ufunc_ram_readAddr_s(18)
    );
  Ucore_Ufunc_ram_readAddr_17_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_readAddr_17_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_readAddr_17_CYINIT_346 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_readAddr_cry_16_O,
      O => Ucore_Ufunc_ram_readAddr_17_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_1_n_LOGIC_ZERO_347 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_0 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_LOGIC_ZERO,
      SEL => Ucore_Ufunc_N_126_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_0_O
    );
  Ucore_Ufunc_N_126_i_348 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => Ucore_Ufunc_addr_offset(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_126_i
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_1_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_5,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(4),
      O => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_GROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_1_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_1_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_1_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_1_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_1 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_5,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_0_O,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_0_O,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_1_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2_n_LOGIC_ONE_349 : X_ONE
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_LOGIC_ONE
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_N_127_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_2_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_N_127_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORF
    );
  Ucore_Ufunc_N_127_i_350 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_127_i
    );
  Ucore_Ufunc_N_128_i_351 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(6),
      O => Ucore_Ufunc_N_128_i
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_3_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_3_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_2_O,
      SEL => Ucore_Ufunc_N_128_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_2_O,
      I1 => Ucore_Ufunc_N_128_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYINIT_352 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_1_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_2_n_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_4 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_6,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_4_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4_n_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_6,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(7),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_FROM
    );
  Ucore_Ufunc_N_129_i_353 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(8),
      O => Ucore_Ufunc_N_129_i
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_5_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_5_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_5 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_0,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_4_O,
      SEL => Ucore_Ufunc_N_129_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_4_O,
      I1 => Ucore_Ufunc_N_129_i,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYINIT_354 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_3_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_4_n_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_LOGIC_ZERO_355 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_6_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_FROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(10),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_GROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_7_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_7_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_6_O,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_6_O,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYINIT_356 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_5_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_6_n_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_LOGIC_ZERO_357 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_8_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(11),
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_FROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(12),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_GROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_9_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_9_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_8_O,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_8_O,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYINIT_358 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_7_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_8_n_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_LOGIC_ZERO_359 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_10_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(13),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_FROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(14),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_GROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_11_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_11_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_11 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_10_O,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_10_O,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYINIT_360 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_9_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_10_n_CYINIT
    );
  Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GWEAND_361 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FWEAND_362 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU14_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU14_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU14_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N308_RAM32X1_GRAMS
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_LOGIC_ZERO_363 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_12 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_12_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(15),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_FROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(16),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_GROM
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYMUXG,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_13_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_13_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_13 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_cry_12_O,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYMUXG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_13 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_12_O,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYINIT_364 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_11_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_12_n_CYINIT
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14_n_LOGIC_ZERO_365 : X_ZERO
    port map (
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un14_nextaddr_offset_cry_14 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_CYINIT,
      SEL => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_cry_14_O
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_CYINIT,
      I1 => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_FROM,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORF
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14_n_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(17),
      ADR3 => VCC,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_FROM
    );
  Ucore_Ufunc_BEL_27 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(18),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_SIG_27
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORF,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORG,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_15_n
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_15 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un14_nextaddr_offset_cry_14_O,
      I1 => Ucore_Ufunc_SIG_27,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_XORG
    );
  Ucore_Ufunc_un14_nextaddr_offset_s_14_n_CYINIT_366 : X_BUF
    port map (
      I => Ucore_Ufunc_un14_nextaddr_offset_cry_13_O,
      O => Ucore_Ufunc_un14_nextaddr_offset_s_14_n_CYINIT
    );
  Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_LOGIC_ZERO_367 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Ualu_C446_C2_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(0),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_LOGIC_ZERO,
      SEL => Ucore_Uusb_N1515,
      O => Ucore_Uusb_Uuc_Ualu_C446_C2_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C2_C0 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(0),
      ADR3 => VCC,
      O => Ucore_Uusb_N1515
    );
  Ucore_Uusb_Uuc_Ualu_C446_C3_C0 : X_LUT4
    generic map(
      INIT => X"A695"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_Utmp2_TMP2(1),
      ADR3 => Ucore_Uusb_Uuc_AO(1),
      O => Ucore_Uusb_N1516
    );
  Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_CYMUXG,
      O => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C3_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(1),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C2_C1_O,
      SEL => Ucore_Uusb_N1516,
      O => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O_CYMUXG
    );
  Ucore_Uusb_Uuc_Ualu_C446_C4_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(2),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYINIT,
      SEL => Ucore_Uusb_N1517,
      O => Ucore_Uusb_Uuc_Ualu_C446_C4_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C4_C0 : X_LUT4
    generic map(
      INIT => X"A599"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR1 => Ucore_Uusb_Uuc_AO(2),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_TMP2(2),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_sel,
      O => Ucore_Uusb_N1517
    );
  Ucore_Uusb_Uuc_Ualu_C446_C5_C0 : X_LUT4
    generic map(
      INIT => X"99A5"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(3),
      ADR2 => Ucore_Uusb_Uuc_AO(3),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_sel,
      O => Ucore_Uusb_N1518
    );
  Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYMUXG,
      O => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C5_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(3),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C4_C1_O,
      SEL => Ucore_Uusb_N1518,
      O => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYMUXG
    );
  Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYINIT_368 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C3_C1_O,
      O => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O_CYINIT
    );
  Ucore_Uusb_Uuc_Ualu_C446_C6_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(4),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYINIT,
      SEL => Ucore_Uusb_N1519,
      O => Ucore_Uusb_Uuc_Ualu_C446_C6_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C6_C0 : X_LUT4
    generic map(
      INIT => X"A959"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR1 => Ucore_Uusb_Uuc_AO(4),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(4),
      O => Ucore_Uusb_N1519
    );
  Ucore_Uusb_Uuc_Ualu_C446_C7_C0 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR1 => Ucore_Uusb_Uuc_BUS10875(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_N1520
    );
  Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYMUXG,
      O => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C7_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(5),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C6_C1_O,
      SEL => Ucore_Uusb_N1520,
      O => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYMUXG
    );
  Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYINIT_369 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C5_C1_O,
      O => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O_CYINIT
    );
  Ucore_Uusb_Uuc_Ualu_C446_C8_C1 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(6),
      IB => Ucore_Uusb_Uuc_Ualu_N1358_CYINIT,
      SEL => Ucore_Uusb_N1521,
      O => Ucore_Uusb_Uuc_Ualu_C446_C8_C1_O
    );
  Ucore_Uusb_Uuc_Ualu_C446_C8_C0 : X_LUT4
    generic map(
      INIT => X"9A95"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(6),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_Uuc_AO(6),
      O => Ucore_Uusb_N1521
    );
  Ucore_Uusb_Uuc_Ualu_C446_C9_C0 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(7),
      ADR3 => VCC,
      O => Ucore_Uusb_N1522
    );
  Ucore_Uusb_Uuc_Ualu_N1358_COUTUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_N1358_CYMUXG,
      O => Ucore_Uusb_Uuc_Ualu_N1358
    );
  Ucore_Uusb_Uuc_Ualu_C446_C9_C2 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_BUS10881(7),
      IB => Ucore_Uusb_Uuc_Ualu_C446_C8_C1_O,
      SEL => Ucore_Uusb_N1522,
      O => Ucore_Uusb_Uuc_Ualu_N1358_CYMUXG
    );
  Ucore_Uusb_Uuc_Ualu_N1358_CYINIT_370 : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C446_C7_C1_O,
      O => Ucore_Uusb_Uuc_Ualu_N1358_CYINIT
    );
  Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ONE_371 : X_ONE
    port map (
      O => Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ONE
    );
  Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ZERO_372 : X_ZERO
    port map (
      O => Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_low_temp2_0_I_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ONE,
      SEL => Ucore_Ufunc_N_59_rt,
      O => Ucore_Ufunc_un1_low_temp2_0_I_1_O
    );
  Ucore_Ufunc_N_59_rt_373 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_N_59,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_59_rt
    );
  Ucore_Ufunc_N_11_0_rt_374 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_11_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_11_0_rt
    );
  Ucore_Ufunc_un1_low_temp2_0_I_28_O_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_low_temp2_0_I_28_O_CYMUXG,
      O => Ucore_Ufunc_un1_low_temp2_0_I_28_O
    );
  Ucore_Ufunc_un1_low_temp2_0_I_28 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un1_low_temp2_0_I_28_O_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_low_temp2_0_I_1_O,
      SEL => Ucore_Ufunc_N_11_0_rt,
      O => Ucore_Ufunc_un1_low_temp2_0_I_28_O_CYMUXG
    );
  I_10_n_1_LOGIC_ZERO_375 : X_ZERO
    port map (
      O => I_10_n_1_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_low_temp2_0_I_19 : X_MUX2
    port map (
      IA => I_10_n_1_LOGIC_ZERO,
      IB => I_10_n_1_CYINIT,
      SEL => Ucore_Ufunc_N_19_rt,
      O => Ucore_Ufunc_un1_low_temp2_0_I_19_O
    );
  Ucore_Ufunc_N_19_rt_376 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_N_19,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_19_rt
    );
  Ucore_Ufunc_N_35_rt_377 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_35,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_35_rt
    );
  I_10_n_1_COUTUSED : X_BUF
    port map (
      I => I_10_n_1_CYMUXG,
      O => I_10_n_1
    );
  Ucore_Ufunc_un1_low_temp2_0_I_10 : X_MUX2
    port map (
      IA => I_10_n_1_LOGIC_ZERO,
      IB => Ucore_Ufunc_un1_low_temp2_0_I_19_O,
      SEL => Ucore_Ufunc_N_35_rt,
      O => I_10_n_1_CYMUXG
    );
  I_10_n_1_CYINIT_378 : X_BUF
    port map (
      I => Ucore_Ufunc_un1_low_temp2_0_I_28_O,
      O => I_10_n_1_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ZERO_379 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ONE_380 : X_ONE
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ONE
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ZERO,
      SEL => Ucore_Ufunc_N_121_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_0_O
    );
  Ucore_Ufunc_N_121_i_381 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(3),
      ADR3 => VCC,
      O => Ucore_Ufunc_N_121_i
    );
  Ucore_Ufunc_N_122_i_382 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_addr_offset(4),
      O => Ucore_Ufunc_N_122_i
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_1_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_1_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_1_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_1_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_0_O,
      SEL => Ucore_Ufunc_N_122_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_0_O,
      I1 => Ucore_Ufunc_N_122_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_1_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2_n_LOGIC_ONE_383 : X_ONE
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_LOGIC_ONE
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_N_123_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_2_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_N_123_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORF
    );
  Ucore_Ufunc_N_123_i_384 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_123_i
    );
  Ucore_Ufunc_N_124_i_385 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(6),
      ADR3 => VCC,
      O => Ucore_Ufunc_N_124_i
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_3_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_3_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_LOGIC_ONE,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_2_O,
      SEL => Ucore_Ufunc_N_124_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_2_O,
      I1 => Ucore_Ufunc_N_124_i,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYINIT_386 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_1_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_2_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_LOGIC_ZERO_387 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_4_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_FROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_GROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_5_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_5_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_4_O,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_4_O,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYINIT_388 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_3_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_4_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_LOGIC_ZERO_389 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_6_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_FROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(10),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_GROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_7_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_7_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_6_O,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_6_O,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYINIT_390 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_5_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_6_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_LOGIC_ZERO_391 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_8 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_8_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_FROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_GROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_9_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_9_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_9 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_8_O,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_9 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_8_O,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYINIT_392 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_7_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_8_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_LOGIC_ZERO_393 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_10 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_10_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_FROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_GROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_11_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_11_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_11 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_10_O,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_11 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_10_O,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYINIT_394 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_9_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_10_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_LOGIC_ZERO_395 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_12 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_12_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(15),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_FROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_addr_offset(16),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_GROM
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYMUXG,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_13_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_13_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_13 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_cry_12_O,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYMUXG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_13 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_12_O,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_GROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYINIT_396 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_11_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_12_n_CYINIT
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14_n_LOGIC_ZERO_397 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nextaddr_offset_cry_14 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_cry_14_O
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_FROM,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORF
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14_n_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(17),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_FROM
    );
  Ucore_Ufunc_BEL_39 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_addr_offset(18),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_SIG_39
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORF,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORG,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_15_n
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_15 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nextaddr_offset_cry_14_O,
      I1 => Ucore_Ufunc_SIG_39,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_XORG
    );
  Ucore_Ufunc_un4_nextaddr_offset_s_14_n_CYINIT_398 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nextaddr_offset_cry_13_O,
      O => Ucore_Ufunc_un4_nextaddr_offset_s_14_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ONE_399 : X_ONE
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ONE
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ZERO_400 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_0 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_0_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_1_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_1_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_1 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_0_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_0_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYINIT_401 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_LOGIC_ONE,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_LOGIC_ZERO_402 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_2 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_2_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_3_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_3_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_3 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_2_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_3 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_2_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYINIT_403 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_1_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_LOGIC_ZERO_404 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_4 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_4_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(11),
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_cur_oldCol(12),
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_5_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_5_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_5 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_4_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_5 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_4_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYINIT_405 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_3_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_LOGIC_ZERO_406 : X_ZERO
    port map (
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_LOGIC_ZERO
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_6 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYINIT,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_6_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYINIT,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_FROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORF
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_FROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(14),
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_GROM
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYMUXG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_7_O
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORG,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_7_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_cry_7 : X_MUX2
    port map (
      IA => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_LOGIC_ZERO,
      IB => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_6_O,
      SEL => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYMUXG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_7 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_6_O,
      I1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_GROM,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_XORG
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYINIT_407 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_5_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n_CYINIT
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_8 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_CYINIT,
      I1 => Ucore_Ufunc_s_cur_oldCol_15_rt,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_XORF
    );
  Ucore_Ufunc_s_cur_oldCol_15_rt_408 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_s_cur_oldCol(15),
      O => Ucore_Ufunc_s_cur_oldCol_15_rt
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_XORF,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n
    );
  Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_CYINIT_409 : X_BUF
    port map (
      I => Ucore_Ufunc_un4_nexts_cur_oldCol_cry_7_O,
      O => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n_CYINIT
    );
  Ucore_Ufunc_i_0_LOGIC_ZERO_410 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_0_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_0_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_0_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(0),
      O => Ucore_Ufunc_i_cry_0_O
    );
  Ucore_Ufunc_i_s_0_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_0_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(0),
      O => Ucore_Ufunc_i_s(0)
    );
  Ucore_Ufunc_i_qxu_0_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(0),
      O => Ucore_Ufunc_i_qxu(0)
    );
  Ucore_Ufunc_i_qxu_1_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(1),
      O => Ucore_Ufunc_i_qxu(1)
    );
  Ucore_Ufunc_i_0_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_0_CYMUXG,
      O => Ucore_Ufunc_i_cry_1_O
    );
  Ucore_Ufunc_i_cry_1_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_0_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_0_O,
      SEL => Ucore_Ufunc_i_qxu(1),
      O => Ucore_Ufunc_i_0_CYMUXG
    );
  Ucore_Ufunc_i_s_1_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_0_O,
      I1 => Ucore_Ufunc_i_qxu(1),
      O => Ucore_Ufunc_i_s(1)
    );
  Ucore_Ufunc_i_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_0_CYINIT_411 : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state_2_rep1,
      O => Ucore_Ufunc_i_0_CYINIT
    );
  Ucore_Ufunc_i_2_LOGIC_ZERO_412 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_2_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_2_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_2_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(2),
      O => Ucore_Ufunc_i_cry_2_O
    );
  Ucore_Ufunc_i_s_2_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_2_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(2),
      O => Ucore_Ufunc_i_s(2)
    );
  Ucore_Ufunc_i_qxu_2_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => Ucore_Ufunc_i(2),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(2)
    );
  Ucore_Ufunc_i_qxu_3_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state_2_rep1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(3),
      O => Ucore_Ufunc_i_qxu(3)
    );
  Ucore_Ufunc_i_2_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_2_CYMUXG,
      O => Ucore_Ufunc_i_cry_3_O
    );
  Ucore_Ufunc_i_cry_3_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_2_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_2_O,
      SEL => Ucore_Ufunc_i_qxu(3),
      O => Ucore_Ufunc_i_2_CYMUXG
    );
  Ucore_Ufunc_i_s_3_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_2_O,
      I1 => Ucore_Ufunc_i_qxu(3),
      O => Ucore_Ufunc_i_s(3)
    );
  Ucore_Ufunc_i_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_2_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_2_CYINIT_413 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_1_O,
      O => Ucore_Ufunc_i_2_CYINIT
    );
  Ucore_Ufunc_i_4_LOGIC_ZERO_414 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_4_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_4_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_4_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(4),
      O => Ucore_Ufunc_i_cry_4_O
    );
  Ucore_Ufunc_i_s_4_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_4_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(4),
      O => Ucore_Ufunc_i_s(4)
    );
  Ucore_Ufunc_i_qxu_4_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(4),
      ADR3 => Ucore_Ufunc_resize_state_2_rep1,
      O => Ucore_Ufunc_i_qxu(4)
    );
  Ucore_Ufunc_i_qxu_5_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(5),
      O => Ucore_Ufunc_i_qxu(5)
    );
  Ucore_Ufunc_i_4_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_4_CYMUXG,
      O => Ucore_Ufunc_i_cry_5_O
    );
  Ucore_Ufunc_i_cry_5_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_4_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_4_O,
      SEL => Ucore_Ufunc_i_qxu(5),
      O => Ucore_Ufunc_i_4_CYMUXG
    );
  Ucore_Ufunc_i_s_5_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_4_O,
      I1 => Ucore_Ufunc_i_qxu(5),
      O => Ucore_Ufunc_i_s(5)
    );
  Ucore_Ufunc_i_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_4_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_4_CYINIT_415 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_3_O,
      O => Ucore_Ufunc_i_4_CYINIT
    );
  Ucore_Ufunc_i_6_LOGIC_ZERO_416 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_6_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_6_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_6_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(6),
      O => Ucore_Ufunc_i_cry_6_O
    );
  Ucore_Ufunc_i_s_6_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_6_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(6),
      O => Ucore_Ufunc_i_s(6)
    );
  Ucore_Ufunc_i_qxu_6_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => Ucore_Ufunc_i(6),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(6)
    );
  Ucore_Ufunc_i_qxu_7_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(7),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(7)
    );
  Ucore_Ufunc_i_6_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_6_CYMUXG,
      O => Ucore_Ufunc_i_cry_7_O
    );
  Ucore_Ufunc_i_cry_7_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_6_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_6_O,
      SEL => Ucore_Ufunc_i_qxu(7),
      O => Ucore_Ufunc_i_6_CYMUXG
    );
  Ucore_Ufunc_i_s_7_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_6_O,
      I1 => Ucore_Ufunc_i_qxu(7),
      O => Ucore_Ufunc_i_s(7)
    );
  Ucore_Ufunc_i_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_6_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_6_CYINIT_417 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_5_O,
      O => Ucore_Ufunc_i_6_CYINIT
    );
  Ucore_Ufunc_i_8_LOGIC_ZERO_418 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_8_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_8_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_8_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_8_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(8),
      O => Ucore_Ufunc_i_cry_8_O
    );
  Ucore_Ufunc_i_s_8_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_8_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(8),
      O => Ucore_Ufunc_i_s(8)
    );
  Ucore_Ufunc_i_qxu_8_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(8),
      ADR3 => Ucore_Ufunc_resize_state(2),
      O => Ucore_Ufunc_i_qxu(8)
    );
  Ucore_Ufunc_i_qxu_9_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(9),
      ADR3 => Ucore_Ufunc_resize_state(2),
      O => Ucore_Ufunc_i_qxu(9)
    );
  Ucore_Ufunc_i_8_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_8_CYMUXG,
      O => Ucore_Ufunc_i_cry_9_O
    );
  Ucore_Ufunc_i_cry_9_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_8_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_8_O,
      SEL => Ucore_Ufunc_i_qxu(9),
      O => Ucore_Ufunc_i_8_CYMUXG
    );
  Ucore_Ufunc_i_s_9_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_8_O,
      I1 => Ucore_Ufunc_i_qxu(9),
      O => Ucore_Ufunc_i_s(9)
    );
  Ucore_Ufunc_i_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_8_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_8_CYINIT_419 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_7_O,
      O => Ucore_Ufunc_i_8_CYINIT
    );
  Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GWEAND_420 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FWEAND_421 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU6_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU6_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU6_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N225_RAM32X1_GRAMS
    );
  Ucore_Ufunc_i_10_LOGIC_ZERO_422 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_10_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_10_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_10_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_10_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(10),
      O => Ucore_Ufunc_i_cry_10_O
    );
  Ucore_Ufunc_i_s_10_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_10_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(10),
      O => Ucore_Ufunc_i_s(10)
    );
  Ucore_Ufunc_i_qxu_10_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_i(10),
      ADR2 => Ucore_Ufunc_resize_state(2),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(10)
    );
  Ucore_Ufunc_i_qxu_11_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(2),
      ADR3 => Ucore_Ufunc_i(11),
      O => Ucore_Ufunc_i_qxu(11)
    );
  Ucore_Ufunc_i_10_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_10_CYMUXG,
      O => Ucore_Ufunc_i_cry_11_O
    );
  Ucore_Ufunc_i_cry_11_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_10_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_10_O,
      SEL => Ucore_Ufunc_i_qxu(11),
      O => Ucore_Ufunc_i_10_CYMUXG
    );
  Ucore_Ufunc_i_s_11_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_10_O,
      I1 => Ucore_Ufunc_i_qxu(11),
      O => Ucore_Ufunc_i_s(11)
    );
  Ucore_Ufunc_i_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_10_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_10_CYINIT_423 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_9_O,
      O => Ucore_Ufunc_i_10_CYINIT
    );
  Ucore_Ufunc_i_12_LOGIC_ZERO_424 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_12_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_12_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_12_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_12_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(12),
      O => Ucore_Ufunc_i_cry_12_O
    );
  Ucore_Ufunc_i_s_12_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_12_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(12),
      O => Ucore_Ufunc_i_s(12)
    );
  Ucore_Ufunc_i_qxu_12_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(12),
      O => Ucore_Ufunc_i_qxu(12)
    );
  Ucore_Ufunc_i_qxu_13_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(13),
      ADR3 => Ucore_Ufunc_resize_state(2),
      O => Ucore_Ufunc_i_qxu(13)
    );
  Ucore_Ufunc_i_12_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_12_CYMUXG,
      O => Ucore_Ufunc_i_cry_13_O
    );
  Ucore_Ufunc_i_cry_13_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_12_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_12_O,
      SEL => Ucore_Ufunc_i_qxu(13),
      O => Ucore_Ufunc_i_12_CYMUXG
    );
  Ucore_Ufunc_i_s_13_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_12_O,
      I1 => Ucore_Ufunc_i_qxu(13),
      O => Ucore_Ufunc_i_s(13)
    );
  Ucore_Ufunc_i_12_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_12_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_12_CYINIT_425 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_11_O,
      O => Ucore_Ufunc_i_12_CYINIT
    );
  Ucore_Ufunc_i_14_LOGIC_ZERO_426 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_14_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_14_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_14_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_14_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(14),
      O => Ucore_Ufunc_i_cry_14_O
    );
  Ucore_Ufunc_i_s_14_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_14_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(14),
      O => Ucore_Ufunc_i_s(14)
    );
  Ucore_Ufunc_i_qxu_14_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_i(14),
      O => Ucore_Ufunc_i_qxu(14)
    );
  Ucore_Ufunc_i_qxu_15_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(15),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(15)
    );
  Ucore_Ufunc_i_14_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_14_CYMUXG,
      O => Ucore_Ufunc_i_cry_15_O
    );
  Ucore_Ufunc_i_cry_15_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_14_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_14_O,
      SEL => Ucore_Ufunc_i_qxu(15),
      O => Ucore_Ufunc_i_14_CYMUXG
    );
  Ucore_Ufunc_i_s_15_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_14_O,
      I1 => Ucore_Ufunc_i_qxu(15),
      O => Ucore_Ufunc_i_s(15)
    );
  Ucore_Ufunc_i_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_14_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_14_CYINIT_427 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_13_O,
      O => Ucore_Ufunc_i_14_CYINIT
    );
  Ucore_Ufunc_i_16_LOGIC_ZERO_428 : X_ZERO
    port map (
      O => Ucore_Ufunc_i_16_LOGIC_ZERO
    );
  Ucore_Ufunc_i_cry_16_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_16_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_16_CYINIT,
      SEL => Ucore_Ufunc_i_qxu(16),
      O => Ucore_Ufunc_i_cry_16_O
    );
  Ucore_Ufunc_i_s_16_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_16_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(16),
      O => Ucore_Ufunc_i_s(16)
    );
  Ucore_Ufunc_i_qxu_16_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => Ucore_Ufunc_i(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(16)
    );
  Ucore_Ufunc_i_qxu_17_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_i(17),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(17)
    );
  Ucore_Ufunc_i_16_COUTUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_16_CYMUXG,
      O => Ucore_Ufunc_i_cry_17_O
    );
  Ucore_Ufunc_i_cry_17_Q : X_MUX2
    port map (
      IA => Ucore_Ufunc_i_16_LOGIC_ZERO,
      IB => Ucore_Ufunc_i_cry_16_O,
      SEL => Ucore_Ufunc_i_qxu(17),
      O => Ucore_Ufunc_i_16_CYMUXG
    );
  Ucore_Ufunc_i_s_17_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_cry_16_O,
      I1 => Ucore_Ufunc_i_qxu(17),
      O => Ucore_Ufunc_i_s(17)
    );
  Ucore_Ufunc_i_16_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_16_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_16_CYINIT_429 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_15_O,
      O => Ucore_Ufunc_i_16_CYINIT
    );
  Ucore_Ufunc_i_s_18_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_i_18_CYINIT,
      I1 => Ucore_Ufunc_i_qxu(18),
      O => Ucore_Ufunc_i_s(18)
    );
  Ucore_Ufunc_i_qxu_0_18_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => Ucore_Ufunc_i(18),
      ADR3 => VCC,
      O => Ucore_Ufunc_i_qxu(18)
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_0_3_Q : X_LUT4
    generic map(
      INIT => X"9900"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_i_18_GROM
    );
  Ucore_Ufunc_i_18_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_i_18_GROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0(3)
    );
  Ucore_Ufunc_i_18_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_i_18_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_i_18_CYINIT_430 : X_BUF
    port map (
      I => Ucore_Ufunc_i_cry_17_O,
      O => Ucore_Ufunc_i_18_CYINIT
    );
  g0_0_a3_13 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(0),
      ADR1 => Ucore_Ufunc_state(2),
      ADR2 => Ucore_Ufunc_ram_writeAddr(10),
      ADR3 => Ucore_Ufunc_ram_writeAddr(7),
      O => g0_0_a3_13_O_FROM
    );
  g0_0_a3_16_431 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(17),
      ADR1 => Ucore_Ufunc_state(1),
      ADR2 => g0_0_a3_13_O,
      ADR3 => Ucore_Ufunc_doneflag,
      O => g0_0_a3_13_O_GROM
    );
  g0_0_a3_13_O_XUSED : X_BUF
    port map (
      I => g0_0_a3_13_O_FROM,
      O => g0_0_a3_13_O
    );
  g0_0_a3_13_O_YUSED : X_BUF
    port map (
      I => g0_0_a3_13_O_GROM,
      O => g0_0_a3_16
    );
  Ucore_Ufunc_addr_offset_5_0_1_10_Q : X_LUT4
    generic map(
      INIT => X"0600"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextaddr_offset_s_7_n,
      ADR1 => Ucore_Ufunc_un14_nextaddr_offset_s_7_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_10_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_10_Q : X_LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextaddr_offset_s_7_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_10_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_10_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_10_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_10_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_10_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_10_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_10_O_GROM,
      O => Ucore_Ufunc_N_45
    );
  Ucore_Ufunc_un1_next_write_data42_4_0 : X_LUT4
    generic map(
      INIT => X"C00C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_state(0),
      ADR2 => Ucore_Ufunc_state(2),
      ADR3 => Ucore_Ufunc_state(1),
      O => Ucore_Ufunc_un1_next_write_data42_4_0_O_FROM
    );
  Ucore_Ufunc_un1_next_write_data42_4_1_432 : X_LUT4
    generic map(
      INIT => X"00AB"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_canRead,
      ADR1 => Ucore_Ufunc_next_write_data38,
      ADR2 => Ucore_Ufunc_next_write_data40,
      ADR3 => Ucore_Ufunc_un1_next_write_data42_4_0_O,
      O => Ucore_Ufunc_un1_next_write_data42_4_0_O_GROM
    );
  Ucore_Ufunc_un1_next_write_data42_4_0_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_next_write_data42_4_0_O_FROM,
      O => Ucore_Ufunc_un1_next_write_data42_4_0_O
    );
  Ucore_Ufunc_un1_next_write_data42_4_0_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_next_write_data42_4_0_O_GROM,
      O => Ucore_Ufunc_un1_next_write_data42_4_1
    );
  Ucore_Ufunc_addr_offset_5_0_1_11_Q : X_LUT4
    generic map(
      INIT => X"0060"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_8_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_8_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_11_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_11_Q : X_LUT4
    generic map(
      INIT => X"78F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_8_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_11_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_11_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_11_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_11_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_11_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_11_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_11_O_GROM,
      O => Ucore_Ufunc_N_46
    );
  Ucore_Ufunc_addr_offset_5_0_1_12_Q : X_LUT4
    generic map(
      INIT => X"0048"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_9_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_9_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_12_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_12_Q : X_LUT4
    generic map(
      INIT => X"7F80"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_addr_offset_5_0_1_12_O,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_9_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_12_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_12_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_12_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_12_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_12_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_12_O_GROM,
      O => Ucore_Ufunc_N_47
    );
  Ucore_Ufunc_addr_offset_5_0_1_13_Q : X_LUT4
    generic map(
      INIT => X"1400"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_10_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_10_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_13_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_13_Q : X_LUT4
    generic map(
      INIT => X"7F80"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset_5_0_1_13_O,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_10_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_13_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_13_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_13_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_13_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_13_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_13_O_GROM,
      O => Ucore_Ufunc_N_48
    );
  Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GWEAND_433 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FWEAND_434 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU30_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU30_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU30_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N474_RAM32X1_GRAMS
    );
  Ucore_Ufunc_addr_offset_5_0_1_14_Q : X_LUT4
    generic map(
      INIT => X"1200"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_11_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_11_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_14_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_14_Q : X_LUT4
    generic map(
      INIT => X"78F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_11_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_14_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_14_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_14_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_14_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_14_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_14_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_14_O_GROM,
      O => Ucore_Ufunc_N_49
    );
  Ucore_Ufunc_addr_offset_5_0_1_15_Q : X_LUT4
    generic map(
      INIT => X"1400"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_12_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_12_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_15_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_15_Q : X_LUT4
    generic map(
      INIT => X"7F80"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset_5_0_1_15_O,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_12_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_15_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_15_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_15_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_15_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_15_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_15_O_GROM,
      O => Ucore_Ufunc_N_50
    );
  Ucore_Ufunc_addr_offset_5_0_1_16_Q : X_LUT4
    generic map(
      INIT => X"1020"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_13_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_13_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_16_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_16_Q : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_13_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_16_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_16_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_16_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_16_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_16_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_16_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_16_O_GROM,
      O => Ucore_Ufunc_N_51_0
    );
  Ucore_Ufunc_addr_offset_5_0_1_17_Q : X_LUT4
    generic map(
      INIT => X"1400"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_14_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_14_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_17_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_17_Q : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_14_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_17_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_17_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_17_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_17_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_17_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_17_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_17_O_GROM,
      O => Ucore_Ufunc_N_52
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_18_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_15_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_15_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_GROM
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_FROM,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_O_GROM,
      O => Ucore_Ufunc_N_53
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_Q : X_LUT4
    generic map(
      INIT => X"8802"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded_rep1,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_resize_state_2_rep1,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_1_21_1_435 : X_LUT4
    generic map(
      INIT => X"003D"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_resize_state_2_rep1,
      ADR3 => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O,
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_GROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_FROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_1_O_GROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_1_21_1
    );
  g0_1_L3 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_1_11,
      ADR1 => Ucore_Ufunc_un1_temp2_1_10,
      ADR2 => N_125,
      ADR3 => Ucore_Ufunc_un1_temp2_1_9,
      O => g0_1_L3_O_FROM
    );
  g0_1_1_436 : X_LUT4
    generic map(
      INIT => X"00D0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_2_8_0,
      ADR1 => g0_1_L5_n,
      ADR2 => g0_1_L3_O,
      ADR3 => Ucore_Ufunc_imageloaded_fast,
      O => g0_1_L3_O_GROM
    );
  g0_1_L3_O_XUSED : X_BUF
    port map (
      I => g0_1_L3_O_FROM,
      O => g0_1_L3_O
    );
  g0_1_L3_O_YUSED : X_BUF
    port map (
      I => g0_1_L3_O_GROM,
      O => g0_1_1
    );
  g0_3_a2_13 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(17),
      ADR1 => Ucore_Ufunc_ram_writeAddr(18),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeAddr(16),
      O => g0_3_a2_13_O_FROM
    );
  g0_0_7_437 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(1),
      ADR1 => Ucore_Ufunc_state(0),
      ADR2 => Ucore_Ufunc_ram_writeAddr(15),
      ADR3 => g0_3_a2_13_O,
      O => g0_3_a2_13_O_GROM
    );
  g0_3_a2_13_O_XUSED : X_BUF
    port map (
      I => g0_3_a2_13_O_FROM,
      O => g0_3_a2_13_O
    );
  g0_3_a2_13_O_YUSED : X_BUF
    port map (
      I => g0_3_a2_13_O_GROM,
      O => g0_0_7
    );
  g0_2_8 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(6),
      ADR1 => Ucore_Ufunc_temp2(14),
      ADR2 => Ucore_Ufunc_temp2(7),
      ADR3 => Ucore_Ufunc_temp2(15),
      O => g0_2_8_O_FROM
    );
  g0_2 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => g0_2_5,
      ADR1 => g0_2_8_O,
      ADR2 => g0_2_4,
      ADR3 => g0_3_5_0,
      O => g0_2_8_O_GROM
    );
  g0_2_8_O_XUSED : X_BUF
    port map (
      I => g0_2_8_O_FROM,
      O => g0_2_8_O
    );
  g0_2_8_O_YUSED : X_BUF
    port map (
      I => g0_2_8_O_GROM,
      O => Ucore_Ufunc_un1_temp2_3
    );
  Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_Q : X_LUT4
    generic map(
      INIT => X"AA05"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state_2_rep1,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_i_a2_0_0_Q : X_LUT4
    generic map(
      INIT => X"0300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_imageloaded_rep1,
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O,
      O => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_GROM
    );
  Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_FROM,
      O => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O
    );
  Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_i_m2_0_0_O_GROM,
      O => Ucore_Ufunc_N_483
    );
  Ucore_Ufunc_sram_doWrite_u_L1 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_resize_state_fast_0_Q,
      ADR3 => Ucore_Ufunc_resize_state_fast_2_Q,
      O => Ucore_Ufunc_presstate_3_FROM
    );
  Ucore_Ufunc_sram_doWrite_u : X_LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_canRead,
      ADR1 => Ucore_Ufunc_imageloaded_fast,
      ADR2 => Ucore_Ufunc_next_write_data38,
      ADR3 => Ucore_Ufunc_sram_doWrite_u_L1_O,
      O => Ucore_Ufunc_presstate_3_GROM
    );
  Ucore_Ufunc_presstate_3_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_presstate_3_FROM,
      O => Ucore_Ufunc_sram_doWrite_u_L1_O
    );
  Ucore_Ufunc_presstate_3_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_presstate_3_GROM,
      O => Ucore_Ufunc_sram_doWrite
    );
  Ucore_Ufunc_presstate_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_presstate_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_nextresize_state_enl_0_1_21 : X_LUT4
    generic map(
      INIT => X"EEEF"
    )
    port map (
      ADR0 => Ucore_Ufunc_nextresize_state_enl_0_1_18_n,
      ADR1 => Ucore_Ufunc_resize_doWrite,
      ADR2 => Ucore_Ufunc_nextresize_state_ss0_O,
      ADR3 => Ucore_Ufunc_nextresize_state_enl_0_1_21_1,
      O => Ucore_Ufunc_resize_state_1_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_1_Q : X_LUT4
    generic map(
      INIT => X"FF82"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_nextresize_state_enl_0_1_21_O,
      O => Ucore_Ufunc_nextresize_state(1)
    );
  Ucore_Ufunc_resize_state_1_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state_1_FROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_1_21_O
    );
  Ucore_Ufunc_resize_state_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_resize_state_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_nextresize_state_m2_3_Q : X_LUT4
    generic map(
      INIT => X"0F02"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_doWrite34,
      ADR1 => Ucore_Ufunc_un37_nextresize_state,
      ADR2 => Ucore_Ufunc_nextresize_state_m2(0),
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_resize_state_3_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_3_Q : X_LUT4
    generic map(
      INIT => X"FECC"
    )
    port map (
      ADR0 => Ucore_Ufunc_nextresize_state_enl_0_a2_0(3),
      ADR1 => Ucore_Ufunc_nextresize_state_enl_0_0(3),
      ADR2 => Ucore_Ufunc_nextresize_state_enl_0_a2_0_0(3),
      ADR3 => Ucore_Ufunc_nextresize_state_m2_3_O,
      O => Ucore_Ufunc_nextresize_state(3)
    );
  Ucore_Ufunc_resize_state_3_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state_3_FROM,
      O => Ucore_Ufunc_nextresize_state_m2_3_O
    );
  Ucore_Ufunc_resize_state_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_resize_state_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un37_nextresize_statelto9_2 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextc_s_9_n,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_un4_nextc_s_6_n,
      ADR3 => Ucore_Ufunc_un4_nextc_s_5_n,
      O => Ucore_Ufunc_un37_nextresize_statelto9_2_O_FROM
    );
  Ucore_Ufunc_un37_nextresize_statelto9 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Ufunc_un37_nextresize_statelto9_2_O,
      ADR1 => Ucore_Ufunc_N_220,
      ADR2 => Ucore_Ufunc_un4_nextc_s_8_n,
      ADR3 => Ucore_Ufunc_un4_nextc_s_7_n,
      O => Ucore_Ufunc_un37_nextresize_statelto9_2_O_GROM
    );
  Ucore_Ufunc_un37_nextresize_statelto9_2_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un37_nextresize_statelto9_2_O_FROM,
      O => Ucore_Ufunc_un37_nextresize_statelto9_2_O
    );
  Ucore_Ufunc_un37_nextresize_statelto9_2_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un37_nextresize_statelto9_2_O_GROM,
      O => Ucore_Ufunc_un37_nextresize_state
    );
  Ucore_Ufunc_addr_offset_5_0_1_4_Q : X_LUT4
    generic map(
      INIT => X"1400"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_1_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_1_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_4_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_4_Q : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_1_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_4_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_4_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_4_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_4_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_4_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_4_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_4_O_GROM,
      O => Ucore_Ufunc_N_39
    );
  Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GWEAND_438 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FWEAND_439 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU22_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU22_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU22_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(2),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N391_RAM32X1_GRAMS
    );
  Ucore_Ufunc_addr_offset_5_0_1_5_Q : X_LUT4
    generic map(
      INIT => X"0060"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_2_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_2_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_5_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_5_Q : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset_5_0_1_5_O,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_2_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      O => Ucore_Ufunc_addr_offset_5_0_1_5_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_5_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_5_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_5_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_5_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_5_O_GROM,
      O => Ucore_Ufunc_N_40
    );
  Ucore_Ufunc_addr_offset_5_0_1_6_Q : X_LUT4
    generic map(
      INIT => X"0208"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR1 => Ucore_Ufunc_un14_nextaddr_offset_s_3_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_3_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_6_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_6_Q : X_LUT4
    generic map(
      INIT => X"78F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_addr_offset_5_0_1_6_O,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_3_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_6_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_6_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_6_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_6_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_6_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_6_O_GROM,
      O => Ucore_Ufunc_N_41
    );
  Ucore_Ufunc_addr_offset_5_0_1_7_Q : X_LUT4
    generic map(
      INIT => X"0060"
    )
    port map (
      ADR0 => Ucore_Ufunc_un14_nextaddr_offset_s_4_n,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_4_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_7_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_7_Q : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un4_nextaddr_offset_s_4_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR3 => Ucore_Ufunc_addr_offset_5_0_1_7_O,
      O => Ucore_Ufunc_addr_offset_5_0_1_7_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_7_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_7_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_7_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_7_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_7_O_GROM,
      O => Ucore_Ufunc_N_42
    );
  Ucore_Ufunc_addr_offset_5_0_1_8_Q : X_LUT4
    generic map(
      INIT => X"0440"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      ADR2 => Ucore_Ufunc_un14_nextaddr_offset_s_5_n,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_5_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_8_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_8_Q : X_LUT4
    generic map(
      INIT => X"7F80"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset_5_0_1_8_O,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR3 => Ucore_Ufunc_un4_nextaddr_offset_s_5_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_8_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_8_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_8_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_8_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_8_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_8_O_GROM,
      O => Ucore_Ufunc_N_43_0
    );
  Ucore_Ufunc_addr_offset_5_0_1_9_Q : X_LUT4
    generic map(
      INIT => X"1400"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un14_nextaddr_offset_s_6_n,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_6_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_9_O_FROM
    );
  Ucore_Ufunc_addr_offset_5_0_9_Q : X_LUT4
    generic map(
      INIT => X"78F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_addr_offset_5_0_1_9_O,
      ADR2 => Ucore_Ufunc_un4_nextaddr_offset_s_6_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      O => Ucore_Ufunc_addr_offset_5_0_1_9_O_GROM
    );
  Ucore_Ufunc_addr_offset_5_0_1_9_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_9_O_FROM,
      O => Ucore_Ufunc_addr_offset_5_0_1_9_O
    );
  Ucore_Ufunc_addr_offset_5_0_1_9_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_5_0_1_9_O_GROM,
      O => Ucore_Ufunc_N_44
    );
  Ucore_Ufunc_next_write_data26_x : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => I_10_n_0,
      ADR1 => I_10_n,
      ADR2 => VCC,
      ADR3 => I_10_n_1,
      O => Ucore_Ufunc_next_write_data26_x_O_FROM
    );
  Ucore_Ufunc_un1_next_write_data26_2 : X_LUT4
    generic map(
      INIT => X"4C00"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_3,
      ADR1 => Ucore_Ufunc_next_write_data26_x_O,
      ADR2 => Ucore_Ufunc_N_243,
      ADR3 => Ucore_Ufunc_next_state36,
      O => Ucore_Ufunc_next_write_data26_x_O_GROM
    );
  Ucore_Ufunc_next_write_data26_x_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data26_x_O_FROM,
      O => Ucore_Ufunc_next_write_data26_x_O
    );
  Ucore_Ufunc_next_write_data26_x_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data26_x_O_GROM,
      O => Ucore_Ufunc_un1_next_write_data26_2_O
    );
  Ucore_Ufunc_next_write_data26 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_next_state36,
      ADR1 => I_10_n_1,
      ADR2 => I_10_n,
      ADR3 => I_10_n_0,
      O => Ucore_Ufunc_next_write_data26_O_FROM
    );
  Ucore_Ufunc_un1_next_write_data37_5 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_3,
      ADR1 => Ucore_Ufunc_next_write_data26_O,
      ADR2 => Ucore_Ufunc_next_write_data37,
      ADR3 => Ucore_Ufunc_N_243,
      O => Ucore_Ufunc_next_write_data26_O_GROM
    );
  Ucore_Ufunc_next_write_data26_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data26_O_FROM,
      O => Ucore_Ufunc_next_write_data26_O
    );
  Ucore_Ufunc_next_write_data26_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data26_O_GROM,
      O => Ucore_Ufunc_un1_next_write_data37_5_n
    );
  Ucore_Ufunc_nextresize_state_enl_i_1_1_0_Q : X_LUT4
    generic map(
      INIT => X"2224"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state_2_rep1,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_presstate_1_Q,
      ADR3 => Ucore_Ufunc_presstate_3_Q,
      O => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_i_1_0_Q : X_LUT4
    generic map(
      INIT => X"1488"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O,
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_GROM
    );
  Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_FROM,
      O => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O
    );
  Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_i_1_1_0_O_GROM,
      O => Ucore_Ufunc_nextresize_state_enl_i_1(0)
    );
  Ucore_Ufunc_sram_writeData_13_Q : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeData(13),
      ADR1 => Ucore_Ufunc_resize_write_data(13),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(13)
    );
  Ucore_Ufunc_sram_writeData_12_Q : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_write_data(12),
      ADR1 => Ucore_Ufunc_ram_writeData(12),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(12)
    );
  Ucore_Ufunc_sram_writedatareg_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_8_Q : X_LUT4
    generic map(
      INIT => X"E020"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_43_0,
      ADR1 => Ucore_Ufunc_N_501,
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_N_60,
      O => Ucore_Ufunc_addr_offset_5(8)
    );
  Ucore_Ufunc_addr_offset_5_7_Q : X_LUT4
    generic map(
      INIT => X"A0C0"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_59_0,
      ADR1 => Ucore_Ufunc_N_42,
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_N_501,
      O => Ucore_Ufunc_addr_offset_5(7)
    );
  Ucore_Ufunc_addr_offset_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_8_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_15_Q : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => Ucore_Ufunc_resize_write_data(15),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_ram_writeData(15),
      O => Ucore_Ufunc_sram_writeData(15)
    );
  Ucore_Ufunc_sram_writeData_14_Q : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => Ucore_Ufunc_resize_write_data(14),
      ADR2 => Ucore_Ufunc_ram_writeData(14),
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_writeData(14)
    );
  Ucore_Ufunc_sram_writedatareg_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_10_Q : X_LUT4
    generic map(
      INIT => X"8C80"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_62,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_N_45,
      O => Ucore_Ufunc_addr_offset_5(10)
    );
  Ucore_Ufunc_addr_offset_5_9_Q : X_LUT4
    generic map(
      INIT => X"8C80"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_61,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_N_44,
      O => Ucore_Ufunc_addr_offset_5(9)
    );
  Ucore_Ufunc_addr_offset_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_10_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2941 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N10
    );
  Ucore_Uusb_C2944 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N5
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N15,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(2)
    );
  Ucore_Uusb_C2939 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(3),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N20
    );
  Ucore_Uusb_C2940 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N15
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N25,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(4)
    );
  Ucore_Uusb_C2937 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N30
    );
  Ucore_Uusb_C2938 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(4),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N25
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_resize_state_0_rep1_440 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_resize_state_0_GROM,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state_0_rep1
    );
  Ucore_Ufunc_N_395_i_441 : X_LUT4
    generic map(
      INIT => X"0301"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_438,
      ADR1 => Ucore_Ufunc_N_483,
      ADR2 => Ucore_Ufunc_nextresize_state_enl_i_1(0),
      ADR3 => Ucore_Ufunc_nextresize_state_m2(0),
      O => Ucore_Ufunc_resize_state_0_GROM
    );
  Ucore_Ufunc_resize_state_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state_0_GROM,
      O => Ucore_Ufunc_N_395_i
    );
  Ucore_Ufunc_resize_state_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_resize_state_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N35,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_7_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(6)
    );
  Ucore_Uusb_C2935 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(7),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N40
    );
  Ucore_Uusb_C2936 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(6),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N35
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_9_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_9_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_BUS1153_9_GROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_9_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(8)
    );
  Ucore_Uusb_C2952 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      O => Ucore_Uusb_Uusb_Usie_BUS1153_9_FROM
    );
  Ucore_Uusb_C2955 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      O => Ucore_Uusb_Uusb_Usie_BUS1153_9_GROM
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_9_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_BUS1153_9_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N10
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_9_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_BUS1153_9_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N5
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_utxoe_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_BYMUXNOT,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFY_RST,
      O => Ucore_utxoe
    );
  Ucore_Uusb_C2786 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N137
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N137,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_BYMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_BUFO8_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N19,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_1_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(1)
    );
  Ucore_Uusb_C3288 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_BUFO8_1_FROM
    );
  Ucore_Uusb_C3289 : X_LUT4
    generic map(
      INIT => X"ACA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(1),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_DBUS(1),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N19
    );
  Ucore_Uusb_Uuc_BUFO8_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_1_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C2_N12
    );
  Ucore_Uusb_C3278 : X_LUT4
    generic map(
      INIT => X"EA40"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7015,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_Uuc_DBUS(3),
      ADR3 => Ucore_Uusb_Uuc_ABUS(3),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N35
    );
  Ucore_Uusb_C3274 : X_LUT4
    generic map(
      INIT => X"F808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR1 => Ucore_Uusb_Uuc_DBUS(2),
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_ABUS(2),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N27
    );
  Ucore_Uusb_C3284 : X_LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7015,
      ADR1 => Ucore_Uusb_Uuc_ABUS(5),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR3 => Ucore_Uusb_Uuc_DBUS(5),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N51
    );
  Ucore_Uusb_C3271 : X_LUT4
    generic map(
      INIT => X"EA40"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7015,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_Uuc_DBUS(4),
      ADR3 => Ucore_Uusb_Uuc_ABUS(4),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N43
    );
  Ucore_Uusb_C3282 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_BUFO8_7_FROM
    );
  Ucore_Uusb_C3280 : X_LUT4
    generic map(
      INIT => X"AAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(7),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_Uuc_DBUS(7),
      ADR3 => Ucore_Uusb_syn7015,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N67
    );
  Ucore_Uusb_Uuc_BUFO8_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_7_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C2_N35
    );
  Ucore_Uusb_C2889 : X_LUT4
    generic map(
      INIT => X"FF27"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR3 => Ucore_Uusb_syn6629,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FROM
    );
  Ucore_Uusb_C2887 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_N1552,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C10_N9
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FROM,
      O => Ucore_Uusb_N1552
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N6,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(0)
    );
  Ucore_Uusb_C2838 : X_LUT4
    generic map(
      INIT => X"40B0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2,
      ADR1 => Ucore_Uusb_syn24588,
      ADR2 => Ucore_Uusb_syn8070,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C3_N3
    );
  Ucore_Uusb_C2834 : X_LUT4
    generic map(
      INIT => X"10FF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(0),
      ADR2 => Ucore_Uusb_syn24588,
      ADR3 => Ucore_Uusb_syn8070,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2799 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_GROM,
      O => Ucore_Uusb_N1554
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_resize_state_2_rep1_442 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_resize_state_2_GROM,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state_2_rep1
    );
  Ucore_Ufunc_nextresize_state_enl_0_2_Q : X_LUT4
    generic map(
      INIT => X"FECC"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_429,
      ADR1 => Ucore_Ufunc_resize_doRead,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => Ucore_Ufunc_resize_state(2),
      O => Ucore_Ufunc_resize_state_2_GROM
    );
  Ucore_Ufunc_resize_state_2_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_state_2_GROM,
      O => Ucore_Ufunc_nextresize_state(2)
    );
  Ucore_Ufunc_resize_state_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_resize_state_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2801 : X_LUT4
    generic map(
      INIT => X"E120"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0,
      ADR1 => Ucore_urx0,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N12
    );
  Ucore_Uusb_C2797 : X_LUT4
    generic map(
      INIT => X"3303"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N20
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_BUFO8_10_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_10_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N88,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N26,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_10_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(10)
    );
  Ucore_Uusb_C3275 : X_LUT4
    generic map(
      INIT => X"EECC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(7),
      ADR1 => Ucore_Uusb_syn27599,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5306,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N88
    );
  Ucore_Uusb_C3285 : X_LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6524,
      ADR1 => Ucore_Uusb_syn6519,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_syn7015,
      O => Ucore_Uusb_Uuc_BUFO8_11_FROM
    );
  Ucore_Uusb_C3279 : X_LUT4
    generic map(
      INIT => X"E2C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(3),
      ADR1 => Ucore_Uusb_syn7015,
      ADR2 => Ucore_Uusb_Uuc_ABUS(11),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C755,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N95
    );
  Ucore_Uusb_Uuc_BUFO8_11_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_11_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C2_N26
    );
  Ucore_Uusb_C3283 : X_LUT4
    generic map(
      INIT => X"EC20"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR1 => Ucore_Uusb_syn7015,
      ADR2 => Ucore_Uusb_Uuc_DBUS(5),
      ADR3 => Ucore_Uusb_Uuc_ABUS(13),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N109
    );
  Ucore_Uusb_C3267 : X_LUT4
    generic map(
      INIT => X"E2C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR1 => Ucore_Uusb_syn7015,
      ADR2 => Ucore_Uusb_Uuc_ABUS(12),
      ADR3 => Ucore_Uusb_Uuc_DBUS(4),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N102
    );
  Ucore_Uusb_C3344 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6831,
      ADR1 => Ucore_Uusb_Uuc_ABUS(1),
      ADR2 => Ucore_Uusb_Uuc_DBUS(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C24_N6
    );
  Ucore_Uusb_C3347 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6831,
      ADR1 => Ucore_Uusb_Uuc_ABUS(0),
      ADR2 => Ucore_Uusb_Uuc_DBUS(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C26_N6
    );
  Ucore_Uusb_Uuc_DPTRO_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3281 : X_LUT4
    generic map(
      INIT => X"F808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(7),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_ABUS(15),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N123
    );
  Ucore_Uusb_C3273 : X_LUT4
    generic map(
      INIT => X"F808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(6),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_ABUS(14),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N116
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_7_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_0_n,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_s_cur_oldCol_5(7)
    );
  Ucore_Ufunc_N_503_i_443 : X_LUT4
    generic map(
      INIT => X"F0FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_s_cur_oldCol(6),
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_N_503_i
    );
  Ucore_Ufunc_s_cur_oldCol_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldCol_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2950 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(3),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FROM
    );
  Ucore_Uusb_C2951 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N20
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N15
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3337 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(3),
      ADR1 => Ucore_Uusb_Uuc_DBUS(3),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6831,
      O => Ucore_Uusb_Uuc_Udptr_C20_N6
    );
  Ucore_Uusb_C3352 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(2),
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_Uuc_DBUS(2),
      O => Ucore_Uusb_Uuc_Udptr_C22_N6
    );
  Ucore_Uusb_Uuc_DPTRO_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3422 : X_LUT4
    generic map(
      INIT => X"0404"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR1 => Ucore_Uusb_syn6653,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Uep0ctrl_in_en_FROM
    );
  Ucore_Uusb_C3388 : X_LUT4
    generic map(
      INIT => X"44CC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => Ucore_Uusb_BUS131(7),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6653,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C0_N5
    );
  Ucore_Uusb_Uusb_Uep0ctrl_in_en_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_in_en_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1471
    );
  Ucore_Uusb_Uusb_Uep0ctrl_in_en_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_in_en_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldCol_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(8),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(8)
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_9_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_2_n,
      O => Ucore_Ufunc_s_cur_oldCol_5(9)
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_8_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_1_n,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldCol_5(8)
    );
  Ucore_Ufunc_s_cur_oldCol_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldCol_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3025 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR3 => Ucore_Uusb_syn28150,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C29_N5
    );
  Ucore_Uusb_C2992 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR3 => Ucore_Uusb_syn28150,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C25_N5
    );
  Ucore_Uusb_Uusb_Usie_NET1039_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_NET1039_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GWEAND_444 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FWEAND_445 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU13_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU13_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU13_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N307_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uglue_bytecount_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uglue_bytecount_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uglue_bytecount_1_FFY_SET
    );
  Ucore_Uusb_Uglue_bytecount_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uglue_C1075_N6,
      CE => Ucore_Uusb_Uglue_C27_N9,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uglue_bytecount_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uglue_bytecount(0)
    );
  Ucore_Uusb_C3434 : X_LUT4
    generic map(
      INIT => X"3C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uglue_bytecount(1),
      ADR2 => Ucore_Uusb_Uglue_bytecount(0),
      ADR3 => Ucore_Uusb_IT(1),
      O => Ucore_Uusb_Uglue_C1075_N11
    );
  Ucore_Uusb_C3444 : X_LUT4
    generic map(
      INIT => X"3F3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uglue_bytecount(0),
      ADR2 => Ucore_Uusb_IT(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uglue_C1075_N6
    );
  Ucore_Uusb_Uglue_bytecount_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uglue_bytecount_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2947 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(5),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N30
    );
  Ucore_Uusb_C2948 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(4),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N25
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3341 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(5),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_Uuc_DBUS(5),
      O => Ucore_Uusb_Uuc_Udptr_C16_N6
    );
  Ucore_Uusb_C3349 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(4),
      ADR1 => Ucore_Uusb_syn6831,
      ADR2 => Ucore_Uusb_Uuc_DBUS(4),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C18_N6
    );
  Ucore_Uusb_Uuc_DPTRO_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3399 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uglue_N33,
      ADR3 => Ucore_Uusb_syn5544,
      O => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FROM
    );
  Ucore_Uusb_C3394 : X_LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6653,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2,
      ADR3 => Ucore_Uusb_NET136,
      O => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_GROM
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FROM,
      O => Ucore_Uusb_NET136
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_GROM,
      O => Ucore_Uusb_N1468
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2945 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(7),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N40
    );
  Ucore_Uusb_C2946 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(6),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N35
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3339 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_DBUS(7),
      ADR2 => Ucore_Uusb_Uuc_ABUS(7),
      ADR3 => Ucore_Uusb_syn6831,
      O => Ucore_Uusb_Uuc_Udptr_C12_N6
    );
  Ucore_Uusb_C3350 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(6),
      ADR1 => Ucore_Uusb_syn6831,
      ADR2 => Ucore_Uusb_Uuc_ABUS(6),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C14_N6
    );
  Ucore_Uusb_Uuc_DPTRO_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2830 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FROM
    );
  Ucore_Uusb_C2810 : X_LUT4
    generic map(
      INIT => X"E4EE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N62
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C328
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3243 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(1),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N10
    );
  Ucore_Uusb_C3245 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_NET2015,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N5
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_DPTRO_9_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_9_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C10_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_9_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(8)
    );
  Ucore_Uusb_C3346 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(9),
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_Uuc_DBUS(1),
      O => Ucore_Uusb_Uuc_Udptr_C8_N6
    );
  Ucore_Uusb_C3343 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ABUS(8),
      ADR3 => Ucore_Uusb_syn6831,
      O => Ucore_Uusb_Uuc_Udptr_C10_N6
    );
  Ucore_Uusb_Uuc_DPTRO_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GWEAND_446 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FWEAND_447 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU5_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU5_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU5_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N224_RAM32X1_GRAMS
    );
  Ucore_Uusb_C2815 : X_LUT4
    generic map(
      INIT => X"EFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C328,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FROM
    );
  Ucore_Uusb_C2813 : X_LUT4
    generic map(
      INIT => X"FFCF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn28560,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N28,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N80
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N28
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3241 : X_LUT4
    generic map(
      INIT => X"0A0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N20
    );
  Ucore_Uusb_C3242 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(2),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N15
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N25,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(4)
    );
  Ucore_Uusb_C3239 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_NET2015,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N30
    );
  Ucore_Uusb_C3240 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(4),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N25
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DSEL_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2603,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(2)
    );
  Ucore_Uusb_C3088 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1567
    );
  Ucore_Uusb_C3101 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2646,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR2 => Ucore_Uusb_syn7362,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2603
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DSEL_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2560,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(1)
    );
  Ucore_Uusb_C3102 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7532,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C654,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FROM
    );
  Ucore_Uusb_C3094 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      ADR2 => Ucore_Uusb_syn7362,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2646,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2560
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2646
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N35,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(6)
    );
  Ucore_Uusb_C3244 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_NET1039,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FROM
    );
  Ucore_Uusb_C3238 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(6),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N35
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_FROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3133 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C656,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C580,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2128
    );
  Ucore_Uusb_C3261 : X_LUT4
    generic map(
      INIT => X"0CC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_urx0,
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Urst_cnt(1),
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N9
    );
  Ucore_Uusb_C3263 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(0),
      ADR2 => Ucore_urx0,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N3
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_1_CEMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C0_N3,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_CEMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3132 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1006
    );
  Ucore_Uusb_C3089 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7460,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N963
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_OP_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N268,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(1)
    );
  Ucore_Uusb_C3121 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FROM
    );
  Ucore_Uusb_C3136 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR1 => Ucore_Uusb_syn7274,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N268
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_1_FROM,
      O => Ucore_Uusb_syn7285
    );
  Ucore_Uusb_C3257 : X_LUT4
    generic map(
      INIT => X"50A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7088,
      ADR1 => VCC,
      ADR2 => Ucore_urx0,
      ADR3 => Ucore_Uusb_Uusb_Usie_Urst_cnt(4),
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N24
    );
  Ucore_Uusb_C3260 : X_LUT4
    generic map(
      INIT => X"7800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Urst_cnt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(2),
      ADR3 => Ucore_urx0,
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N14
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_4_CEMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C0_N3,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_CEMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3147 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FROM
    );
  Ucore_Uusb_C3146 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C667,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C765,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1049,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1049
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N529
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DSEL_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1092,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(3)
    );
  Ucore_Uusb_C3086 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR3 => Ucore_Uusb_syn5344,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FROM
    );
  Ucore_Uusb_C3179 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1092
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_3_FROM,
      O => Ucore_Uusb_syn27968
    );
  Ucore_Uusb_C2904 : X_LUT4
    generic map(
      INIT => X"BFBF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N11
    );
  Ucore_Uusb_C2909 : X_LUT4
    generic map(
      INIT => X"BFBF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8063,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2
    );
  Ucore_Uusb_C3024 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FROM
    );
  Ucore_Uusb_C3021 : X_LUT4
    generic map(
      INIT => X"C101"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_NET230,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_NET230
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C30_N9
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2902 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(3),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N21
    );
  Ucore_Uusb_C2903 : X_LUT4
    generic map(
      INIT => X"7FBF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8063,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N16
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2900 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(5),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N31
    );
  Ucore_Uusb_C2901 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(4),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N26
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2898 : X_LUT4
    generic map(
      INIT => X"AFFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(7),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N41
    );
  Ucore_Uusb_C2899 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(6),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N36
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2896 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(9),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N51
    );
  Ucore_Uusb_C2897 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(8),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N46
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2798 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N84
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2808 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_N303
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DSEL_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N615,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(2)
    );
  Ucore_Uusb_C3116 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR1 => Ucore_Uusb_syn5326,
      ADR2 => Ucore_Uusb_syn5302,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C667,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FROM
    );
  Ucore_Uusb_C3115 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C780,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N133,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N615
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N133
    );
  Ucore_Uusb_C3445 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1024,
      ADR2 => Ucore_Uusb_Uusb_Usie_BUS1153(7),
      ADR3 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      O => Ucore_Uusb_Uglue_in_trac_FROM
    );
  Ucore_Uusb_C3435 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uglue_in_trac,
      ADR3 => Ucore_Uusb_IT(1),
      O => Ucore_Uusb_Uglue_in_trac_GROM
    );
  Ucore_Uusb_Uglue_in_trac_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_in_trac_FROM,
      O => Ucore_Uusb_IT(1)
    );
  Ucore_Uusb_Uglue_in_trac_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_in_trac_GROM,
      O => Ucore_Uusb_Uglue_n_1032
    );
  Ucore_Uusb_Uglue_in_trac_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uglue_in_trac_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3264 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7088,
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(4),
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(5),
      ADR3 => Ucore_urx0,
      O => Ucore_Uusb_Uusb_Usie_NET2015_GROM
    );
  Ucore_Uusb_Uusb_Usie_NET2015_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_NET2015_GROM,
      O => Ucore_Uusb_Uusb_Usie_Urst_C0_N3
    );
  Ucore_Uusb_Uusb_Usie_NET2015_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_NET2015_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3085 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27968,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn7341,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1523,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1784
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3117 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N53,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1394
    );
  Ucore_Uusb_C3192 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR2 => Ucore_Uusb_syn27986,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1913
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DWR_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1956,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(4)
    );
  Ucore_Uusb_C3074 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C556,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C654,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FROM
    );
  Ucore_Uusb_C3076 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1956
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_FROM,
      O => Ucore_Uusb_syn27992
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GWEAND_448 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FWEAND_449 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU21_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU21_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU21_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(1),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N390_RAM32X1_GRAMS
    );
  Ucore_Uusb_C3292 : X_LUT4
    generic map(
      INIT => X"CCC4"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6524,
      ADR1 => Ucore_Uusb_syn5306,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_Uuc_Ubuf_relf_FROM
    );
  Ucore_Uusb_C3266 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => sw1_p174_c,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C751,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_N29,
      O => Ucore_Uusb_Uuc_Ubuf_relf_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_relf_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_relf_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_N29
    );
  Ucore_Uusb_Uuc_Ubuf_relf_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_relf_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C0_N5
    );
  Ucore_Uusb_Uuc_Ubuf_relf_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Ubuf_relf_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DWR_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N442,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(2)
    );
  Ucore_Uusb_C3145 : X_LUT4
    generic map(
      INIT => X"FEF0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5327,
      ADR1 => Ucore_Uusb_syn5326,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N529,
      ADR3 => Ucore_Uusb_syn5302,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FROM
    );
  Ucore_Uusb_C3072 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N133,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N442
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N485
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_N1523,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C1_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen
    );
  Ucore_Uusb_C2926 : X_LUT4
    generic map(
      INIT => X"DD00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FROM
    );
  Ucore_Uusb_C2912 : X_LUT4
    generic map(
      INIT => X"0055"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_N1523
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_FROM,
      O => Ucore_Uusb_syn28312
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_state_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_state_0_FFY_RST
    );
  Ucore_Ufunc_state_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_28_i,
      CE => Ucore_Ufunc_un1_rst_7_i,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_state_0_FFY_RST,
      O => Ucore_Ufunc_state(0)
    );
  Ucore_Ufunc_N_28_i_450 : X_LUT4
    generic map(
      INIT => X"FAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_rst_4,
      ADR1 => VCC,
      ADR2 => sw1_p174_c,
      ADR3 => Ucore_Ufunc_next_write_data40,
      O => Ucore_Ufunc_N_28_i
    );
  Ucore_Uusb_C3001 : X_LUT4
    generic map(
      INIT => X"FEEE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7855,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C355,
      ADR2 => Ucore_Uusb_syn28154,
      ADR3 => Ucore_Uusb_syn5165,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N37
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3022 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FROM
    );
  Ucore_Uusb_C2995 : X_LUT4
    generic map(
      INIT => X"B380"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_S_62_cell0,
      ADR3 => Ucore_Uusb_syn7877,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N16
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C348
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2781 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C12_N5
    );
  Ucore_Uusb_C2837 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR3 => Ucore_Uusb_syn8079,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C2_N3
    );
  fse0_p17_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => fse0_p17_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2894 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(11),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N61
    );
  Ucore_Uusb_C2895 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(10),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N56
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2892 : X_LUT4
    generic map(
      INIT => X"BFBF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(13),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N71
    );
  Ucore_Uusb_C2893 : X_LUT4
    generic map(
      INIT => X"F7F7"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(12),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N66
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2905 : X_LUT4
    generic map(
      INIT => X"BFBF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FROM
    );
  Ucore_Uusb_C2891 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(14),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N76
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FROM,
      O => Ucore_Uusb_N1524
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3491 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q(1),
      O => Ucore_Uusb_Uuc_ALUOP_0_FROM
    );
  Ucore_Uusb_C3049 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      ADR2 => Ucore_Uusb_syn28047,
      ADR3 => Ucore_Uusb_syn28046,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N24
    );
  Ucore_Uusb_Uuc_ALUOP_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP_0_FROM,
      O => Ucore_Uusb_syn6493
    );
  Ucore_Uusb_C3196 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5302,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR2 => Ucore_Uusb_syn5327,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C765,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FROM
    );
  Ucore_Uusb_C3144 : X_LUT4
    generic map(
      INIT => X"FF0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2257,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2171
    );
  Ucore_Uusb_C3156 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_syn27841,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FROM
    );
  Ucore_Uusb_C3139 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C598,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C642,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2257,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2257
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_GROM,
      O => Ucore_Uusb_syn27876
    );
  Ucore_Uusb_C3122 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C598,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C705,
      ADR2 => Ucore_Uusb_syn7473,
      ADR3 => Ucore_Uusb_syn5249,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2689
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_1_LOGIC_ZERO_451 : X_ZERO
    port map (
      O => Ucore_Ufunc_addr_1_LOGIC_ZERO
    );
  Ucore_Ufunc_un1_nextaddr_s_1 : X_XOR2
    port map (
      I0 => Ucore_Ufunc_addr_1_LOGIC_ZERO,
      I1 => Ucore_Ufunc_s_cur_oldCol_6_rt,
      O => Ucore_Ufunc_un1_nextaddr_s_1_n
    );
  Ucore_Ufunc_s_cur_oldCol_6_rt_452 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_s_cur_oldCol(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldCol_6_rt
    );
  Ucore_Ufunc_addr_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3327 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5318,
      ADR1 => Ucore_Uusb_Uuc_DBUS(1),
      ADR2 => Ucore_Uusb_syn6904,
      ADR3 => Ucore_Uusb_Uuc_PO(1),
      O => Ucore_Uusb_Uuc_Upsw_C0_N42
    );
  Ucore_Uusb_C3329 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5318,
      ADR1 => Ucore_Uusb_Uuc_PO(0),
      ADR2 => Ucore_Uusb_syn6904,
      ADR3 => Ucore_Uusb_Uuc_DBUS(0),
      O => Ucore_Uusb_Uuc_Upsw_C0_N48
    );
  Ucore_Uusb_Uuc_PO_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3316 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(4),
      ADR1 => Ucore_Uusb_syn6904,
      ADR2 => Ucore_Uusb_Uuc_PO(4),
      ADR3 => Ucore_Uusb_syn5318,
      O => Ucore_Uusb_Uuc_Upsw_C0_N24
    );
  Ucore_Uusb_C3317 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6904,
      ADR1 => Ucore_Uusb_Uuc_DBUS(3),
      ADR2 => Ucore_Uusb_Uuc_PO(3),
      ADR3 => Ucore_Uusb_syn5318,
      O => Ucore_Uusb_Uuc_Upsw_C0_N30
    );
  Ucore_Uusb_Uuc_PO_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3330 : X_LUT4
    generic map(
      INIT => X"5544"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6904,
      ADR1 => Ucore_Uusb_syn6926,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C689,
      O => Ucore_Uusb_Uuc_PO_7_FROM
    );
  Ucore_Uusb_C3305 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6904,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_DBUS(7),
      ADR3 => Ucore_Uusb_syn20438,
      O => Ucore_Uusb_Uuc_Upsw_C0_N6
    );
  Ucore_Uusb_Uuc_PO_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PO_7_FROM,
      O => Ucore_Uusb_syn5318
    );
  Ucore_Uusb_Uuc_PO_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2795 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR2 => vp_p10_c,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C25_N5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_resize_doWrite35_0_a2 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_resize_state(2),
      O => Ucore_Ufunc_doneflag_FROM
    );
  Ucore_Ufunc_resize_doWrite37_0_a2 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_resize_doWrite37
    );
  Ucore_Ufunc_doneflag_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_doneflag_FROM,
      O => Ucore_Ufunc_resize_doWrite35
    );
  Ucore_Ufunc_doneflag_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_doneflag_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2782 : X_LUT4
    generic map(
      INIT => X"F858"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N12
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3392 : X_LUT4
    generic map(
      INIT => X"0811"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FROM
    );
  Ucore_Uusb_C3391 : X_LUT4
    generic map(
      INIT => X"F800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C38_N68
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FROM,
      O => Ucore_Uusb_N1467
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2964 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N9
    );
  Ucore_Uusb_C2965 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N3
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N14,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(2)
    );
  Ucore_Uusb_C2962 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(3),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N19
    );
  Ucore_Uusb_C2963 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N14
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N42,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1)
    );
  Ucore_Uusb_C2784 : X_LUT4
    generic map(
      INIT => X"00EE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FROM
    );
  Ucore_Uusb_C2776 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N42
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_FROM,
      O => Ucore_Uusb_syn8481
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3251 : X_LUT4
    generic map(
      INIT => X"0A0A"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N10
    );
  Ucore_Uusb_C3255 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_BUS131(0),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N5
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2778 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N163
    );
  Ucore_Uusb_C2777 : X_LUT4
    generic map(
      INIT => X"7788"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N31
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2960 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N29
    );
  Ucore_Uusb_C2961 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(4),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N24
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N15,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(2)
    );
  Ucore_Uusb_C3249 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_BUS131(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N20
    );
  Ucore_Uusb_C3250 : X_LUT4
    generic map(
      INIT => X"0A0A"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N15
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2958 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N39
    );
  Ucore_Uusb_C2959 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(6),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N34
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N6,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(0)
    );
  Ucore_Uusb_C2883 : X_LUT4
    generic map(
      INIT => X"3FF3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N11
    );
  Ucore_Uusb_C2884 : X_LUT4
    generic map(
      INIT => X"0FFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3247 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR2 => Ucore_Uusb_BUS131(5),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N30
    );
  Ucore_Uusb_C3248 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_BUS131(4),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_NET2015,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N25
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2989 : X_LUT4
    generic map(
      INIT => X"C043"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FROM
    );
  Ucore_Uusb_C2882 : X_LUT4
    generic map(
      INIT => X"6CFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N16
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FROM,
      O => Ucore_Uusb_syn7896
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3844 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_rxd(6),
      ADR1 => Ucore_Uusb_BUS131(6),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FROM
    );
  Ucore_Uusb_C3246 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_BUS131(6),
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N35
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FROM,
      O => Ucore_Uusb_Uusb_BUS67(6)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_un8_doingwrite1 : X_LUT4
    generic map(
      INIT => X"505F"
    )
    port map (
      ADR0 => Ucore_Ufunc_sram_presstate(2),
      ADR1 => VCC,
      ADR2 => clk48x2,
      ADR3 => Ucore_Ufunc_presstate_3_Q,
      O => ram_oe_c_FROM
    );
  Ucore_Ufunc_sram_nextoen_f0 : X_LUT4
    generic map(
      INIT => X"0F0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_sram_doWrite,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_presstate_1_Q,
      ADR3 => Ucore_Ufunc_presstate_3_Q,
      O => Ucore_Ufunc_sram_nextoen
    );
  ram_oe_c_XUSED : X_BUF
    port map (
      I => ram_oe_c_FROM,
      O => ram_we_c
    );
  ram_oe_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => ram_oe_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2845 : X_LUT4
    generic map(
      INIT => X"2C88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8288,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N21
    );
  Ucore_Uusb_C2843 : X_LUT4
    generic map(
      INIT => X"80ED"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      ADR1 => Ucore_Uusb_syn8288,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N47
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2796 : X_LUT4
    generic map(
      INIT => X"5544"
    )
    port map (
      ADR0 => Ucore_urx0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N84,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5329,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N15
    );
  Ucore_Uusb_C2802 : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8421,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR2 => Ucore_urx0,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N27
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2972 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N9
    );
  Ucore_Uusb_C2975 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N3
    );
  Ucore_Uusb_Uusb_rxd_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_rxd_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GWEAND_453 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FWEAND_454 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N35,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU12_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU12_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU12_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N306_RAM32X1_GRAMS
    );
  Ucore_Uusb_Uusb_rxd_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N14,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_3_FFY_RST,
      O => Ucore_Uusb_Uusb_rxd(2)
    );
  Ucore_Uusb_C2970 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(3),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N19
    );
  Ucore_Uusb_C2971 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N14
    );
  Ucore_Uusb_Uusb_rxd_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_rxd_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_OP_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1611,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(0)
    );
  Ucore_Uusb_C3097 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C758,
      ADR1 => Ucore_Uusb_syn7460,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1654
    );
  Ucore_Uusb_C3108 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn7335,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1611
    );
  Ucore_Uusb_C2968 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(5),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N29
    );
  Ucore_Uusb_C2969 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(4),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N24
    );
  Ucore_Uusb_Uusb_rxd_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_rxd_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_rxd_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N34,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_7_FFY_RST,
      O => Ucore_Uusb_Uusb_rxd(6)
    );
  Ucore_Uusb_C2966 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(7),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N39
    );
  Ucore_Uusb_C2967 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(6),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N34
    );
  Ucore_Uusb_Uusb_rxd_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_rxd_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3095 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C564,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1740
    );
  Ucore_Uusb_C3212 : X_LUT4
    generic map(
      INIT => X"5540"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5312,
      ADR2 => Ucore_Uusb_syn5302,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C806,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FROM
    );
  Ucore_Uusb_C3082 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C650,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C597,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_N26
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_GROM,
      O => Ucore_Uusb_syn27978
    );
  Ucore_Ufunc_s_cur_oldRow_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_502_i,
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(6)
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_7_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_0_n,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_s_cur_oldRow_5(7)
    );
  Ucore_Ufunc_N_502_i_455 : X_LUT4
    generic map(
      INIT => X"F3F3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_s_cur_oldRow(6),
      ADR3 => VCC,
      O => Ucore_Ufunc_N_502_i
    );
  Ucore_Ufunc_s_cur_oldRow_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldRow_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_9_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_2_n,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(9)
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_8_Q : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_s_cur_oldRow_5(8)
    );
  Ucore_Ufunc_s_cur_oldRow_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldRow_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_1_Q : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_write_data(1),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_writeData(1),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(1)
    );
  Ucore_Ufunc_sram_writeData_0_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeData(0),
      ADR2 => Ucore_Ufunc_resize_write_data(0),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(0)
    );
  Ucore_Ufunc_sram_writedatareg_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_3_Q : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeData(3),
      ADR1 => Ucore_Ufunc_resize_write_data(3),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_writeData(3)
    );
  Ucore_Ufunc_sram_writeData_2_Q : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_write_data(2),
      ADR2 => Ucore_Ufunc_ram_writeData(2),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(2)
    );
  Ucore_Ufunc_sram_writedatareg_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GWEAND_456 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FWEAND_457 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N34,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU4_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU4_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU4_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N223_RAM32X1_GRAMS
    );
  Ucore_Ufunc_sram_writeData_5_Q : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_write_data(5),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_ram_writeData(5),
      O => Ucore_Ufunc_sram_writeData(5)
    );
  Ucore_Ufunc_sram_writeData_4_Q : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_write_data(4),
      ADR3 => Ucore_Ufunc_ram_writeData(4),
      O => Ucore_Ufunc_sram_writeData(4)
    );
  Ucore_Ufunc_sram_writedatareg_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2920 : X_LUT4
    generic map(
      INIT => X"DDCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N19
    );
  Ucore_Uusb_C2934 : X_LUT4
    generic map(
      INIT => X"E7E7"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N12
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_7_Q : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeData(7),
      ADR2 => Ucore_Ufunc_resize_write_data(7),
      ADR3 => Ucore_Ufunc_imageloaded,
      O => Ucore_Ufunc_sram_writeData(7)
    );
  Ucore_Ufunc_sram_writeData_6_Q : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeData(6),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_resize_write_data(6),
      O => Ucore_Ufunc_sram_writeData(6)
    );
  Ucore_Ufunc_sram_writedatareg_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_9_Q : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeData(9),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_resize_write_data(9),
      O => Ucore_Ufunc_sram_writeData(9)
    );
  Ucore_Ufunc_sram_writeData_8_Q : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_write_data(8),
      ADR3 => Ucore_Ufunc_ram_writeData(8),
      O => Ucore_Ufunc_sram_writeData(8)
    );
  Ucore_Ufunc_sram_writedatareg_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3023 : X_LUT4
    generic map(
      INIT => X"0101"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FROM
    );
  Ucore_Uusb_C2918 : X_LUT4
    generic map(
      INIT => X"EF00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C363
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N15,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(2)
    );
  Ucore_Uusb_C2933 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FROM
    );
  Ucore_Uusb_C2916 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6,
      ADR3 => Ucore_Uusb_syn8037,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N15
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C171
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2793 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N169
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_c_5_0_a2_1_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_un4_nextc_s_1_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(1)
    );
  Ucore_Ufunc_c_5_0_a2_0_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_un4_nextc_s_0_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(0)
    );
  Ucore_Ufunc_c_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_c_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_c_5_0_a2_3_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_un4_nextc_s_3_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(3)
    );
  Ucore_Ufunc_c_5_0_a2_2_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_un4_nextc_s_2_n,
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(2)
    );
  Ucore_Ufunc_c_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_c_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_c_5_0_a2_5_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_un4_nextc_s_5_n,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(5)
    );
  Ucore_Ufunc_c_5_0_a2_4_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_un4_nextc_s_4_n,
      O => Ucore_Ufunc_c_5(4)
    );
  Ucore_Ufunc_c_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_c_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GWEAND_458 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FWEAND_459 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N37,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU28_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU28_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU28_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N472_RAM32X1_GRAMS
    );
  Ucore_Ufunc_c_5_0_a2_7_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_un4_nextc_s_7_n,
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(7)
    );
  Ucore_Ufunc_c_5_0_a2_6_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextc_s_6_n,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_c_5(6)
    );
  Ucore_Ufunc_c_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_c_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_c_5_0_a2_9_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_un4_nextc_s_9_n,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(9)
    );
  Ucore_Ufunc_c_5_0_a2_8_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextc_s_8_n,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_c_5(8)
    );
  Ucore_Ufunc_c_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_c_9_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3227 : X_LUT4
    generic map(
      INIT => X"BF80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N77
    );
  Ucore_Uusb_C3237 : X_LUT4
    generic map(
      INIT => X"26AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N103
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3081 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2517,
      ADR1 => Ucore_Uusb_syn27978,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2345
    );
  Ucore_Uusb_C3138 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27876,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2171,
      ADR2 => Ucore_Uusb_syn7414,
      ADR3 => Ucore_Uusb_syn7410,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2302
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DWR_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2431,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(3)
    );
  Ucore_Uusb_C3073 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27929,
      ADR1 => Ucore_Uusb_syn27928,
      ADR2 => Ucore_Uusb_syn27992,
      ADR3 => Ucore_Uusb_syn5344,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2431
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3155 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FROM
    );
  Ucore_Uusb_C3113 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7499,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1437,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C664,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C578,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1308
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1351
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_stall_en_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C8_N5,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C9_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_stall_en
    );
  Ucore_Uusb_C3406 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6653,
      O => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FROM
    );
  Ucore_Uusb_C3401 : X_LUT4
    generic map(
      INIT => X"50F0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_BUS131(4),
      ADR3 => Ucore_Uusb_syn6653,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C8_N5
    );
  Ucore_Uusb_Uusb_Uep0ctrl_stall_en_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1469
    );
  Ucore_Uusb_Uusb_Uep0ctrl_stall_en_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_stall_en_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_presstate_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_presstate_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_presstate_1_FFY_RST
    );
  Ucore_Ufunc_sram_presstate_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_nextstate,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_presstate_1_FFY_RST,
      O => Ucore_Ufunc_presstate_1_Q
    );
  Ucore_Ufunc_sram_N_231_i_460 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_sram_doWrite,
      ADR1 => Ucore_Ufunc_ram_canRead,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_sram_doRead,
      O => Ucore_Ufunc_presstate_1_FROM
    );
  Ucore_Ufunc_sram_nextstate_461 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Ufunc_sram_doWrite,
      ADR1 => Ucore_Ufunc_ram_canRead,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_sram_doRead,
      O => Ucore_Ufunc_sram_nextstate
    );
  Ucore_Ufunc_presstate_1_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_presstate_1_FROM,
      O => Ucore_Ufunc_sram_N_231_i
    );
  Ucore_Ufunc_presstate_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_presstate_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3129 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7274,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FROM
    );
  Ucore_Uusb_C3128 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N791,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N748
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N791
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DWR_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N834,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(2)
    );
  Ucore_Uusb_C3071 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N877
    );
  Ucore_Uusb_C3211 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N834
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C3_N5,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2
    );
  Ucore_Uusb_C2980 : X_LUT4
    generic map(
      INIT => X"21A9"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FROM
    );
  Ucore_Uusb_C2842 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C3_N5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_FROM,
      O => Ucore_Uusb_syn28235
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3112 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C667,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C765,
      ADR2 => Ucore_Uusb_syn7394,
      ADR3 => Ucore_Uusb_syn5249,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N90
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2876 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_syn6626,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FROM
    );
  Ucore_Uusb_C2874 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      ADR2 => Ucore_Uusb_syn6626,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FROM,
      O => Ucore_Uusb_N1541
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3301 : X_LUT4
    generic map(
      INIT => X"8050"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6779,
      ADR1 => Ucore_Uusb_syn5332,
      ADR2 => Ucore_Uusb_syn6514,
      ADR3 => Ucore_Uusb_syn6524,
      O => Ucore_Uusb_Uuc_Utmp2_sel_FROM
    );
  Ucore_Uusb_C3300 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_T2WR,
      O => Ucore_Uusb_Uuc_Utmp2_sel_GROM
    );
  Ucore_Uusb_Uuc_Utmp2_sel_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Utmp2_sel_FROM,
      O => Ucore_Uusb_Uuc_T2WR
    );
  Ucore_Uusb_Uuc_Utmp2_sel_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Utmp2_sel_GROM,
      O => Ucore_Uusb_N1511
    );
  Ucore_Uusb_Uuc_Utmp2_sel_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Utmp2_sel_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2880 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FROM
    );
  Ucore_Uusb_C2877 : X_LUT4
    generic map(
      INIT => X"A8A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C157,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N15
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FROM,
      O => Ucore_Uusb_syn6626
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_addrreg_4_0_Q : X_LUT4
    generic map(
      INIT => X"8B88"
    )
    port map (
      ADR0 => Ucore_Ufunc_sram_writeAddr(0),
      ADR1 => Ucore_Ufunc_sram_doWrite,
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_ram_readAddr(0),
      O => Ucore_Ufunc_sram_addrreg_4(0)
    );
  a0_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => a0_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3431 : X_LUT4
    generic map(
      INIT => X"AAA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C34_N20
    );
  Ucore_Uusb_C3384 : X_LUT4
    generic map(
      INIT => X"F0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C34_N12
    );
  Ucore_Uusb_BUS126_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_BUS126_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GWEAND_462 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_ADR4_INV,
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FWEAND_463 : X_AND2
    port map (
      I0 => Ucore_Uusb_Uuc_Uram_U1_N36,
      I1 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FWEAND
    );
  Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FWEINV : X_INV
    port map (
      I => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_ADR4_INV
    );
  Ucore_Uusb_Uuc_Uram_U1_BU20_F5 : X_MUX2
    port map (
      IA => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GRAMS,
      IB => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FRAMS,
      SEL => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1
    );
  Ucore_Uusb_Uuc_Uram_U1_BU20_F : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_FRAMS
    );
  Ucore_Uusb_Uuc_Uram_U1_BU20_G : X_RAMS16
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(3),
      I => Ucore_Uusb_Uuc_DBUS(0),
      CLK => Ucore_Uusb_CLK24,
      WE => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GWEAND,
      O => Ucore_Uusb_Uuc_Uram_U1_N389_RAM32X1_GRAMS
    );
  Ucore_Uusb_C3407 : X_LUT4
    generic map(
      INIT => X"FA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(3),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C34_N36
    );
  Ucore_Uusb_C3390 : X_LUT4
    generic map(
      INIT => X"A8A8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C34_N28
    );
  Ucore_Uusb_BUS126_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_BUS126_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3389 : X_LUT4
    generic map(
      INIT => X"CCDC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR2 => Ucore_Uusb_syn6653,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C34_N53
    );
  Ucore_Uusb_C3427 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      O => Ucore_Uusb_BUS126_6_GROM
    );
  Ucore_Uusb_BUS126_6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_BUS126_6_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_N219
    );
  Ucore_Uusb_BUS126_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_BUS126_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3433 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => VCC,
      O => Ucore_Uusb_BUS126_7_FROM
    );
  Ucore_Uusb_C3404 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_stall_en,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      O => Ucore_Uusb_BUS126_7_GROM
    );
  Ucore_Uusb_BUS126_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_BUS126_7_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_N210
    );
  Ucore_Uusb_BUS126_7_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_BUS126_7_GROM,
      O => Ucore_Uusb_syn6704
    );
  Ucore_Uusb_BUS126_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_BUS126_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_11_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_4_n,
      O => Ucore_Ufunc_s_cur_oldCol_5(11)
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_10_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_3_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldCol_5(10)
    );
  Ucore_Ufunc_s_cur_oldCol_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldCol_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_13_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_6_n,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldCol_5(13)
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_12_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_5_n,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldCol_5(12)
    );
  Ucore_Ufunc_s_cur_oldCol_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldCol_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_15_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_8_n,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_s_cur_oldCol_5(15)
    );
  Ucore_Ufunc_s_cur_oldCol_5_0_a2_14_Q : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_un4_nexts_cur_oldCol_s_7_n,
      O => Ucore_Ufunc_s_cur_oldCol_5(14)
    );
  Ucore_Ufunc_s_cur_oldCol_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldCol_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3441 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_Uglue_txen1_FROM
    );
  Ucore_Uusb_C3437 : X_LUT4
    generic map(
      INIT => X"55D5"
    )
    port map (
      ADR0 => Ucore_Uusb_IT(1),
      ADR1 => Ucore_Uusb_Uglue_bytecount(1),
      ADR2 => Ucore_Uusb_Uglue_txen1,
      ADR3 => Ucore_Uusb_NET3345,
      O => Ucore_Uusb_Uglue_txen1_GROM
    );
  Ucore_Uusb_Uglue_txen1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_txen1_FROM,
      O => Ucore_Uusb_NET3345
    );
  Ucore_Uusb_Uglue_txen1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_txen1_GROM,
      O => Ucore_Uusb_Uglue_C29_N9
    );
  Ucore_Uusb_Uglue_txen1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uglue_txen1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3417 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      O => Ucore_Uusb_Uusb_TG_0_FROM
    );
  Ucore_Uusb_C3393 : X_LUT4
    generic map(
      INIT => X"FFDE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_in_en,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR2 => Ucore_Uusb_Uusb_TG(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C36_N6
    );
  Ucore_Uusb_Uusb_TG_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_TG_0_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1454
    );
  Ucore_Uusb_Uusb_TG_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_TG_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3378 : X_LUT4
    generic map(
      INIT => X"2828"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6739,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N10
    );
  Ucore_Uusb_C3382 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6739,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N5
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3345 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_Uuc_ABUS(11),
      O => Ucore_Uusb_Uuc_Udptr_C4_N6
    );
  Ucore_Uusb_C3342 : X_LUT4
    generic map(
      INIT => X"EE44"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6831,
      ADR1 => Ucore_Uusb_Uuc_DBUS(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_ABUS(10),
      O => Ucore_Uusb_Uuc_Udptr_C6_N6
    );
  Ucore_Uusb_Uuc_DPTRO_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_11_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3355 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(13),
      ADR1 => Ucore_Uusb_Uuc_DBUS(5),
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C0_N6
    );
  Ucore_Uusb_C3338 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn6831,
      ADR2 => Ucore_Uusb_Uuc_DBUS(4),
      ADR3 => Ucore_Uusb_Uuc_ABUS(12),
      O => Ucore_Uusb_Uuc_Udptr_C2_N6
    );
  Ucore_Uusb_Uuc_DPTRO_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_13_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3351 : X_LUT4
    generic map(
      INIT => X"F1F0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6519,
      ADR1 => Ucore_Uusb_syn6527,
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_syn5315,
      O => Ucore_Uusb_Uuc_DPTRO_15_FROM
    );
  Ucore_Uusb_C3348 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(7),
      ADR1 => Ucore_Uusb_syn6831,
      ADR2 => Ucore_Uusb_Uuc_ABUS(15),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Udptr_C28_N6
    );
  Ucore_Uusb_Uuc_DPTRO_15_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DPTRO_15_FROM,
      O => Ucore_Uusb_N1483
    );
  Ucore_Uusb_Uuc_DPTRO_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3387 : X_LUT4
    generic map(
      INIT => X"2A2A"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(5),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR2 => Ucore_Uusb_syn6653,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C5_N5
    );
  Ucore_Uusb_C3395 : X_LUT4
    generic map(
      INIT => X"3F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn6653,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_BUS131(6),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C2_N5
    );
  Ucore_Uusb_Uusb_Uep0ctrl_setup_en_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_OP_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1178,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(1)
    );
  Ucore_Uusb_C3114 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N53,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1221,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FROM
    );
  Ucore_Uusb_C3130 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C578,
      ADR1 => Ucore_Uusb_syn7441,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N53,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1178
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_1_FROM,
      O => Ucore_Uusb_syn7499
    );
  Ucore_Uusb_C3172 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5300,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR2 => Ucore_Uusb_syn5290,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FROM
    );
  Ucore_Uusb_C3087 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7321,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR2 => Ucore_Uusb_syn7304,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1221,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1221
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1523
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_OP_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(3)
    );
  Ucore_Uusb_C3154 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5312,
      ADR3 => Ucore_Uusb_syn5163,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FROM
    );
  Ucore_Uusb_C3219 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5312,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR3 => Ucore_Uusb_syn5163,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C576
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_3_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_N53
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_11_Q : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_4_n,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(11)
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_10_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_3_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(10)
    );
  Ucore_Ufunc_s_cur_oldRow_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldRow_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_13_Q : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_6_n,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_s_cur_oldRow_5(13)
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_12_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_5_n,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(12)
    );
  Ucore_Ufunc_s_cur_oldRow_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldRow_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_15_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(15)
    );
  Ucore_Ufunc_s_cur_oldRow_5_0_a2_14_Q : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nexts_cur_oldRow_s_7_n,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_s_cur_oldRow_5(14)
    );
  Ucore_Ufunc_s_cur_oldRow_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_cur_oldRow_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3090 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C667,
      ADR1 => Ucore_Uusb_syn7532,
      ADR2 => Ucore_Uusb_syn27960,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C765,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2818
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_12_Q : X_LUT4
    generic map(
      INIT => X"A280"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => Ucore_Ufunc_N_501,
      ADR2 => Ucore_Ufunc_N_64,
      ADR3 => Ucore_Ufunc_N_47,
      O => Ucore_Ufunc_addr_offset_5(12)
    );
  Ucore_Ufunc_addr_offset_5_11_Q : X_LUT4
    generic map(
      INIT => X"B080"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_63,
      ADR1 => Ucore_Ufunc_N_501,
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_N_46,
      O => Ucore_Ufunc_addr_offset_5(11)
    );
  Ucore_Ufunc_addr_offset_12_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_12_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_14_Q : X_LUT4
    generic map(
      INIT => X"8A80"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => Ucore_Ufunc_N_66,
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_N_49,
      O => Ucore_Ufunc_addr_offset_5(14)
    );
  Ucore_Ufunc_addr_offset_5_13_Q : X_LUT4
    generic map(
      INIT => X"B800"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_65,
      ADR1 => Ucore_Ufunc_N_501,
      ADR2 => Ucore_Ufunc_N_48,
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_addr_offset_5(13)
    );
  Ucore_Ufunc_addr_offset_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_14_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_4_Q : X_LUT4
    generic map(
      INIT => X"C088"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_39,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_56,
      ADR3 => Ucore_Ufunc_N_501,
      O => Ucore_Ufunc_addr_offset_5(4)
    );
  Ucore_Ufunc_addr_offset_5_3_Q : X_LUT4
    generic map(
      INIT => X"A00A"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_addr_offset(3),
      O => Ucore_Ufunc_addr_offset_5(3)
    );
  Ucore_Ufunc_addr_offset_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_4_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_16_Q : X_LUT4
    generic map(
      INIT => X"C480"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_501,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_68,
      ADR3 => Ucore_Ufunc_N_51_0,
      O => Ucore_Ufunc_addr_offset_5(16)
    );
  Ucore_Ufunc_addr_offset_5_15_Q : X_LUT4
    generic map(
      INIT => X"88C0"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_67,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_50,
      ADR3 => Ucore_Ufunc_N_501,
      O => Ucore_Ufunc_addr_offset_5(15)
    );
  Ucore_Ufunc_addr_offset_16_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_16_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_writeData_11_Q : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_write_data(11),
      ADR1 => Ucore_Ufunc_imageloaded,
      ADR2 => Ucore_Ufunc_ram_writeData(11),
      ADR3 => VCC,
      O => Ucore_Ufunc_sram_writeData(11)
    );
  Ucore_Ufunc_sram_writeData_10_Q : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeData(10),
      ADR2 => Ucore_Ufunc_imageloaded,
      ADR3 => Ucore_Ufunc_resize_write_data(10),
      O => Ucore_Ufunc_sram_writeData(10)
    );
  Ucore_Ufunc_sram_writedatareg_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_writedatareg_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_6_Q : X_LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => Ucore_Ufunc_N_501,
      ADR2 => Ucore_Ufunc_N_41,
      ADR3 => Ucore_Ufunc_N_58,
      O => Ucore_Ufunc_addr_offset_5(6)
    );
  Ucore_Ufunc_addr_offset_5_5_Q : X_LUT4
    generic map(
      INIT => X"CA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_40,
      ADR1 => Ucore_Ufunc_N_57,
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_addr_offset_5(5)
    );
  Ucore_Ufunc_addr_offset_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_6_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_N_7_i_i_a2 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_resize_state_2_rep1,
      O => Ucore_Ufunc_addr_offset_17_FROM
    );
  Ucore_Ufunc_addr_offset_5_17_Q : X_LUT4
    generic map(
      INIT => X"CA00"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_52,
      ADR1 => Ucore_Ufunc_N_69,
      ADR2 => Ucore_Ufunc_N_501,
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_addr_offset_5(17)
    );
  Ucore_Ufunc_addr_offset_17_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_17_FROM,
      O => Ucore_Ufunc_N_7_i_i_a2_n
    );
  Ucore_Ufunc_addr_offset_17_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_17_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uport0_pad_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(2),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(2)
    );
  Ucore_Uusb_Uuc_Uport0_pad_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(4),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_5_FFY_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(4)
    );
  Ucore_Uusb_Uuc_Uport0_pad_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(6),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_7_FFY_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(6)
    );
  Ucore_Ufunc_resize_doWrite29_0_a2 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(0),
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_resize_doWrite29_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_0_3_Q : X_LUT4
    generic map(
      INIT => X"A88A"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state(2),
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_resize_doWrite29_GROM
    );
  Ucore_Ufunc_resize_doWrite29_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doWrite29_FROM,
      O => Ucore_Ufunc_resize_doWrite29
    );
  Ucore_Ufunc_resize_doWrite29_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doWrite29_GROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_0(3)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_prev_cur_oldRow_11_SRMUX_OUTPUTNOT
    );
  g0_3_a2_7_464 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(4),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_ram_writeAddr(11),
      ADR3 => VCC,
      O => g0_3_a2_7_FROM
    );
  g0_0_a3_10_465 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(11),
      ADR1 => Ucore_Ufunc_ram_writeAddr(15),
      ADR2 => Ucore_Ufunc_ram_writeAddr(18),
      ADR3 => Ucore_Ufunc_ram_writeAddr(16),
      O => g0_3_a2_7_GROM
    );
  g0_3_a2_7_XUSED : X_BUF
    port map (
      I => g0_3_a2_7_FROM,
      O => g0_3_a2_7
    );
  g0_3_a2_7_YUSED : X_BUF
    port map (
      I => g0_3_a2_7_GROM,
      O => g0_0_a3_10
    );
  g0_1_4_466 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(0),
      ADR1 => Ucore_Ufunc_ram_writeAddr(1),
      ADR2 => Ucore_Ufunc_ram_writeAddr(14),
      ADR3 => Ucore_Ufunc_ram_writeAddr(2),
      O => g0_1_4_FROM
    );
  g0_0_a3_11_467 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(2),
      ADR1 => Ucore_Ufunc_ram_writeAddr(1),
      ADR2 => Ucore_Ufunc_ram_writeAddr(0),
      ADR3 => Ucore_Ufunc_ram_writeAddr(14),
      O => g0_1_4_GROM
    );
  g0_1_4_XUSED : X_BUF
    port map (
      I => g0_1_4_FROM,
      O => g0_1_4
    );
  g0_1_4_YUSED : X_BUF
    port map (
      I => g0_1_4_GROM,
      O => g0_0_a3_11
    );
  g0_0_a3_12_468 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(12),
      ADR1 => Ucore_Ufunc_ram_writeAddr(8),
      ADR2 => Ucore_Ufunc_ram_writeAddr(9),
      ADR3 => Ucore_Ufunc_ram_writeAddr(13),
      O => g0_0_a3_12_FROM
    );
  g0_0_a3_17_469 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_ram_writeAddr_1_11,
      ADR1 => g0_0_a3_10,
      ADR2 => g0_0_a3_11,
      ADR3 => g0_0_a3_12,
      O => g0_0_a3_12_GROM
    );
  g0_0_a3_12_XUSED : X_BUF
    port map (
      I => g0_0_a3_12_FROM,
      O => g0_0_a3_12
    );
  g0_0_a3_12_YUSED : X_BUF
    port map (
      I => g0_0_a3_12_GROM,
      O => g0_0_a3_17
    );
  Ucore_Ufunc_s_prev_cur_oldRow_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_prev_cur_oldRow_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_s_prev_cur_oldRow_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_prev_cur_oldRow_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_1_4_Q : X_LUT4
    generic map(
      INIT => X"5AAA"
    )
    port map (
      ADR0 => Ucore_Ufunc_addr_offset(4),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_N_56_FROM
    );
  Ucore_Ufunc_addr_offset_5_sn_m2_i_a2_1_470 : X_LUT4
    generic map(
      INIT => X"2828"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_520,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_2_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR3 => VCC,
      O => Ucore_Ufunc_N_56_GROM
    );
  Ucore_Ufunc_N_56_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_56_FROM,
      O => Ucore_Ufunc_N_56
    );
  Ucore_Ufunc_N_56_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_56_GROM,
      O => Ucore_Ufunc_addr_offset_5_sn_m2_i_a2_1
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_0_3_Q : X_LUT4
    generic map(
      INIT => X"F010"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_FROM
    );
  Ucore_Ufunc_sram_writeAddr_0_Q : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(0),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_imageloaded_rep1,
      ADR3 => Ucore_Ufunc_i(0),
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_GROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_FROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_a2_0(3)
    );
  Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_nextresize_state_enl_0_a2_0_3_GROM,
      O => Ucore_Ufunc_sram_writeAddr(0)
    );
  Ucore_Ufunc_ram_writeData_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeData_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un51_nextresize_statelto5_0_a2 : X_LUT4
    generic map(
      INIT => X"FC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_r(3),
      ADR2 => Ucore_Ufunc_r(4),
      ADR3 => Ucore_Ufunc_r(5),
      O => Ucore_Ufunc_N_567_GROM
    );
  Ucore_Ufunc_N_567_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_567_GROM,
      O => Ucore_Ufunc_N_567
    );
  Ucore_Ufunc_ram_writeData_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uphy_un1_vm_1 : X_LUT4
    generic map(
      INIT => X"0033"
    )
    port map (
      ADR0 => VCC,
      ADR1 => vm_p9_c,
      ADR2 => VCC,
      ADR3 => vp_p10_c,
      O => Ucore_urx0_FROM
    );
  Ucore_Uusb_C2804 : X_LUT4
    generic map(
      INIT => X"7040"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(1),
      ADR3 => Ucore_urx0,
      O => Ucore_urx0_GROM
    );
  Ucore_urx0_XUSED : X_BUF
    port map (
      I => Ucore_urx0_FROM,
      O => Ucore_urx0
    );
  Ucore_urx0_YUSED : X_BUF
    port map (
      I => Ucore_urx0_GROM,
      O => Ucore_Uusb_syn28585
    );
  g0_0_2_0 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_low_temp2_fast_6_Q,
      ADR1 => Ucore_Ufunc_high_temp2_fast(7),
      ADR2 => Ucore_Ufunc_high_temp2_fast(6),
      ADR3 => Ucore_Ufunc_low_temp2_fast_7_Q,
      O => N_125_GROM
    );
  N_125_YUSED : X_BUF
    port map (
      I => N_125_GROM,
      O => N_125
    );
  Ucore_Ufunc_un1_temp2_2_8 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_low_temp2_fast(2),
      ADR1 => Ucore_Ufunc_low_temp2_fast(4),
      ADR2 => Ucore_Ufunc_low_temp2_fast(3),
      ADR3 => Ucore_Ufunc_low_temp2_fast(5),
      O => Ucore_Ufunc_un1_temp2_2_8_0_FROM
    );
  Ucore_Ufunc_un1_temp2_1_10_471 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_low_temp2_fast(4),
      ADR1 => Ucore_Ufunc_high_temp2_fast(1),
      ADR2 => Ucore_Ufunc_high_temp2_fast(0),
      ADR3 => Ucore_Ufunc_low_temp2_fast(5),
      O => Ucore_Ufunc_un1_temp2_2_8_0_GROM
    );
  Ucore_Ufunc_un1_temp2_2_8_0_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_2_8_0_FROM,
      O => Ucore_Ufunc_un1_temp2_2_8_0
    );
  Ucore_Ufunc_un1_temp2_2_8_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_2_8_0_GROM,
      O => Ucore_Ufunc_un1_temp2_1_10
    );
  Ucore_Ufunc_un1_temp2_1_11_472 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_high_temp2_fast(4),
      ADR1 => Ucore_Ufunc_high_temp2_fast(2),
      ADR2 => Ucore_Ufunc_high_temp2_fast(3),
      ADR3 => Ucore_Ufunc_high_temp2_fast(5),
      O => Ucore_Ufunc_un1_temp2_1_11_FROM
    );
  g0_0_0 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_1_9,
      ADR1 => N_125,
      ADR2 => Ucore_Ufunc_un1_temp2_1_10,
      ADR3 => Ucore_Ufunc_un1_temp2_1_11,
      O => Ucore_Ufunc_un1_temp2_1_11_GROM
    );
  Ucore_Ufunc_un1_temp2_1_11_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_1_11_FROM,
      O => Ucore_Ufunc_un1_temp2_1_11
    );
  Ucore_Ufunc_un1_temp2_1_11_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_1_11_GROM,
      O => Ucore_Ufunc_un1_temp2_1
    );
  Ucore_Ufunc_addr_offset_5_1_5_Q : X_LUT4
    generic map(
      INIT => X"8F07"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_addr_offset(5),
      ADR3 => Ucore_Ufunc_un9_nextaddr_offset_s_1_n,
      O => Ucore_Ufunc_N_57_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_10_Q : X_LUT4
    generic map(
      INIT => X"F780"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR2 => Ucore_Ufunc_un9_nextaddr_offset_s_6_n,
      ADR3 => Ucore_Ufunc_un19_nextaddr_offset_s_5_n,
      O => Ucore_Ufunc_N_57_GROM
    );
  Ucore_Ufunc_N_57_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_57_FROM,
      O => Ucore_Ufunc_N_57
    );
  Ucore_Ufunc_N_57_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_57_GROM,
      O => Ucore_Ufunc_N_62
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_1_6_Q : X_LUT4
    generic map(
      INIT => X"ACCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un9_nextaddr_offset_s_2_n,
      ADR1 => Ucore_Ufunc_un19_nextaddr_offset_s_1_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_N_58_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_11_Q : X_LUT4
    generic map(
      INIT => X"F780"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un9_nextaddr_offset_s_7_n,
      ADR3 => Ucore_Ufunc_un19_nextaddr_offset_s_6_n,
      O => Ucore_Ufunc_N_58_GROM
    );
  Ucore_Ufunc_N_58_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_58_FROM,
      O => Ucore_Ufunc_N_58
    );
  Ucore_Ufunc_N_58_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_58_GROM,
      O => Ucore_Ufunc_N_63
    );
  Ucore_Ufunc_addr_offset_5_1_7_Q : X_LUT4
    generic map(
      INIT => X"B8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un9_nextaddr_offset_s_3_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_2_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_N_59_0_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_12_Q : X_LUT4
    generic map(
      INIT => X"BF80"
    )
    port map (
      ADR0 => Ucore_Ufunc_un9_nextaddr_offset_s_8_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR2 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR3 => Ucore_Ufunc_un19_nextaddr_offset_s_7_n,
      O => Ucore_Ufunc_N_59_0_GROM
    );
  Ucore_Ufunc_N_59_0_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_59_0_FROM,
      O => Ucore_Ufunc_N_59_0
    );
  Ucore_Ufunc_N_59_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_59_0_GROM,
      O => Ucore_Ufunc_N_64
    );
  Ucore_Ufunc_addr_offset_5_1_8_Q : X_LUT4
    generic map(
      INIT => X"E4CC"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un19_nextaddr_offset_s_3_n,
      ADR2 => Ucore_Ufunc_un9_nextaddr_offset_s_4_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      O => Ucore_Ufunc_N_60_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_13_Q : X_LUT4
    generic map(
      INIT => X"D8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un9_nextaddr_offset_s_9_n,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_8_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      O => Ucore_Ufunc_N_60_GROM
    );
  Ucore_Ufunc_N_60_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_60_FROM,
      O => Ucore_Ufunc_N_60
    );
  Ucore_Ufunc_N_60_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_60_GROM,
      O => Ucore_Ufunc_N_65
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_1_9_Q : X_LUT4
    generic map(
      INIT => X"F870"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_4_n,
      ADR3 => Ucore_Ufunc_un9_nextaddr_offset_s_5_n,
      O => Ucore_Ufunc_N_61_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_14_Q : X_LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un19_nextaddr_offset_s_9_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR3 => Ucore_Ufunc_un9_nextaddr_offset_s_10_n,
      O => Ucore_Ufunc_N_61_GROM
    );
  Ucore_Ufunc_N_61_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_61_FROM,
      O => Ucore_Ufunc_N_61
    );
  Ucore_Ufunc_N_61_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_61_GROM,
      O => Ucore_Ufunc_N_66
    );
  Ucore_Ufunc_addr_offset_5_1_16_Q : X_LUT4
    generic map(
      INIT => X"D8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un9_nextaddr_offset_s_12_n,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_11_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      O => Ucore_Ufunc_N_68_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_15_Q : X_LUT4
    generic map(
      INIT => X"B8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un9_nextaddr_offset_s_11_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_10_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_N_68_GROM
    );
  Ucore_Ufunc_N_68_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_68_FROM,
      O => Ucore_Ufunc_N_68
    );
  Ucore_Ufunc_N_68_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_68_GROM,
      O => Ucore_Ufunc_N_67
    );
  Ucore_Ufunc_addr_offset_5_1_17_Q : X_LUT4
    generic map(
      INIT => X"B8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un9_nextaddr_offset_s_13_n,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_12_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      O => Ucore_Ufunc_N_69_GROM
    );
  Ucore_Ufunc_N_69_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_69_GROM,
      O => Ucore_Ufunc_N_69
    );
  Ucore_Ufunc_next_write_data38_473 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(0),
      ADR1 => Ucore_Ufunc_state(2),
      ADR2 => Ucore_Ufunc_state(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_next_write_data38_FROM
    );
  Ucore_Ufunc_dwire6_474 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(1),
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_state(2),
      ADR3 => Ucore_Ufunc_state(0),
      O => Ucore_Ufunc_next_write_data38_GROM
    );
  Ucore_Ufunc_next_write_data38_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data38_FROM,
      O => Ucore_Ufunc_next_write_data38
    );
  Ucore_Ufunc_next_write_data38_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data38_GROM,
      O => Ucore_Ufunc_dwire6
    );
  Ucore_Uusb_TI_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_TI_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_TI_1_FFY_RST
    );
  Ucore_Uusb_Uglue_togglein_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_TI_1_BYMUXNOT,
      CE => Ucore_Uusb_Uglue_n_1032,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_TI_1_FFY_RST,
      O => Ucore_Uusb_TI(1)
    );
  Ucore_Uusb_TI_1_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_TI(1),
      O => Ucore_Uusb_TI_1_BYMUXNOT
    );
  Ucore_Uusb_TI_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_TI_1_SRMUX_OUTPUTNOT
    );
  g0_3_5_0_475 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(3),
      ADR1 => Ucore_Ufunc_temp2(0),
      ADR2 => Ucore_Ufunc_temp2(4),
      ADR3 => Ucore_Ufunc_temp2(2),
      O => g0_3_5_0_GROM
    );
  g0_3_5_0_YUSED : X_BUF
    port map (
      I => g0_3_5_0_GROM,
      O => g0_3_5_0
    );
  Ucore_Uusb_Uuc_OP2_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_5_FFY_RST,
      O => Ucore_Uusb_Uuc_OP2(4)
    );
  Ucore_Uusb_Uuc_OP2_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_7_FFY_RST,
      O => Ucore_Uusb_Uuc_OP2(6)
    );
  Ucore_Ufunc_resize_doRead_0_a2 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_canRead,
      ADR1 => Ucore_Ufunc_N_429,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => Ucore_Ufunc_resize_state_fast_2_Q,
      O => Ucore_Ufunc_resize_doRead_FROM
    );
  Ucore_Ufunc_sram_doRead_u : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_doRead,
      ADR1 => Ucore_Ufunc_next_write_data40,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_imageloaded_fast,
      O => Ucore_Ufunc_resize_doRead_GROM
    );
  Ucore_Ufunc_resize_doRead_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doRead_FROM,
      O => Ucore_Ufunc_resize_doRead
    );
  Ucore_Ufunc_resize_doRead_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doRead_GROM,
      O => Ucore_Ufunc_sram_doRead
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_LOGIC_ONE_476 : X_ONE
    port map (
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_LOGIC_ONE
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_BYMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_SRMUX_OUTPUTNOT
    );
  g0_0_a2_3_0_a2 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(3),
      ADR1 => Ucore_Ufunc_ram_writeAddr(4),
      ADR2 => Ucore_Ufunc_ram_writeAddr(5),
      ADR3 => Ucore_Ufunc_ram_writeAddr(6),
      O => Ucore_Ufunc_un1_ram_writeAddr_1_11_FROM
    );
  g0_3_a2_14_477 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(6),
      ADR1 => Ucore_Ufunc_ram_writeAddr(9),
      ADR2 => Ucore_Ufunc_ram_writeAddr(8),
      ADR3 => Ucore_Ufunc_ram_writeAddr(3),
      O => Ucore_Ufunc_un1_ram_writeAddr_1_11_GROM
    );
  Ucore_Ufunc_un1_ram_writeAddr_1_11_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_ram_writeAddr_1_11_FROM,
      O => Ucore_Ufunc_un1_ram_writeAddr_1_11
    );
  Ucore_Ufunc_un1_ram_writeAddr_1_11_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_ram_writeAddr_1_11_GROM,
      O => g0_3_a2_14
    );
  Ucore_Ufunc_s_prev_cur_oldRow_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_prev_cur_oldRow_7_SRMUX_OUTPUTNOT
    );
  g0_3_a2_18_478 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => g0_3_a2_14,
      ADR1 => g0_3_a2_7,
      ADR2 => Ucore_Ufunc_state(2),
      ADR3 => Ucore_Ufunc_ram_writeAddr(5),
      O => g0_3_a2_18_FROM
    );
  g0_1_0 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => g0_0_7,
      ADR1 => g0_1_5,
      ADR2 => g0_1_4,
      ADR3 => g0_3_a2_18,
      O => g0_3_a2_18_GROM
    );
  g0_3_a2_18_XUSED : X_BUF
    port map (
      I => g0_3_a2_18_FROM,
      O => g0_3_a2_18
    );
  g0_3_a2_18_YUSED : X_BUF
    port map (
      I => g0_3_a2_18_GROM,
      O => Ucore_Ufunc_un1_ram_writeAddr_1
    );
  Ucore_Ufunc_s_prev_cur_oldRow_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_s_prev_cur_oldRow_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeData_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_1_SRMUX_OUTPUTNOT
    );
  g0_1_5_479 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_ram_writeAddr(13),
      ADR1 => Ucore_Ufunc_ram_writeAddr(7),
      ADR2 => Ucore_Ufunc_ram_writeAddr(12),
      ADR3 => Ucore_Ufunc_ram_writeAddr(10),
      O => g0_1_5_GROM
    );
  g0_1_5_YUSED : X_BUF
    port map (
      I => g0_1_5_GROM,
      O => g0_1_5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_SRMUX_OUTPUTNOT
    );
  g0_L3 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_low_temp2_fast_0_Q,
      ADR1 => Ucore_Ufunc_high_temp2_fast(3),
      ADR2 => Ucore_Ufunc_high_temp2_fast(2),
      ADR3 => Ucore_Ufunc_low_temp2_fast_1_Q,
      O => g0_L3_n_FROM
    );
  Ucore_Ufunc_un1_temp2_1_9_480 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_low_temp2_fast(3),
      ADR1 => Ucore_Ufunc_low_temp2_fast_0_Q,
      ADR2 => Ucore_Ufunc_low_temp2_fast(2),
      ADR3 => Ucore_Ufunc_low_temp2_fast_1_Q,
      O => g0_L3_n_GROM
    );
  g0_L3_n_XUSED : X_BUF
    port map (
      I => g0_L3_n_FROM,
      O => g0_L3_n
    );
  g0_L3_n_YUSED : X_BUF
    port map (
      I => g0_L3_n_GROM,
      O => Ucore_Ufunc_un1_temp2_1_9
    );
  g0_2_4_481 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(13),
      ADR1 => Ucore_Ufunc_temp2(1),
      ADR2 => Ucore_Ufunc_temp2(9),
      ADR3 => Ucore_Ufunc_temp2(5),
      O => g0_2_4_GROM
    );
  g0_2_4_YUSED : X_BUF
    port map (
      I => g0_2_4_GROM,
      O => g0_2_4
    );
  Ucore_Ufunc_ram_writeData_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_3_SRMUX_OUTPUTNOT
    );
  g0_2_5_482 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(11),
      ADR1 => Ucore_Ufunc_temp2(12),
      ADR2 => Ucore_Ufunc_temp2(10),
      ADR3 => Ucore_Ufunc_temp2(8),
      O => g0_2_5_GROM
    );
  g0_2_5_YUSED : X_BUF
    port map (
      I => g0_2_5_GROM,
      O => g0_2_5
    );
  Ucore_Ufunc_un1_temp2_2_7_483 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_high_temp2_fast(2),
      ADR1 => Ucore_Ufunc_high_temp2_fast(3),
      ADR2 => Ucore_Ufunc_low_temp2_fast_1_Q,
      ADR3 => Ucore_Ufunc_low_temp2_fast_0_Q,
      O => Ucore_Ufunc_un1_temp2_2_7_FROM
    );
  g0_1_L5 : X_LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      ADR0 => g0_1_L1_n,
      ADR1 => g0_0_a2_x_n,
      ADR2 => Ucore_Ufunc_high_temp2_fast(0),
      ADR3 => Ucore_Ufunc_un1_temp2_2_7,
      O => Ucore_Ufunc_un1_temp2_2_7_GROM
    );
  Ucore_Ufunc_un1_temp2_2_7_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_2_7_FROM,
      O => Ucore_Ufunc_un1_temp2_2_7
    );
  Ucore_Ufunc_un1_temp2_2_7_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_temp2_2_7_GROM,
      O => g0_1_L5_n
    );
  Ucore_Ufunc_ram_writeData_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeData_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeData_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeData_9_SRMUX_OUTPUTNOT
    );
  g0_0 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => g0_0_a3_17,
      ADR1 => g0_0_a3_16,
      ADR2 => Ucore_Ufunc_N_243,
      ADR3 => Ucore_Ufunc_N_240_1,
      O => Ucore_Ufunc_N_217_i_GROM
    );
  Ucore_Ufunc_N_217_i_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_217_i_GROM,
      O => Ucore_Ufunc_N_217_i
    );
  Ucore_Ufunc_ram_writeAddr_s_18_Q : X_XOR2
    port map (
      I0 => Ucore_Ufunc_ram_writeAddr_18_CYINIT,
      I1 => Ucore_Ufunc_ram_writeAddr_qxu(18),
      O => Ucore_Ufunc_ram_writeAddr_s(18)
    );
  Ucore_Ufunc_ram_writeAddr_qxu_0_18_Q : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_ram_writeAddr(18),
      ADR2 => Ucore_Ufunc_N_218,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_writeAddr_qxu(18)
    );
  g0_1 : X_LUT4
    generic map(
      INIT => X"45CF"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_temp2_3,
      ADR1 => Ucore_Ufunc_doneflag,
      ADR2 => Ucore_Ufunc_un1_ram_writeAddr_1,
      ADR3 => g0_1_1,
      O => Ucore_Ufunc_ram_writeAddr_18_GROM
    );
  Ucore_Ufunc_ram_writeAddr_18_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_18_GROM,
      O => Ucore_Ufunc_N_218
    );
  Ucore_Ufunc_ram_writeAddr_18_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_ram_writeAddr_18_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ram_writeAddr_18_CYINIT_484 : X_BUF
    port map (
      I => Ucore_Ufunc_ram_writeAddr_cry_17_O,
      O => Ucore_Ufunc_ram_writeAddr_18_CYINIT
    );
  g0_0_a2_2_1_a2 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(0),
      ADR1 => Ucore_Ufunc_state(2),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_state(1),
      O => Ucore_Ufunc_next_write_data37_FROM
    );
  Ucore_Ufunc_next_write_data40_485 : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(0),
      ADR1 => Ucore_Ufunc_state(1),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_state(2),
      O => Ucore_Ufunc_next_write_data37_GROM
    );
  Ucore_Ufunc_next_write_data37_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data37_FROM,
      O => Ucore_Ufunc_next_write_data37
    );
  Ucore_Ufunc_next_write_data37_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data37_GROM,
      O => Ucore_Ufunc_next_write_data40
    );
  g0_L5 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(14),
      ADR1 => Ucore_Ufunc_temp2(15),
      ADR2 => Ucore_Ufunc_temp2(6),
      ADR3 => Ucore_Ufunc_temp2(7),
      O => g0_L5_O_FROM
    );
  g4_0_486 : X_LUT4
    generic map(
      INIT => X"EEFF"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(14),
      ADR1 => Ucore_Ufunc_temp2(15),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un1_temp2_2_7,
      O => g0_L5_O_GROM
    );
  g0_L5_O_XUSED : X_BUF
    port map (
      I => g0_L5_O_FROM,
      O => g0_L5_O
    );
  g0_L5_O_YUSED : X_BUF
    port map (
      I => g0_L5_O_GROM,
      O => g4_0
    );
  g4_1_487 : X_LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(6),
      ADR1 => N_112,
      ADR2 => Ucore_Ufunc_un1_temp2_2_8_0,
      ADR3 => Ucore_Ufunc_temp2(7),
      O => g4_1_FROM
    );
  g0_0_a2_0 : X_LUT4
    generic map(
      INIT => X"0054"
    )
    port map (
      ADR0 => Ucore_Ufunc_imageloaded_fast,
      ADR1 => g4_0,
      ADR2 => g4_1,
      ADR3 => Ucore_Ufunc_un1_temp2_1,
      O => g4_1_GROM
    );
  g4_1_XUSED : X_BUF
    port map (
      I => g4_1_FROM,
      O => g4_1
    );
  g4_1_YUSED : X_BUF
    port map (
      I => g4_1_GROM,
      O => Ucore_Ufunc_N_243
    );
  Ucore_Ufunc_un1_dwire6 : X_LUT4
    generic map(
      INIT => X"DF3F"
    )
    port map (
      ADR0 => Ucore_Ufunc_next_state36,
      ADR1 => Ucore_Ufunc_state(0),
      ADR2 => Ucore_Ufunc_state(2),
      ADR3 => Ucore_Ufunc_state(1),
      O => Ucore_Ufunc_N_244_FROM
    );
  Ucore_Ufunc_next_write_data39_488 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_state(2),
      O => Ucore_Ufunc_N_244_GROM
    );
  Ucore_Ufunc_N_244_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_244_FROM,
      O => Ucore_Ufunc_N_244
    );
  Ucore_Ufunc_N_244_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_244_GROM,
      O => Ucore_Ufunc_next_write_data39
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0_489 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_8_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0_GROM
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0_GROM,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0
    );
  Ucore_Ufunc_resize_state_fast_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_resize_state_fast_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_BYMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_imageloaded_fast_BYMUX : X_INV
    port map (
      I => Ucore_Ufunc_doneflag,
      O => Ucore_Ufunc_imageloaded_fast_BYMUXNOT
    );
  Ucore_Ufunc_imageloaded_fast_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_imageloaded_fast_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp2_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp2_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un1_rst_3_490 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_next_write_data37_1,
      ADR1 => Ucore_Ufunc_N_249,
      ADR2 => Ucore_Ufunc_un1_temp2_1,
      ADR3 => sw1_p174_c,
      O => Ucore_Ufunc_state_2_FROM
    );
  Ucore_Ufunc_N_30_i_491 : X_LUT4
    generic map(
      INIT => X"FFA2"
    )
    port map (
      ADR0 => sw1_p174_c,
      ADR1 => Ucore_Ufunc_N_244,
      ADR2 => Ucore_Ufunc_next_write_data40,
      ADR3 => Ucore_Ufunc_un1_rst_3,
      O => Ucore_Ufunc_N_30_i
    );
  Ucore_Ufunc_state_2_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_state_2_FROM,
      O => Ucore_Ufunc_un1_rst_3
    );
  Ucore_Ufunc_un1_rst_4_492 : X_LUT4
    generic map(
      INIT => X"A8A0"
    )
    port map (
      ADR0 => sw1_p174_c,
      ADR1 => Ucore_Ufunc_next_write_data39,
      ADR2 => Ucore_Ufunc_next_write_data38,
      ADR3 => Ucore_Ufunc_next_state36,
      O => Ucore_Ufunc_state_1_FROM
    );
  Ucore_Ufunc_N_29_i_493 : X_LUT4
    generic map(
      INIT => X"FFC4"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_244,
      ADR1 => sw1_p174_c,
      ADR2 => Ucore_Ufunc_un1_next_write_data37_5_n,
      ADR3 => Ucore_Ufunc_un1_rst_4,
      O => Ucore_Ufunc_N_29_i
    );
  Ucore_Ufunc_state_1_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_state_1_FROM,
      O => Ucore_Ufunc_un1_rst_4
    );
  Ucore_Uusb_CLK24I_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_CLK24I,
      O => Ucore_Uusb_CLK24I_BYMUXNOT
    );
  Ucore_Uusb_CLK24I_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_CLK24I_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ie_0_a2_0 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state_0_rep1,
      ADR2 => Ucore_Ufunc_resize_state_fast_2_Q,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_N_500_FROM
    );
  Ucore_Ufunc_ie_0_a2 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state_2_rep1,
      ADR2 => Ucore_Ufunc_resize_state_0_rep1,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_N_500_GROM
    );
  Ucore_Ufunc_N_500_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_500_FROM,
      O => Ucore_Ufunc_N_500
    );
  Ucore_Ufunc_N_500_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_500_GROM,
      O => Ucore_Ufunc_resize_doWrite34
    );
  Ucore_Ufunc_nextresize_state_enl_i_m2_0_Q : X_LUT4
    generic map(
      INIT => X"0589"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_resize_state(2),
      ADR3 => Ucore_Ufunc_resize_state(0),
      O => Ucore_Ufunc_N_438_FROM
    );
  Ucore_Ufunc_resize_doWrite34_1_0_o2 : X_LUT4
    generic map(
      INIT => X"5F5F"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state_0_rep1,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => VCC,
      O => Ucore_Ufunc_N_438_GROM
    );
  Ucore_Ufunc_N_438_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_438_FROM,
      O => Ucore_Ufunc_N_438
    );
  Ucore_Ufunc_N_438_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_438_GROM,
      O => Ucore_Ufunc_N_429
    );
  Ucore_Ufunc_imageloaded_rep1_BYMUX : X_INV
    port map (
      I => Ucore_Ufunc_doneflag,
      O => Ucore_Ufunc_imageloaded_rep1_BYMUXNOT
    );
  Ucore_Ufunc_imageloaded_rep1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_imageloaded_rep1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_BUS1610_4_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(3),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_4_FFY_RST,
      O => Ucore_Uusb_BUS1610_3_Q
    );
  Ucore_Ufunc_imageloaded_BYMUX : X_INV
    port map (
      I => Ucore_Ufunc_doneflag,
      O => Ucore_Ufunc_imageloaded_BYMUXNOT
    );
  Ucore_Ufunc_imageloaded_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_imageloaded_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_pidreg_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N15,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_offset_5_sn_m2_i_a2 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      ADR1 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n,
      ADR2 => Ucore_Ufunc_addr_offset_5_sn_m2_i_a2_1,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_1_1_0,
      O => Ucore_Ufunc_addr_offset_18_FROM
    );
  Ucore_Ufunc_addr_offset_5_18_Q : X_LUT4
    generic map(
      INIT => X"C088"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_53,
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_N_70,
      ADR3 => Ucore_Ufunc_N_501,
      O => Ucore_Ufunc_addr_offset_5(18)
    );
  Ucore_Ufunc_addr_offset_18_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_addr_offset_18_FROM,
      O => Ucore_Ufunc_N_501
    );
  Ucore_Ufunc_addr_offset_18_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_addr_offset_18_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_next_write_data37_1_494 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Ufunc_state(1),
      ADR1 => Ucore_Ufunc_state(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_next_write_data37_1_GROM
    );
  Ucore_Ufunc_next_write_data37_1_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_next_write_data37_1_GROM,
      O => Ucore_Ufunc_next_write_data37_1
    );
  g0_1_a2_2_495 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => I_10_n_0,
      ADR1 => Ucore_Ufunc_state(2),
      ADR2 => Ucore_Ufunc_state(0),
      ADR3 => Ucore_Ufunc_state(1),
      O => g0_1_a2_2_FROM
    );
  g0_1_a2 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => I_10_n_1,
      ADR1 => I_10_n,
      ADR2 => g0_1_a2_2,
      ADR3 => Ucore_Ufunc_next_state36,
      O => g0_1_a2_2_GROM
    );
  g0_1_a2_2_XUSED : X_BUF
    port map (
      I => g0_1_a2_2_FROM,
      O => g0_1_a2_2
    );
  g0_1_a2_2_YUSED : X_BUF
    port map (
      I => g0_1_a2_2_GROM,
      O => Ucore_Ufunc_N_240_1
    );
  Ucore_Ufunc_un37_nextresize_statelto4 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un4_nextc_s_4_n,
      ADR1 => Ucore_Ufunc_un4_nextc_s_1_n,
      ADR2 => Ucore_Ufunc_un4_nextc_s_3_n,
      ADR3 => Ucore_Ufunc_un4_nextc_s_2_n,
      O => Ucore_Ufunc_N_220_GROM
    );
  Ucore_Ufunc_N_220_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_220_GROM,
      O => Ucore_Ufunc_N_220
    );
  Ucore_Uusb_BUS1610_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_15_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(15),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_15_FFY_RST,
      O => Ucore_Uusb_BUS1610_15_Q
    );
  g0_1_L1 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_temp2(15),
      ADR1 => Ucore_Ufunc_temp2(14),
      ADR2 => Ucore_Ufunc_temp2(6),
      ADR3 => Ucore_Ufunc_temp2(7),
      O => g0_1_L1_n_GROM
    );
  g0_1_L1_n_YUSED : X_BUF
    port map (
      I => g0_1_L1_n_GROM,
      O => g0_1_L1_n
    );
  Ucore_Uusb_Uuc_Uctrl_INI_LOGIC_ZERO_496 : X_ZERO
    port map (
      O => Ucore_Uusb_Uuc_Uctrl_INI_LOGIC_ZERO
    );
  Ucore_Uusb_Uuc_Uctrl_INI_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_INI_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_resize_doWrite_0_a2_1 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_resize_state_fast_0_Q,
      O => Ucore_Ufunc_resize_doWrite_1_FROM
    );
  Ucore_Ufunc_resize_doWrite_0_a2 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state_2_rep1,
      ADR1 => Ucore_Ufunc_ram_canRead,
      ADR2 => Ucore_Ufunc_resize_state(3),
      ADR3 => Ucore_Ufunc_resize_doWrite_1,
      O => Ucore_Ufunc_resize_doWrite_1_GROM
    );
  Ucore_Ufunc_resize_doWrite_1_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doWrite_1_FROM,
      O => Ucore_Ufunc_resize_doWrite_1
    );
  Ucore_Ufunc_resize_doWrite_1_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_resize_doWrite_1_GROM,
      O => Ucore_Ufunc_resize_doWrite
    );
  g0_0_a2 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_high_temp2_fast(5),
      ADR1 => Ucore_Ufunc_high_temp2_fast(4),
      ADR2 => Ucore_Ufunc_high_temp2_fast(1),
      ADR3 => Ucore_Ufunc_high_temp2_fast(0),
      O => N_112_FROM
    );
  g0_0_a2_x : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => Ucore_Ufunc_high_temp2_fast(5),
      ADR1 => Ucore_Ufunc_high_temp2_fast(1),
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_high_temp2_fast(4),
      O => N_112_GROM
    );
  N_112_XUSED : X_BUF
    port map (
      I => N_112_FROM,
      O => N_112
    );
  N_112_YUSED : X_BUF
    port map (
      I => N_112_GROM,
      O => g0_0_a2_x_n
    );
  sr_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sr_3_SRMUX_OUTPUTNOT
    );
  sr_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sr_5_SRMUX_OUTPUTNOT
    );
  Ucore_din_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_11_SRMUX_OUTPUTNOT
    );
  sr_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sr_6_SRMUX_OUTPUTNOT
    );
  Ucore_dout_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_dout_15_SRMUX_OUTPUTNOT
    );
  Ucore_din_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_0 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_state_fast_2_Q,
      ADR2 => Ucore_Ufunc_resize_state_0_rep1,
      ADR3 => Ucore_Ufunc_resize_state(1),
      O => Ucore_Ufunc_N_520_FROM
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_2_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_3_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR3 => Ucore_Ufunc_N_520,
      O => Ucore_Ufunc_N_520_GROM
    );
  Ucore_Ufunc_N_520_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_520_FROM,
      O => Ucore_Ufunc_N_520
    );
  Ucore_Ufunc_N_520_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_520_GROM,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L1_n
    );
  Ucore_Uusb_C3000 : X_LUT4
    generic map(
      INIT => X"AA26"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR2 => Ucore_Uusb_syn6629,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      O => Ucore_Uusb_syn7870_FROM
    );
  Ucore_Uusb_C2996 : X_LUT4
    generic map(
      INIT => X"0ACE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13,
      ADR3 => Ucore_Uusb_syn7870,
      O => Ucore_Uusb_syn7870_GROM
    );
  Ucore_Uusb_syn7870_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7870_FROM,
      O => Ucore_Uusb_syn7870
    );
  Ucore_Uusb_syn7870_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7870_GROM,
      O => Ucore_Uusb_syn7877
    );
  Ucore_Uusb_C3010 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(0),
      O => Ucore_Uusb_Uusb_Usie_NET1035_FROM
    );
  Ucore_Uusb_C2998 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5330,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C27_N5
    );
  Ucore_Uusb_Uusb_Usie_NET1035_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_NET1035_FROM,
      O => Ucore_Uusb_syn5330
    );
  Ucore_Uusb_Uusb_Usie_NET1035_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_NET1035_SRMUX_OUTPUTNOT
    );
  Ucore_din_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3003 : X_LUT4
    generic map(
      INIT => X"E000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C1461,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR2 => Ucore_Uusb_syn28128,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_FROM
    );
  Ucore_Uusb_C3002 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C348,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C603_C6,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_GROM
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_FROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6_GROM,
      O => Ucore_Uusb_syn28154
    );
  Ucore_Ufunc_un1_resize_doWrite36_4_8_0_a2 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_7_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_5_n,
      ADR2 => Ucore_Ufunc_un1_s_cur_oldRow_s_6_n,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_4_n,
      O => Ucore_Ufunc_un1_resize_doWrite36_2_8_FROM
    );
  Ucore_Ufunc_addr_offset_5_1_18_Q : X_LUT4
    generic map(
      INIT => X"D8F0"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_1_n,
      ADR1 => Ucore_Ufunc_un9_nextaddr_offset_s_14_n,
      ADR2 => Ucore_Ufunc_un19_nextaddr_offset_s_13_n,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite36_2_8,
      O => Ucore_Ufunc_un1_resize_doWrite36_2_8_GROM
    );
  Ucore_Ufunc_un1_resize_doWrite36_2_8_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_2_8_FROM,
      O => Ucore_Ufunc_un1_resize_doWrite36_2_8
    );
  Ucore_Ufunc_un1_resize_doWrite36_2_8_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_2_8_GROM,
      O => Ucore_Ufunc_N_70
    );
  Ucore_Ufunc_sram_presstate_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_sram_presstate_2_SRMUX_OUTPUTNOT
    );
  sl_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sl_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_SRMUX_OUTPUTNOT
    );
  sl_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sl_3_SRMUX_OUTPUTNOT
    );
  sl_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sl_5_SRMUX_OUTPUTNOT
    );
  sl_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sl_6_SRMUX_OUTPUTNOT
    );
  Ucore_dout_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_dout_7_SRMUX_OUTPUTNOT
    );
  sr_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => sr_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_SRMUX_OUTPUTNOT
    );
  Ucore_din_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_1_SRMUX_OUTPUTNOT
    );
  Ucore_din_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_SRMUX_OUTPUTNOT
    );
  Ucore_din_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_SRMUX_OUTPUTNOT
    );
  Ucore_din_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_SRMUX_OUTPUTNOT
    );
  Ucore_din_9_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_din_9_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_11_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_11_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_13_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_13_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_temp1_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_temp1_15_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un1_rst_7_i_497 : X_LUT4
    generic map(
      INIT => X"F733"
    )
    port map (
      ADR0 => Ucore_Ufunc_next_write_data37,
      ADR1 => sw1_p174_c,
      ADR2 => Ucore_Ufunc_un1_next_write_data26_2_O,
      ADR3 => Ucore_Ufunc_un1_next_write_data42_4_1,
      O => Ucore_Ufunc_un1_rst_7_i_GROM
    );
  Ucore_Ufunc_un1_rst_7_i_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_rst_7_i_GROM,
      O => Ucore_Ufunc_un1_rst_7_i
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => Ucore_Ufunc_un1_s_cur_oldRow_s_11_n,
      ADR1 => Ucore_Ufunc_un1_s_cur_oldRow_s_9_n,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un1_s_cur_oldRow_s_10_n,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n_GROM
    );
  Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n_GROM,
      O => Ucore_Ufunc_un1_resize_doWrite36_3_0_a2_L3_n
    );
  Ucore_Uusb_Uuc_AO_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_AO_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_AO_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_AO_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_AO_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_AO_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_AO_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_AO_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_sram_canwrite_0_a2 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => Ucore_Ufunc_presstate_1_Q,
      ADR1 => VCC,
      ADR2 => Ucore_Ufunc_presstate_3_Q,
      ADR3 => VCC,
      O => Ucore_Ufunc_ram_canRead_FROM
    );
  Ucore_Ufunc_nextresize_state_enl_0_1_18 : X_LUT4
    generic map(
      INIT => X"8802"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_ram_canRead,
      ADR3 => Ucore_Ufunc_resize_state_2_rep1,
      O => Ucore_Ufunc_ram_canRead_GROM
    );
  Ucore_Ufunc_ram_canRead_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_canRead_FROM,
      O => Ucore_Ufunc_ram_canRead
    );
  Ucore_Ufunc_ram_canRead_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ram_canRead_GROM,
      O => Ucore_Ufunc_nextresize_state_enl_0_1_18_n
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_CKINV : X_INV
    port map (
      I => clk48,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_CKMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_un1_rst_2_0_a2_0_498 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(1),
      ADR1 => Ucore_Ufunc_resize_state_0_rep1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Ufunc_un1_rst_2_0_a2_0_FROM
    );
  Ucore_Ufunc_un1_rst_2_0_a2 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => sw1_p174_c,
      ADR1 => Ucore_Ufunc_resize_state(3),
      ADR2 => Ucore_Ufunc_resize_state(2),
      ADR3 => Ucore_Ufunc_un1_rst_2_0_a2_0,
      O => Ucore_Ufunc_un1_rst_2_0_a2_0_GROM
    );
  Ucore_Ufunc_un1_rst_2_0_a2_0_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_rst_2_0_a2_0_FROM,
      O => Ucore_Ufunc_un1_rst_2_0_a2_0
    );
  Ucore_Ufunc_un1_rst_2_0_a2_0_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_rst_2_0_a2_0_GROM,
      O => Ucore_Ufunc_un1_rst_2_0_a2_n
    );
  Ucore_Ufunc_un1_next_write_data37_8_16 : X_LUT4
    generic map(
      INIT => X"F0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_un1_temp2_3,
      ADR2 => Ucore_Ufunc_N_249,
      ADR3 => Ucore_Ufunc_un1_temp2_1,
      O => Ucore_Ufunc_un1_next_write_data37_8_16_n_GROM
    );
  Ucore_Ufunc_un1_next_write_data37_8_16_n_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_next_write_data37_8_16_n_GROM,
      O => Ucore_Ufunc_un1_next_write_data37_8_16_n
    );
  Ucore_Uusb_C3100 : X_LUT4
    generic map(
      INIT => X"E4A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5299,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C576,
      ADR3 => Ucore_Uusb_syn5311,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FROM
    );
  Ucore_Uusb_C3093 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C705,
      ADR1 => Ucore_Uusb_syn7362,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C598,
      ADR3 => Ucore_Uusb_syn7544,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2732
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FROM,
      O => Ucore_Uusb_syn7544
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2999 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR3 => Ucore_Uusb_syn7870,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_FROM
    );
  Ucore_Uusb_C3020 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C355
    );
  Ucore_Uusb_C2997 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_FROM
    );
  Ucore_Uusb_C3012 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_cell6,
      ADR1 => Ucore_Uusb_syn28150,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13_GROM,
      O => Ucore_Uusb_syn5165
    );
  Ucore_Uusb_C3432 : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C492_FROM
    );
  Ucore_Uusb_C3004 : X_LUT4
    generic map(
      INIT => X"CC88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_stall_en,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C492_GROM
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C492_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C492_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C492
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C492_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C492_GROM,
      O => Ucore_Uusb_syn28128
    );
  Ucore_Uusb_C3429 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_NET1024,
      O => Ucore_Uusb_Uusb_in_trac_0_FROM
    );
  Ucore_Uusb_C3005 : X_LUT4
    generic map(
      INIT => X"5F57"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      ADR1 => Ucore_Uusb_syn6653,
      ADR2 => Ucore_Uusb_syn5458,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      O => Ucore_Uusb_Uusb_in_trac_0_GROM
    );
  Ucore_Uusb_Uusb_in_trac_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_in_trac_0_FROM,
      O => Ucore_Uusb_Uusb_in_trac(0)
    );
  Ucore_Uusb_Uusb_in_trac_0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_in_trac_0_GROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C603_C6
    );
  Ucore_Uusb_C3014 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_BUS1153(9),
      ADR1 => Ucore_Uusb_syn28144,
      ADR2 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      ADR3 => Ucore_Uusb_syn28141,
      O => Ucore_Uusb_syn28147_FROM
    );
  Ucore_Uusb_C3013 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7799,
      ADR1 => Ucore_Uusb_syn28142,
      ADR2 => Ucore_Uusb_syn28143,
      ADR3 => Ucore_Uusb_syn28147,
      O => Ucore_Uusb_syn28147_GROM
    );
  Ucore_Uusb_syn28147_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28147_FROM,
      O => Ucore_Uusb_syn28147
    );
  Ucore_Uusb_syn28147_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28147_GROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_cell6
    );
  Ucore_Uusb_C3006 : X_LUT4
    generic map(
      INIT => X"F4F0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_S_62_cell0,
      ADR1 => Ucore_Uusb_syn7852,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C363,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C348,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FROM
    );
  Ucore_Uusb_C2993 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn28193,
      ADR3 => Ucore_Uusb_syn7855,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N27
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FROM,
      O => Ucore_Uusb_syn7855
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3056 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_Q,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      O => Ucore_Uusb_syn28034_FROM
    );
  Ucore_Uusb_C3031 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(0),
      O => Ucore_Uusb_syn28034_GROM
    );
  Ucore_Uusb_syn28034_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28034_FROM,
      O => Ucore_Uusb_syn28034
    );
  Ucore_Uusb_syn28034_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28034_GROM,
      O => Ucore_Uusb_syn28106
    );
  Ucore_Uusb_C3015 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_BUS1153(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_BUS1153(1),
      O => Ucore_Uusb_syn28144_GROM
    );
  Ucore_Uusb_syn28144_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28144_GROM,
      O => Ucore_Uusb_syn28144
    );
  Ucore_Uusb_C3064 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_Q,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn7677_FROM
    );
  Ucore_Uusb_C3040 : X_LUT4
    generic map(
      INIT => X"CE0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(2),
      O => Ucore_Uusb_syn7677_GROM
    );
  Ucore_Uusb_syn7677_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7677_FROM,
      O => Ucore_Uusb_syn7677
    );
  Ucore_Uusb_syn7677_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7677_GROM,
      O => Ucore_Uusb_syn28078
    );
  Ucore_Uusb_C3120 : X_LUT4
    generic map(
      INIT => X"EE00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5326,
      ADR1 => Ucore_Uusb_syn5327,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5302,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FROM
    );
  Ucore_Uusb_C3083 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N311,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N59,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C640,
      ADR3 => Ucore_Uusb_syn7394,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N356
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FROM,
      O => Ucore_Uusb_syn7394
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3104 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27929,
      ADR1 => Ucore_Uusb_syn5344,
      ADR2 => Ucore_Uusb_syn27928,
      ADR3 => VCC,
      O => Ucore_Uusb_syn7527_FROM
    );
  Ucore_Uusb_C3103 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C642,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C650,
      ADR3 => Ucore_Uusb_syn7527,
      O => Ucore_Uusb_syn7527_GROM
    );
  Ucore_Uusb_syn7527_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7527_FROM,
      O => Ucore_Uusb_syn7527
    );
  Ucore_Uusb_syn7527_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7527_GROM,
      O => Ucore_Uusb_syn7532
    );
  Ucore_Uusb_C3016 : X_LUT4
    generic map(
      INIT => X"0A05"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_BUS1153(10),
      ADR3 => Ucore_Uusb_Uusb_Usie_BUS1153(0),
      O => Ucore_Uusb_syn28141_GROM
    );
  Ucore_Uusb_syn28141_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28141_GROM,
      O => Ucore_Uusb_syn28141
    );
  Ucore_Uusb_C3008 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(3),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      O => Ucore_Uusb_syn7848_FROM
    );
  Ucore_Uusb_C2942 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C286,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR3 => Ucore_Uusb_syn7848,
      O => Ucore_Uusb_syn7848_GROM
    );
  Ucore_Uusb_syn7848_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7848_FROM,
      O => Ucore_Uusb_syn7848
    );
  Ucore_Uusb_syn7848_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7848_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9
    );
  Ucore_Uusb_C3201 : X_LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5328,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_syn5300,
      ADR3 => Ucore_Uusb_syn5311,
      O => Ucore_Uusb_syn27750_FROM
    );
  Ucore_Uusb_C3200 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5311,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5313,
      ADR3 => Ucore_Uusb_syn27750,
      O => Ucore_Uusb_syn27750_GROM
    );
  Ucore_Uusb_syn27750_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27750_FROM,
      O => Ucore_Uusb_syn27750
    );
  Ucore_Uusb_syn27750_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27750_GROM,
      O => Ucore_Uusb_syn27752
    );
  Ucore_Uusb_C3223 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_INI,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR2 => Ucore_Uusb_syn7197,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_FROM
    );
  Ucore_Uusb_C3041 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(1),
      ADR3 => Ucore_Uusb_syn7724,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3_GROM,
      O => Ucore_Uusb_syn7727
    );
  Ucore_Uusb_C3017 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_BUS1153(4),
      ADR1 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(6),
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(4),
      ADR3 => Ucore_Uusb_Uusb_Usie_BUS1153(6),
      O => Ucore_Uusb_syn28143_GROM
    );
  Ucore_Uusb_syn28143_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28143_GROM,
      O => Ucore_Uusb_syn28143
    );
  Ucore_Uusb_C3009 : X_LUT4
    generic map(
      INIT => X"CC80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Uepdec_cell6,
      ADR2 => Ucore_Uusb_syn28150,
      ADR3 => Ucore_Uusb_syn5330,
      O => Ucore_Uusb_syn7842_FROM
    );
  Ucore_Uusb_C3007 : X_LUT4
    generic map(
      INIT => X"0FCF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn7848,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2,
      ADR3 => Ucore_Uusb_syn7842,
      O => Ucore_Uusb_syn7842_GROM
    );
  Ucore_Uusb_syn7842_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7842_FROM,
      O => Ucore_Uusb_syn7842
    );
  Ucore_Uusb_syn7842_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7842_GROM,
      O => Ucore_Uusb_syn7852
    );
  Ucore_Uusb_C3202 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      O => Ucore_Uusb_syn5311_FROM
    );
  Ucore_Uusb_C3126 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5299,
      ADR3 => Ucore_Uusb_syn5311,
      O => Ucore_Uusb_syn5311_GROM
    );
  Ucore_Uusb_syn5311_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5311_FROM,
      O => Ucore_Uusb_syn5311
    );
  Ucore_Uusb_syn5311_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5311_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C556
    );
  Ucore_Uusb_C3236 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5336_FROM
    );
  Ucore_Uusb_C3050 : X_LUT4
    generic map(
      INIT => X"CE0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(0),
      O => Ucore_Uusb_syn5336_GROM
    );
  Ucore_Uusb_syn5336_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5336_FROM,
      O => Ucore_Uusb_syn5336
    );
  Ucore_Uusb_syn5336_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5336_GROM,
      O => Ucore_Uusb_syn28047
    );
  Ucore_Uusb_C3042 : X_LUT4
    generic map(
      INIT => X"8A80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      O => Ucore_Uusb_syn7724_FROM
    );
  Ucore_Uusb_C3029 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_Q,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR3 => Ucore_Uusb_syn7724,
      O => Ucore_Uusb_syn7724_GROM
    );
  Ucore_Uusb_syn7724_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7724_FROM,
      O => Ucore_Uusb_syn7724
    );
  Ucore_Uusb_syn7724_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7724_GROM,
      O => Ucore_Uusb_syn28107
    );
  Ucore_Uusb_C3034 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28090,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(1),
      ADR3 => Ucore_Uusb_syn7727,
      O => Ucore_Uusb_Uuc_DSEL_1_FROM
    );
  Ucore_Uusb_C3033 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR2 => Ucore_Uusb_syn28089,
      ADR3 => Ucore_Uusb_syn28093,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N48
    );
  Ucore_Uusb_Uuc_DSEL_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DSEL_1_FROM,
      O => Ucore_Uusb_syn28093
    );
  Ucore_Uusb_C3026 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(3),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(1),
      ADR3 => VCC,
      O => Ucore_Uusb_syn28150_FROM
    );
  Ucore_Uusb_C3011 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_cell6,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid2,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(2),
      ADR3 => Ucore_Uusb_syn28150,
      O => Ucore_Uusb_syn28150_GROM
    );
  Ucore_Uusb_syn28150_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28150_FROM,
      O => Ucore_Uusb_syn28150
    );
  Ucore_Uusb_syn28150_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28150_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_S_62_cell0
    );
  Ucore_Uusb_C3018 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(3),
      ADR1 => Ucore_Uusb_Uusb_Usie_BUS1153(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(5),
      ADR3 => Ucore_Uusb_Uusb_Usie_BUS1153(5),
      O => Ucore_Uusb_syn28142_GROM
    );
  Ucore_Uusb_syn28142_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28142_GROM,
      O => Ucore_Uusb_syn28142
    );
  Ucore_Uusb_C3203 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C784,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C780,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C788,
      O => Ucore_Uusb_syn27751_GROM
    );
  Ucore_Uusb_syn27751_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27751_GROM,
      O => Ucore_Uusb_syn27751
    );
  Ucore_Uusb_C3131 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5300,
      ADR1 => Ucore_Uusb_syn7304,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn5290,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FROM
    );
  Ucore_Uusb_C3079 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7321,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C558,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N311,
      ADR3 => Ucore_Uusb_syn7441,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2085
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FROM,
      O => Ucore_Uusb_syn7441
    );
  Ucore_Uusb_C3123 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C576,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FROM
    );
  Ucore_Uusb_C3111 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C746,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn7362,
      ADR3 => Ucore_Uusb_syn7473,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2775
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FROM,
      O => Ucore_Uusb_syn7473
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3135 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_syn5300,
      ADR2 => Ucore_Uusb_syn5290,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C656_FROM
    );
  Ucore_Uusb_C3107 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_syn5300,
      ADR2 => Ucore_Uusb_syn5290,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C656_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C656_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C656_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C656
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C656_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C656_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C654
    );
  Ucore_Uusb_C3220 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      O => Ucore_Uusb_syn5312_FROM
    );
  Ucore_Uusb_C3198 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5300,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5312,
      O => Ucore_Uusb_syn5312_GROM
    );
  Ucore_Uusb_syn5312_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5312_FROM,
      O => Ucore_Uusb_syn5312
    );
  Ucore_Uusb_syn5312_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5312_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C568
    );
  Ucore_Uusb_C3204 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_syn5328,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FROM
    );
  Ucore_Uusb_C3191 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C780,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C780
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_N59
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3140 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR1 => Ucore_Uusb_syn5295,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C598_FROM
    );
  Ucore_Uusb_C3106 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C597,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C664,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C598,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C598_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C598_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C598_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C598
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C598_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C598_GROM,
      O => Ucore_Uusb_syn27928
    );
  Ucore_Uusb_C3124 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C700,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FROM
    );
  Ucore_Uusb_C3110 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5327,
      ADR1 => Ucore_Uusb_syn5302,
      ADR2 => Ucore_Uusb_syn5326,
      ADR3 => Ucore_Uusb_syn5249,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N179
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FROM,
      O => Ucore_Uusb_syn5249
    );
  Ucore_Uusb_C3057 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      O => Ucore_Uusb_syn28033_FROM
    );
  Ucore_Uusb_C3060 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      O => Ucore_Uusb_syn28033_GROM
    );
  Ucore_Uusb_syn28033_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28033_FROM,
      O => Ucore_Uusb_syn28033
    );
  Ucore_Uusb_syn28033_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28033_GROM,
      O => Ucore_Uusb_syn28023
    );
  Ucore_Uusb_C3513 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      O => Ucore_Uusb_syn6430_FROM
    );
  Ucore_Uusb_C3052 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_0_Q,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      O => Ucore_Uusb_syn6430_GROM
    );
  Ucore_Uusb_syn6430_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6430_FROM,
      O => Ucore_Uusb_syn6430
    );
  Ucore_Uusb_syn6430_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6430_GROM,
      O => Ucore_Uusb_syn28046
    );
  Ucore_Uusb_C3028 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR1 => Ucore_Uusb_syn28107,
      ADR2 => Ucore_Uusb_syn28104,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      O => Ucore_Uusb_Uuc_DSEL_0_FROM
    );
  Ucore_Uusb_C3027 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28106,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn28105,
      ADR3 => Ucore_Uusb_syn28110,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N29
    );
  Ucore_Uusb_Uuc_DSEL_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DSEL_0_FROM,
      O => Ucore_Uusb_syn28110
    );
  g0_L1 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_high_temp2_fast(5),
      ADR1 => Ucore_Ufunc_high_temp2_fast(0),
      ADR2 => Ucore_Ufunc_high_temp2_fast(4),
      ADR3 => Ucore_Ufunc_high_temp2_fast(1),
      O => g0_L1_n_GROM
    );
  g0_L1_n_YUSED : X_BUF
    port map (
      I => g0_L1_n_GROM,
      O => g0_L1_n
    );
  Ucore_Uusb_C3214 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      O => Ucore_Uusb_syn5162_FROM
    );
  Ucore_Uusb_C3221 : X_LUT4
    generic map(
      INIT => X"0044"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      O => Ucore_Uusb_syn5162_GROM
    );
  Ucore_Uusb_syn5162_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5162_FROM,
      O => Ucore_Uusb_syn5162
    );
  Ucore_Uusb_syn5162_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5162_GROM,
      O => Ucore_Uusb_syn5163
    );
  Ucore_Uusb_C3213 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR1 => Ucore_Uusb_syn5162,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5302_FROM
    );
  Ucore_Uusb_C3195 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn5302,
      O => Ucore_Uusb_syn5302_GROM
    );
  Ucore_Uusb_syn5302_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5302_FROM,
      O => Ucore_Uusb_syn5302
    );
  Ucore_Uusb_syn5302_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5302_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C584
    );
  Ucore_Uusb_C3205 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      O => Ucore_Uusb_syn5328_FROM
    );
  Ucore_Uusb_C3158 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5312,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5328,
      O => Ucore_Uusb_syn5328_GROM
    );
  Ucore_Uusb_syn5328_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5328_FROM,
      O => Ucore_Uusb_syn5328
    );
  Ucore_Uusb_syn5328_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5328_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C597
    );
  Ucore_Uusb_C3189 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5299,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn5295,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C640_FROM
    );
  Ucore_Uusb_C3141 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5295,
      ADR2 => Ucore_Uusb_syn5299,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C640_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C640_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C640_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C640
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C640_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C640_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C642
    );
  Ucore_Uusb_C3039 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(2),
      O => Ucore_Uusb_syn28077_FROM
    );
  Ucore_Uusb_C3045 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456,
      O => Ucore_Uusb_syn28077_GROM
    );
  Ucore_Uusb_syn28077_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28077_FROM,
      O => Ucore_Uusb_syn28077
    );
  Ucore_Uusb_syn28077_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28077_GROM,
      O => Ucore_Uusb_syn28061
    );
  Ucore_Uusb_C3308 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C611,
      ADR1 => Ucore_Uusb_syn23519,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C617,
      ADR3 => Ucore_Uusb_syn6992,
      O => Ucore_Uusb_syn27530_FROM
    );
  Ucore_Uusb_C3310 : X_LUT4
    generic map(
      INIT => X"A8A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(7),
      ADR1 => Ucore_Uusb_syn23519,
      ADR2 => Ucore_Uusb_syn6920,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C661,
      O => Ucore_Uusb_syn27530_GROM
    );
  Ucore_Uusb_syn27530_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27530_FROM,
      O => Ucore_Uusb_syn27530
    );
  Ucore_Uusb_syn27530_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27530_GROM,
      O => Ucore_Uusb_syn6989
    );
  Ucore_Uusb_C3230 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR2 => Ucore_Uusb_syn5336,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_4_FROM
    );
  Ucore_Uusb_C3229 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      ADR2 => Ucore_Uusb_syn21091,
      ADR3 => Ucore_Uusb_syn27684,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N51
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP_4_FROM,
      O => Ucore_Uusb_syn27684
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3151 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5299,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C700_FROM
    );
  Ucore_Uusb_C3206 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_syn5299,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C700_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C700_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C700_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C700
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C700_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C700_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C784
    );
  Ucore_Uusb_C3142 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C702,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C650,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FROM
    );
  Ucore_Uusb_C3127 : X_LUT4
    generic map(
      INIT => X"FFF4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR3 => Ucore_Uusb_syn7414,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FROM,
      O => Ucore_Uusb_syn7414
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1697
    );
  Ucore_Uusb_C3166 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_syn5301,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C702_FROM
    );
  Ucore_Uusb_C3134 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5301,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C702_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C702_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C702_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C702
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C702_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C702_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C580
    );
  Ucore_Uusb_C3062 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      O => Ucore_Uusb_Uuc_ALUOP_3_FROM
    );
  Ucore_Uusb_C3061 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7677,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR3 => Ucore_Uusb_syn28016,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N74
    );
  Ucore_Uusb_Uuc_ALUOP_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP_3_FROM,
      O => Ucore_Uusb_syn28016
    );
  Ucore_Uusb_C3038 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456,
      ADR1 => Ucore_Uusb_syn28077,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(2),
      O => Ucore_Uusb_Uuc_DSEL_2_FROM
    );
  Ucore_Uusb_C3037 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7727,
      ADR1 => Ucore_Uusb_syn7706,
      ADR2 => Ucore_Uusb_syn28078,
      ADR3 => Ucore_Uusb_syn28080,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N68
    );
  Ucore_Uusb_Uuc_DSEL_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DSEL_2_FROM,
      O => Ucore_Uusb_syn28080
    );
  Ucore_Uusb_C3738 : X_LUT4
    generic map(
      INIT => X"8488"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26076,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(7),
      O => Ucore_Uusb_syn5903_FROM
    );
  Ucore_Uusb_C3311 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6957,
      O => Ucore_Uusb_syn5903_GROM
    );
  Ucore_Uusb_syn5903_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5903_FROM,
      O => Ucore_Uusb_syn5903
    );
  Ucore_Uusb_syn5903_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5903_GROM,
      O => Ucore_Uusb_syn6991
    );
  Ucore_Uusb_C3303 : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6472,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn6519,
      ADR3 => Ucore_Uusb_syn5317,
      O => Ucore_Uusb_syn27544_FROM
    );
  Ucore_Uusb_C3302 : X_LUT4
    generic map(
      INIT => X"F2F3"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5315,
      ADR1 => Ucore_Uusb_syn6779,
      ADR2 => Ucore_Uusb_syn27544,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_syn27544_GROM
    );
  Ucore_Uusb_syn27544_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27544_FROM,
      O => Ucore_Uusb_syn27544
    );
  Ucore_Uusb_syn27544_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27544_GROM,
      O => Ucore_Uusb_Uuc_RAWR
    );
  Ucore_Uusb_C3231 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_FROM
    );
  Ucore_Uusb_C3036 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454_GROM,
      O => Ucore_Uusb_syn28089
    );
  Ucore_Uusb_C3190 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      O => Ucore_Uusb_syn5295_FROM
    );
  Ucore_Uusb_C3215 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_syn5313,
      O => Ucore_Uusb_syn5295_GROM
    );
  Ucore_Uusb_syn5295_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5295_FROM,
      O => Ucore_Uusb_syn5295
    );
  Ucore_Uusb_syn5295_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5295_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C806
    );
  Ucore_Uusb_C3207 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      O => Ucore_Uusb_syn5299_FROM
    );
  Ucore_Uusb_C3150 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn5299,
      O => Ucore_Uusb_syn5299_GROM
    );
  Ucore_Uusb_syn5299_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5299_FROM,
      O => Ucore_Uusb_syn5299
    );
  Ucore_Uusb_syn5299_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5299_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C690
    );
  Ucore_Uusb_C3143 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C564,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C758,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn7264,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FROM
    );
  Ucore_Uusb_C3125 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C556,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C702,
      ADR2 => Ucore_Uusb_syn7410,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2214,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FROM,
      O => Ucore_Uusb_syn7410
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2517
    );
  Ucore_Uusb_C3119 : X_LUT4
    generic map(
      INIT => X"FF0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FROM
    );
  Ucore_Uusb_C3118 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7285,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_N59,
      ADR2 => Ucore_Uusb_syn7394,
      ADR3 => Ucore_Uusb_syn7460,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2861
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FROM,
      O => Ucore_Uusb_syn7460
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3055 : X_LUT4
    generic map(
      INIT => X"EECC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(4),
      ADR1 => Ucore_Uusb_syn28034,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      O => Ucore_Uusb_Uuc_ALUOP_1_FROM
    );
  Ucore_Uusb_C3054 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR2 => Ucore_Uusb_syn28033,
      ADR3 => Ucore_Uusb_syn28036,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N41
    );
  Ucore_Uusb_Uuc_ALUOP_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP_1_FROM,
      O => Ucore_Uusb_syn28036
    );
  Ucore_Uusb_C3047 : X_LUT4
    generic map(
      INIT => X"FF55"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      O => Ucore_Uusb_syn7709_FROM
    );
  Ucore_Uusb_C3046 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_Q,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      ADR3 => Ucore_Uusb_syn7709,
      O => Ucore_Uusb_syn7709_GROM
    );
  Ucore_Uusb_syn7709_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7709_FROM,
      O => Ucore_Uusb_syn7709
    );
  Ucore_Uusb_syn7709_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7709_GROM,
      O => Ucore_Uusb_syn28060
    );
  Ucore_Uusb_C3837 : X_LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS1610_14_Q,
      ADR1 => Ucore_Uusb_BUS1610_13_Q,
      ADR2 => Ucore_Uusb_BUS1610_15_Q,
      ADR3 => Ucore_Uusb_BUS1610_12_Q,
      O => Ucore_Uusb_Uglue_N31_FROM
    );
  Ucore_Uusb_C3400 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS1610_13_Q,
      ADR1 => Ucore_Uusb_BUS1610_14_Q,
      ADR2 => Ucore_Uusb_BUS1610_15_Q,
      ADR3 => Ucore_Uusb_BUS1610_12_Q,
      O => Ucore_Uusb_Uglue_N31_GROM
    );
  Ucore_Uusb_Uglue_N31_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_N31_FROM,
      O => Ucore_Uusb_Uglue_N31
    );
  Ucore_Uusb_Uglue_N31_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_N31_GROM,
      O => Ucore_Uusb_Uglue_N33
    );
  Ucore_Uusb_C3469 : X_LUT4
    generic map(
      INIT => X"EDED"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR3 => VCC,
      O => Ucore_Uusb_syn6532_FROM
    );
  Ucore_Uusb_C3304 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C569,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      O => Ucore_Uusb_syn6532_GROM
    );
  Ucore_Uusb_syn6532_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6532_FROM,
      O => Ucore_Uusb_syn6532
    );
  Ucore_Uusb_syn6532_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6532_GROM,
      O => Ucore_Uusb_syn6472
    );
  Ucore_Uusb_C3713 : X_LUT4
    generic map(
      INIT => X"0B53"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_syn5945_FROM
    );
  Ucore_Uusb_C3232 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5945_GROM
    );
  Ucore_Uusb_syn5945_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5945_FROM,
      O => Ucore_Uusb_syn5945
    );
  Ucore_Uusb_syn5945_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5945_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477
    );
  Ucore_Uusb_C3224 : X_LUT4
    generic map(
      INIT => X"000A"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7197,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_INI,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3
    );
  Ucore_Uusb_C3216 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      O => Ucore_Uusb_syn5313_FROM
    );
  Ucore_Uusb_C3210 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_syn5313,
      O => Ucore_Uusb_syn5313_GROM
    );
  Ucore_Uusb_syn5313_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5313_FROM,
      O => Ucore_Uusb_syn5313
    );
  Ucore_Uusb_syn5313_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5313_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C792
    );
  Ucore_Uusb_C3160 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7341,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FROM
    );
  Ucore_Uusb_C3159 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1827,
      ADR3 => Ucore_Uusb_syn27833,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2042
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FROM,
      O => Ucore_Uusb_syn27833
    );
  Ucore_Uusb_C3048 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5539,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454,
      O => Ucore_Uusb_Uuc_DSEL_3_FROM
    );
  Ucore_Uusb_C3043 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28062,
      ADR1 => Ucore_Uusb_syn28061,
      ADR2 => Ucore_Uusb_syn28060,
      ADR3 => Ucore_Uusb_syn7706,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N88
    );
  Ucore_Uusb_Uuc_DSEL_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DSEL_3_FROM,
      O => Ucore_Uusb_syn7706
    );
  Ucore_Uusb_C3233 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_FROM
    );
  Ucore_Uusb_C3035 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481_GROM,
      O => Ucore_Uusb_syn28090
    );
  Ucore_Uusb_C3321 : X_LUT4
    generic map(
      INIT => X"F9F0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26076,
      ADR1 => Ucore_Uusb_syn6957,
      ADR2 => Ucore_Uusb_syn6964,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C690,
      O => Ucore_Uusb_syn27498_FROM
    );
  Ucore_Uusb_C3320 : X_LUT4
    generic map(
      INIT => X"FF0A"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27492,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn23977,
      ADR3 => Ucore_Uusb_syn27498,
      O => Ucore_Uusb_syn27498_GROM
    );
  Ucore_Uusb_syn27498_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27498_FROM,
      O => Ucore_Uusb_syn27498
    );
  Ucore_Uusb_syn27498_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27498_GROM,
      O => Ucore_Uusb_syn27499
    );
  Ucore_Uusb_C3313 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn26082,
      ADR2 => Ucore_Uusb_syn6004,
      ADR3 => Ucore_Uusb_syn27516,
      O => Ucore_Uusb_Uuc_PO_6_FROM
    );
  Ucore_Uusb_C3312 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(6),
      ADR1 => Ucore_Uusb_syn6904,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6981,
      O => Ucore_Uusb_Uuc_Upsw_C0_N12
    );
  Ucore_Uusb_Uuc_PO_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PO_6_FROM,
      O => Ucore_Uusb_syn6981
    );
  Ucore_Uusb_Uuc_PO_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3225 : X_LUT4
    generic map(
      INIT => X"888C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_syn27695,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      O => Ucore_Uusb_syn7197_FROM
    );
  Ucore_Uusb_C3222 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_INI,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C477,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR3 => Ucore_Uusb_syn7197,
      O => Ucore_Uusb_syn7197_GROM
    );
  Ucore_Uusb_syn7197_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7197_FROM,
      O => Ucore_Uusb_syn7197
    );
  Ucore_Uusb_syn7197_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7197_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3
    );
  Ucore_Uusb_C3209 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      O => Ucore_Uusb_syn5300_FROM
    );
  Ucore_Uusb_C3208 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_syn5300,
      O => Ucore_Uusb_syn5300_GROM
    );
  Ucore_Uusb_syn5300_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5300_FROM,
      O => Ucore_Uusb_syn5300
    );
  Ucore_Uusb_syn5300_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5300_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C788
    );
  Ucore_Uusb_C3153 : X_LUT4
    generic map(
      INIT => X"F5F4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C576,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FROM
    );
  Ucore_Uusb_C3152 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1351,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2257,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C597,
      ADR3 => Ucore_Uusb_syn7362,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2388
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FROM,
      O => Ucore_Uusb_syn7362
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3426 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1465_FROM
    );
  Ucore_Uusb_C3410 : X_LUT4
    generic map(
      INIT => X"8C04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_syn5333,
      ADR2 => Ucore_Uusb_Uusb_in_trac(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_setup_en,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1465_GROM
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C1465_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1465_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1465
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C1465_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1465_GROM,
      O => Ucore_Uusb_syn27276
    );
  Ucore_Uusb_C3693 : X_LUT4
    generic map(
      INIT => X"4884"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5736,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C458_C13,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(6),
      O => Ucore_Uusb_syn6023_FROM
    );
  Ucore_Uusb_C3314 : X_LUT4
    generic map(
      INIT => X"F444"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26072,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => Ucore_Uusb_syn6926,
      ADR3 => Ucore_Uusb_Uuc_PO(6),
      O => Ucore_Uusb_syn6023_GROM
    );
  Ucore_Uusb_syn6023_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6023_FROM,
      O => Ucore_Uusb_syn6023
    );
  Ucore_Uusb_syn6023_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6023_GROM,
      O => Ucore_Uusb_syn27516
    );
  Ucore_Uusb_C3533 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_FROM
    );
  Ucore_Uusb_C3234 : X_LUT4
    generic map(
      INIT => X"CFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn27676,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16
    );
  Ucore_Uusb_C3497 : X_LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_FROM
    );
  Ucore_Uusb_C3226 : X_LUT4
    generic map(
      INIT => X"1033"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165_GROM,
      O => Ucore_Uusb_syn27695
    );
  Ucore_Uusb_C3218 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FROM
    );
  Ucore_Uusb_C3217 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5163,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR3 => Ucore_Uusb_syn5326,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FROM,
      O => Ucore_Uusb_syn5326
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_N103
    );
  Ucore_Uusb_C3170 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR1 => Ucore_Uusb_syn5301,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FROM
    );
  Ucore_Uusb_C3109 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C664,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C578,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1480
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C578
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3162 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C650,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C564,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C758,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      O => Ucore_Uusb_syn7335_FROM
    );
  Ucore_Uusb_C3161 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C702,
      ADR1 => Ucore_Uusb_syn5344,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_syn7335,
      O => Ucore_Uusb_syn7335_GROM
    );
  Ucore_Uusb_syn7335_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7335_FROM,
      O => Ucore_Uusb_syn7335
    );
  Ucore_Uusb_syn7335_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7335_GROM,
      O => Ucore_Uusb_syn7341
    );
  Ucore_Uusb_C3066 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      O => Ucore_Uusb_Uuc_ALUOP_4_FROM
    );
  Ucore_Uusb_C3065 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn7644,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn28005,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N90
    );
  Ucore_Uusb_Uuc_ALUOP_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP_4_FROM,
      O => Ucore_Uusb_syn28005
    );
  Ucore_Uusb_C3411 : X_LUT4
    generic map(
      INIT => X"F0E0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_out_en,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_stall_en,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_in_en,
      O => Ucore_Uusb_syn6694_GROM
    );
  Ucore_Uusb_syn6694_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6694_GROM,
      O => Ucore_Uusb_syn6694
    );
  Ucore_Uusb_C3403 : X_LUT4
    generic map(
      INIT => X"FBFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C1465,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_out_en,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C1450,
      ADR3 => Ucore_Uusb_syn6704,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FROM
    );
  Ucore_Uusb_C3402 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C9_C0,
      ADR1 => Ucore_Uusb_syn6707,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C1469,
      ADR3 => Ucore_Uusb_syn27291,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C38_N56
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FROM,
      O => Ucore_Uusb_syn27291
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3331 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C603,
      ADR1 => Ucore_Uusb_syn5913,
      ADR2 => Ucore_Uusb_syn6920,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C661,
      O => Ucore_Uusb_syn6926_FROM
    );
  Ucore_Uusb_C3322 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_PO(2),
      ADR3 => Ucore_Uusb_syn6926,
      O => Ucore_Uusb_syn6926_GROM
    );
  Ucore_Uusb_syn6926_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6926_FROM,
      O => Ucore_Uusb_syn6926
    );
  Ucore_Uusb_syn6926_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6926_GROM,
      O => Ucore_Uusb_syn6964
    );
  Ucore_Uusb_C3307 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn20390,
      ADR1 => Ucore_Uusb_syn27530,
      ADR2 => Ucore_Uusb_syn6989,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C683,
      O => Ucore_Uusb_syn27532_FROM
    );
  Ucore_Uusb_C3306 : X_LUT4
    generic map(
      INIT => X"FFCE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR1 => Ucore_Uusb_syn6991,
      ADR2 => Ucore_Uusb_syn23977,
      ADR3 => Ucore_Uusb_syn27532,
      O => Ucore_Uusb_syn27532_GROM
    );
  Ucore_Uusb_syn27532_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27532_FROM,
      O => Ucore_Uusb_syn27532
    );
  Ucore_Uusb_syn27532_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27532_GROM,
      O => Ucore_Uusb_syn20438
    );
  Ucore_Uusb_C3368 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn21091_FROM
    );
  Ucore_Uusb_C3235 : X_LUT4
    generic map(
      INIT => X"2AFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      O => Ucore_Uusb_syn21091_GROM
    );
  Ucore_Uusb_syn21091_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn21091_FROM,
      O => Ucore_Uusb_syn21091
    );
  Ucore_Uusb_syn21091_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn21091_GROM,
      O => Ucore_Uusb_syn27676
    );
  Ucore_Uusb_C3171 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5290,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn5313,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C664_FROM
    );
  Ucore_Uusb_C3169 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_syn5301,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C664,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C664_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C664_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C664_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C664
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C664_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C664_GROM,
      O => Ucore_Uusb_syn7321
    );
  Ucore_Uusb_C3164 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5295,
      ADR1 => Ucore_Uusb_syn5300,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C650_FROM
    );
  Ucore_Uusb_C3163 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => Ucore_Uusb_syn5325,
      ADR2 => Ucore_Uusb_syn5300,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C650_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C650_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C650_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C650
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C650_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C650_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C564
    );
  Ucore_Uusb_C3059 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      O => Ucore_Uusb_Uuc_ALUOP_2_FROM
    );
  Ucore_Uusb_C3058 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7644,
      ADR1 => Ucore_Uusb_syn28023,
      ADR2 => Ucore_Uusb_syn7677,
      ADR3 => Ucore_Uusb_syn28024,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N58
    );
  Ucore_Uusb_Uuc_ALUOP_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_ALUOP_2_FROM,
      O => Ucore_Uusb_syn28024
    );
  Ucore_Uusb_C3762 : X_LUT4
    generic map(
      INIT => X"9C93"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26085,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(7),
      O => Ucore_Uusb_syn20388_FROM
    );
  Ucore_Uusb_C3324 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C433_C2_C5,
      O => Ucore_Uusb_syn20388_GROM
    );
  Ucore_Uusb_syn20388_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20388_FROM,
      O => Ucore_Uusb_syn20388
    );
  Ucore_Uusb_syn20388_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20388_GROM,
      O => Ucore_Uusb_syn20390
    );
  Ucore_Ufunc_ram_writeAddr_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(1),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(1)
    );
  Ucore_Ufunc_ram_writeAddr_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(3),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(3)
    );
  Ucore_Ufunc_ram_writeAddr_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(7),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(7)
    );
  Ucore_Ufunc_ram_writeAddr_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(0),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(0)
    );
  Ucore_Ufunc_ram_writeAddr_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(5),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(5)
    );
  Ucore_Ufunc_ram_writeAddr_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(2),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(2)
    );
  Ucore_Ufunc_addr_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_4_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(4)
    );
  Ucore_Ufunc_addr_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_12_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(12)
    );
  Ucore_Ufunc_addr_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_6_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(6)
    );
  Ucore_Ufunc_addr_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_axb_3,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(3)
    );
  Ucore_Ufunc_addr_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_5_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(5)
    );
  Ucore_Ufunc_addr_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_8_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(8)
    );
  Ucore_Ufunc_addr_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_10_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(10)
    );
  Ucore_Ufunc_ram_writeAddr_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(13),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(13)
    );
  Ucore_Ufunc_ram_writeAddr_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(4),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(4)
    );
  Ucore_Ufunc_ram_writeAddr_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(6),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(6)
    );
  Ucore_Ufunc_ram_writeAddr_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(9),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(9)
    );
  Ucore_Ufunc_ram_writeAddr_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(11),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(11)
    );
  Ucore_Ufunc_ram_writeAddr_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(8),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(8)
    );
  Ucore_Ufunc_i_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(8),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(8)
    );
  Ucore_Ufunc_i_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(10),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(10)
    );
  Ucore_Ufunc_i_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(13),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(13)
    );
  Ucore_Ufunc_i_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(12),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(12)
    );
  Ucore_Ufunc_i_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(15),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(15)
    );
  Ucore_Ufunc_i_17_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(17),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(17)
    );
  Ucore_Ufunc_ram_readAddr_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(13),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(13)
    );
  Ucore_Ufunc_ram_readAddr_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(15),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(15)
    );
  Ucore_Ufunc_ram_readAddr_17_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(17),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_17_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(17)
    );
  Ucore_Uusb_C3500 : X_LUT4
    generic map(
      INIT => X"33FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn6505,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5624,
      O => Ucore_Uusb_Uuc_Udmux_C929_FROM
    );
  Ucore_Uusb_C3485 : X_LUT4
    generic map(
      INIT => X"F090"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR2 => Ucore_Uusb_syn27122,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C929,
      O => Ucore_Uusb_Uuc_Udmux_C929_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C929_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C929_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C929
    );
  Ucore_Uusb_Uuc_Udmux_C929_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C929_GROM,
      O => Ucore_Uusb_syn6514
    );
  Ucore_Uusb_C3381 : X_LUT4
    generic map(
      INIT => X"A8B9"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      O => Ucore_Uusb_syn27327_FROM
    );
  Ucore_Uusb_C3412 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      O => Ucore_Uusb_syn27327_GROM
    );
  Ucore_Uusb_syn27327_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27327_FROM,
      O => Ucore_Uusb_syn27327
    );
  Ucore_Uusb_syn27327_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27327_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1450
    );
  Ucore_Uusb_C3828 : X_LUT4
    generic map(
      INIT => X"4F40"
    )
    port map (
      ADR0 => Ucore_Uusb_Uglue_N31,
      ADR1 => Ucore_Uusb_syn5544,
      ADR2 => Ucore_Uusb_syn5458,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C11_C1,
      O => Ucore_Uusb_Uusb_NET71_FROM
    );
  Ucore_Uusb_C3252 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27650,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET2015,
      ADR2 => Ucore_Uusb_syn5544,
      ADR3 => Ucore_Uusb_syn27651,
      O => Ucore_Uusb_Uusb_NET71_GROM
    );
  Ucore_Uusb_Uusb_NET71_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_NET71_FROM,
      O => Ucore_Uusb_Uusb_NET71
    );
  Ucore_Uusb_Uusb_NET71_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_NET71_GROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6
    );
  Ucore_Uusb_C3092 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn7274,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn7264,
      O => Ucore_Uusb_syn27958_FROM
    );
  Ucore_Uusb_C3091 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      ADR1 => Ucore_Uusb_syn7499,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C580,
      ADR3 => Ucore_Uusb_syn27958,
      O => Ucore_Uusb_syn27958_GROM
    );
  Ucore_Uusb_syn27958_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27958_FROM,
      O => Ucore_Uusb_syn27958
    );
  Ucore_Uusb_syn27958_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27958_GROM,
      O => Ucore_Uusb_syn27960
    );
  Ucore_Uusb_C3501 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27103,
      ADR1 => Ucore_Uusb_syn27110,
      ADR2 => Ucore_Uusb_syn27104,
      ADR3 => Ucore_Uusb_syn6498,
      O => Ucore_Uusb_syn6505_FROM
    );
  Ucore_Uusb_C3484 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5161,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_syn6505,
      O => Ucore_Uusb_syn6505_GROM
    );
  Ucore_Uusb_syn6505_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6505_FROM,
      O => Ucore_Uusb_syn6505
    );
  Ucore_Uusb_syn6505_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6505_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C939
    );
  Ucore_Uusb_C3421 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_in_en,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_out_en,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C1471,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FROM
    );
  Ucore_Uusb_C3420 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27248,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_N219,
      ADR3 => Ucore_Uusb_syn27249,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C38_N25
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FROM,
      O => Ucore_Uusb_syn27249
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2873 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      O => Ucore_Uusb_syn5164_FROM
    );
  Ucore_Uusb_C3413 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1035,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      O => Ucore_Uusb_syn5164_GROM
    );
  Ucore_Uusb_syn5164_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5164_FROM,
      O => Ucore_Uusb_syn5164
    );
  Ucore_Uusb_syn5164_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5164_GROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C9_C0
    );
  Ucore_Uusb_C3333 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C677,
      ADR3 => Ucore_Uusb_syn6908,
      O => Ucore_Uusb_syn27466_FROM
    );
  Ucore_Uusb_C3332 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C597,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR3 => Ucore_Uusb_syn27466,
      O => Ucore_Uusb_syn27466_GROM
    );
  Ucore_Uusb_syn27466_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27466_FROM,
      O => Ucore_Uusb_syn27466
    );
  Ucore_Uusb_syn27466_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27466_GROM,
      O => Ucore_Uusb_syn6920
    );
  Ucore_Uusb_C3729 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_syn5667,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(4),
      O => Ucore_Uusb_Uuc_Ualu_C617_FROM
    );
  Ucore_Uusb_C3309 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR2 => Ucore_Uusb_syn5323,
      ADR3 => Ucore_Uusb_Uuc_Ualu_N1358,
      O => Ucore_Uusb_Uuc_Ualu_C617_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C617_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C617_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C617
    );
  Ucore_Uusb_Uuc_Ualu_C617_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C617_GROM,
      O => Ucore_Uusb_syn6992
    );
  Ucore_Uusb_C2771 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS1610_14_Q,
      ADR1 => Ucore_Uusb_BUS1610_15_Q,
      ADR2 => Ucore_Uusb_BUS1610_12_Q,
      ADR3 => Ucore_Uusb_BUS1610_13_Q,
      O => Ucore_Uusb_Uglue_N37_FROM
    );
  Ucore_Uusb_C3253 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_BUS1610_12_Q,
      ADR3 => Ucore_Uusb_BUS1610_13_Q,
      O => Ucore_Uusb_Uglue_N37_GROM
    );
  Ucore_Uusb_Uglue_N37_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_N37_FROM,
      O => Ucore_Uusb_Uglue_N37
    );
  Ucore_Uusb_Uglue_N37_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_N37_GROM,
      O => Ucore_Uusb_syn27651
    );
  Ucore_Uusb_C3181 : X_LUT4
    generic map(
      INIT => X"5400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5327,
      ADR2 => Ucore_Uusb_syn5326,
      ADR3 => Ucore_Uusb_syn5300,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FROM
    );
  Ucore_Uusb_C3180 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_N59,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR3 => Ucore_Uusb_syn7274,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FROM,
      O => Ucore_Uusb_syn7274
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N399
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3176 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5162,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR2 => Ucore_Uusb_syn5290,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C746_FROM
    );
  Ucore_Uusb_C3165 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5290,
      ADR1 => Ucore_Uusb_syn5301,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C746_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C746_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C746_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C746
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_C746_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C746_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C758
    );
  Ucore_Uusb_C3584 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C319,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(9),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C325,
      O => Ucore_Uusb_syn26906_FROM
    );
  Ucore_Uusb_C3157 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      O => Ucore_Uusb_syn26906_GROM
    );
  Ucore_Uusb_syn26906_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26906_FROM,
      O => Ucore_Uusb_syn26906
    );
  Ucore_Uusb_syn26906_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26906_GROM,
      O => Ucore_Uusb_syn27841
    );
  Ucore_Uusb_C3149 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5328,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C690,
      ADR2 => Ucore_Uusb_syn5300,
      ADR3 => Ucore_Uusb_syn5313,
      O => Ucore_Uusb_syn27855_FROM
    );
  Ucore_Uusb_C3148 : X_LUT4
    generic map(
      INIT => X"0C08"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C700,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn27855,
      O => Ucore_Uusb_syn27855_GROM
    );
  Ucore_Uusb_syn27855_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27855_FROM,
      O => Ucore_Uusb_syn27855
    );
  Ucore_Uusb_syn27855_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27855_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C667
    );
  Ucore_Uusb_C3430 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      ADR1 => Ucore_Uusb_Uusb_Usie_BUS1153(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_FROM
    );
  Ucore_Uusb_C3019 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_NET1024,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1039,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET1035,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_GROM
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_FROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2_GROM,
      O => Ucore_Uusb_syn7799
    );
  Ucore_Uusb_C3326 : X_LUT4
    generic map(
      INIT => X"3F03"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_syn26085,
      ADR3 => Ucore_Uusb_Uuc_BUS10875(7),
      O => Ucore_Uusb_syn23977_FROM
    );
  Ucore_Uusb_C3325 : X_LUT4
    generic map(
      INIT => X"EECC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C683,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn23977,
      O => Ucore_Uusb_syn23977_GROM
    );
  Ucore_Uusb_syn23977_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23977_FROM,
      O => Ucore_Uusb_syn23977
    );
  Ucore_Uusb_syn23977_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23977_GROM,
      O => Ucore_Uusb_syn6951
    );
  Ucore_Uusb_C3254 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_BUS1610_15_Q,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_BUS1610_14_Q,
      O => Ucore_Uusb_syn27650_GROM
    );
  Ucore_Uusb_syn27650_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27650_GROM,
      O => Ucore_Uusb_syn27650
    );
  Ucore_Uusb_C3174 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C756,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C705,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C746,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FROM
    );
  Ucore_Uusb_C3084 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C664,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N53,
      ADR3 => Ucore_Uusb_syn7304,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1135
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FROM,
      O => Ucore_Uusb_syn7304
    );
  Ucore_Uusb_C3078 : X_LUT4
    generic map(
      INIT => X"FFBA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N311,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FROM
    );
  Ucore_Uusb_C3077 : X_LUT4
    generic map(
      INIT => X"FF54"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C788,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C690,
      ADR3 => Ucore_Uusb_syn27984,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N225
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FROM,
      O => Ucore_Uusb_syn27984
    );
  Ucore_Uusb_C3511 : X_LUT4
    generic map(
      INIT => X"0888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27054,
      ADR1 => Ucore_Uusb_syn6430,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      O => Ucore_Uusb_syn27056_FROM
    );
  Ucore_Uusb_C3510 : X_LUT4
    generic map(
      INIT => X"D000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555,
      ADR2 => Ucore_Uusb_syn23576,
      ADR3 => Ucore_Uusb_syn27056,
      O => Ucore_Uusb_syn27056_GROM
    );
  Ucore_Uusb_syn27056_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27056_FROM,
      O => Ucore_Uusb_syn27056
    );
  Ucore_Uusb_syn27056_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27056_GROM,
      O => Ucore_Uusb_syn6437
    );
  Ucore_Uusb_C3503 : X_LUT4
    generic map(
      INIT => X"80A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27093,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555,
      ADR2 => Ucore_Uusb_syn27094,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(2),
      O => Ucore_Uusb_syn6464_FROM
    );
  Ucore_Uusb_C3502 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_RAM_REG(7),
      ADR1 => Ucore_Uusb_syn6464,
      ADR2 => Ucore_Uusb_syn6451,
      ADR3 => Ucore_Uusb_syn6437,
      O => Ucore_Uusb_syn6464_GROM
    );
  Ucore_Uusb_syn6464_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6464_FROM,
      O => Ucore_Uusb_syn6464
    );
  Ucore_Uusb_syn6464_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6464_GROM,
      O => Ucore_Uusb_syn27110
    );
  Ucore_Uusb_C3423 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      O => Ucore_Uusb_syn6653_FROM
    );
  Ucore_Uusb_C3396 : X_LUT4
    generic map(
      INIT => X"ACCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_S_1_cell0,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_syn6653,
      O => Ucore_Uusb_syn6653_GROM
    );
  Ucore_Uusb_syn6653_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6653_FROM,
      O => Ucore_Uusb_syn6653
    );
  Ucore_Uusb_syn6653_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6653_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C9_N9
    );
  Ucore_Uusb_C3415 : X_LUT4
    generic map(
      INIT => X"EA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_in_en,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1035,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C1471,
      O => Ucore_Uusb_syn6691_FROM
    );
  Ucore_Uusb_C3414 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_in_trac(0),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_C492,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_out_en,
      ADR3 => Ucore_Uusb_syn6691,
      O => Ucore_Uusb_syn6691_GROM
    );
  Ucore_Uusb_syn6691_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6691_FROM,
      O => Ucore_Uusb_syn6691
    );
  Ucore_Uusb_syn6691_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6691_GROM,
      O => Ucore_Uusb_syn27278
    );
  Ucore_Uusb_C3335 : X_LUT4
    generic map(
      INIT => X"FA75"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6524,
      ADR1 => Ucore_Uusb_syn5332,
      ADR2 => Ucore_Uusb_syn6779,
      ADR3 => Ucore_Uusb_syn6514,
      O => Ucore_Uusb_Uuc_PO_5_FROM
    );
  Ucore_Uusb_C3315 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(5),
      ADR1 => Ucore_Uusb_Uuc_DBUS(5),
      ADR2 => Ucore_Uusb_syn5318,
      ADR3 => Ucore_Uusb_syn6904,
      O => Ucore_Uusb_Uuc_Upsw_C0_N18
    );
  Ucore_Uusb_Uuc_PO_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PO_5_FROM,
      O => Ucore_Uusb_syn6904
    );
  Ucore_Uusb_Uuc_PO_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3319 : X_LUT4
    generic map(
      INIT => X"BAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27499,
      ADR1 => Ucore_Uusb_syn20390,
      ADR2 => Ucore_Uusb_syn6951,
      ADR3 => Ucore_Uusb_syn26085,
      O => Ucore_Uusb_Uuc_PO_2_FROM
    );
  Ucore_Uusb_C3318 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6904,
      ADR1 => Ucore_Uusb_Uuc_DBUS(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn20436,
      O => Ucore_Uusb_Uuc_Upsw_C0_N36
    );
  Ucore_Uusb_Uuc_PO_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_PO_2_FROM,
      O => Ucore_Uusb_syn20436
    );
  Ucore_Uusb_Uuc_PO_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_PO_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3183 : X_LUT4
    generic map(
      INIT => X"00A8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5299,
      ADR1 => Ucore_Uusb_syn5327,
      ADR2 => Ucore_Uusb_syn5326,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FROM
    );
  Ucore_Uusb_C3182 : X_LUT4
    generic map(
      INIT => X"FF0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C792,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_syn7264,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FROM,
      O => Ucore_Uusb_syn7264
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1870
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3707 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(7),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C331,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(15),
      O => Ucore_Uusb_syn26593_FROM
    );
  Ucore_Uusb_C3600 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(2),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C331,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(10),
      O => Ucore_Uusb_syn26593_GROM
    );
  Ucore_Uusb_syn26593_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26593_FROM,
      O => Ucore_Uusb_syn26593
    );
  Ucore_Uusb_syn26593_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26593_GROM,
      O => Ucore_Uusb_syn26858
    );
  Ucore_Uusb_C3520 : X_LUT4
    generic map(
      INIT => X"BAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn23598,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(3),
      O => Ucore_Uusb_syn27074_FROM
    );
  Ucore_Uusb_C3519 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27073,
      ADR1 => Ucore_Uusb_syn27072,
      ADR2 => Ucore_Uusb_syn23597,
      ADR3 => Ucore_Uusb_syn27074,
      O => Ucore_Uusb_syn27074_GROM
    );
  Ucore_Uusb_syn27074_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27074_FROM,
      O => Ucore_Uusb_syn27074
    );
  Ucore_Uusb_syn27074_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27074_GROM,
      O => Ucore_Uusb_syn6498
    );
  Ucore_Uusb_C3523 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(3),
      O => Ucore_Uusb_syn27073_FROM
    );
  Ucore_Uusb_C3504 : X_LUT4
    generic map(
      INIT => X"153F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167,
      O => Ucore_Uusb_syn27073_GROM
    );
  Ucore_Uusb_syn27073_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27073_FROM,
      O => Ucore_Uusb_syn27073
    );
  Ucore_Uusb_syn27073_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27073_GROM,
      O => Ucore_Uusb_syn27094
    );
  Ucore_Uusb_C2871 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3,
      ADR2 => Ucore_Uusb_Uglue_bytecount(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_syn5303_FROM
    );
  Ucore_Uusb_C3440 : X_LUT4
    generic map(
      INIT => X"0F2F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uglue_txen1,
      ADR1 => Ucore_Uusb_NET3345,
      ADR2 => Ucore_Uusb_IT(1),
      ADR3 => Ucore_Uusb_Uglue_bytecount(1),
      O => Ucore_Uusb_syn5303_GROM
    );
  Ucore_Uusb_syn5303_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5303_FROM,
      O => Ucore_Uusb_syn5303
    );
  Ucore_Uusb_syn5303_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5303_GROM,
      O => Ucore_Uusb_Uglue_C27_N9
    );
  Ucore_Uusb_C3416 : X_LUT4
    generic map(
      INIT => X"F780"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1039,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C1461,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C1454,
      O => Ucore_Uusb_syn27277_GROM
    );
  Ucore_Uusb_syn27277_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27277_GROM,
      O => Ucore_Uusb_syn27277
    );
  Ucore_Uusb_C3360 : X_LUT4
    generic map(
      INIT => X"B0B0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27389,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_syn6805,
      ADR3 => VCC,
      O => Ucore_Uusb_syn6824_FROM
    );
  Ucore_Uusb_C3298 : X_LUT4
    generic map(
      INIT => X"B300"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR1 => Ucore_Uusb_syn6821,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => Ucore_Uusb_syn6824,
      O => Ucore_Uusb_syn6824_GROM
    );
  Ucore_Uusb_syn6824_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6824_FROM,
      O => Ucore_Uusb_syn6824
    );
  Ucore_Uusb_syn6824_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6824_GROM,
      O => Ucore_Uusb_Uuc_PCWR
    );
  Ucore_Uusb_C3291 : X_LUT4
    generic map(
      INIT => X"000A"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6514,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6519,
      ADR3 => Ucore_Uusb_syn6527,
      O => Ucore_Uusb_Uuc_Udmux_C751_FROM
    );
  Ucore_Uusb_C3328 : X_LUT4
    generic map(
      INIT => X"33B3"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5316,
      ADR1 => Ucore_Uusb_syn6904,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_Uuc_Udmux_C751_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C751_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C751_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C751
    );
  Ucore_Uusb_Uuc_Udmux_C751_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C751_GROM,
      O => Ucore_Uusb_N1495
    );
  Ucore_Uusb_C3168 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C570,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FROM
    );
  Ucore_Uusb_C3167 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7321,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1437,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1221,
      ADR3 => Ucore_Uusb_syn27935,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FROM,
      O => Ucore_Uusb_syn27935
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1827
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2800 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6
    );
  Ucore_Uusb_C3710 : X_LUT4
    generic map(
      INIT => X"A088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR1 => Ucore_Uusb_BUS131(7),
      ADR2 => Ucore_Uusb_Uuc_Uport0_pad(7),
      ADR3 => Ucore_Uusb_syn5952,
      O => Ucore_Uusb_syn26597_FROM
    );
  Ucore_Uusb_C3601 : X_LUT4
    generic map(
      INIT => X"A808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR1 => Ucore_Uusb_BUS131(2),
      ADR2 => Ucore_Uusb_syn5952,
      ADR3 => Ucore_Uusb_Uuc_Uport0_pad(2),
      O => Ucore_Uusb_syn26597_GROM
    );
  Ucore_Uusb_syn26597_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26597_FROM,
      O => Ucore_Uusb_syn26597
    );
  Ucore_Uusb_syn26597_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26597_GROM,
      O => Ucore_Uusb_syn26862
    );
  Ucore_Uusb_C3425 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1461_FROM
    );
  Ucore_Uusb_C3424 : X_LUT4
    generic map(
      INIT => X"FF30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_in_trac(0),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C1465,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_C1461,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1461_GROM
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C1461_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1461_FROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1461
    );
  Ucore_Uusb_Uusb_Uep0ctrl_C1461_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1461_GROM,
      O => Ucore_Uusb_syn27248
    );
  Ucore_Uusb_C3409 : X_LUT4
    generic map(
      INIT => X"FFCE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C1450,
      ADR1 => Ucore_Uusb_syn27276,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C9_C0,
      ADR3 => Ucore_Uusb_syn6694,
      O => Ucore_Uusb_syn27279_FROM
    );
  Ucore_Uusb_C3408 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6690,
      ADR1 => Ucore_Uusb_syn27277,
      ADR2 => Ucore_Uusb_syn27278,
      ADR3 => Ucore_Uusb_syn27279,
      O => Ucore_Uusb_syn27279_GROM
    );
  Ucore_Uusb_syn27279_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27279_FROM,
      O => Ucore_Uusb_syn27279
    );
  Ucore_Uusb_syn27279_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27279_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C39_N30
    );
  Ucore_Uusb_C3361 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      O => Ucore_Uusb_syn27389_FROM
    );
  Ucore_Uusb_C3359 : X_LUT4
    generic map(
      INIT => X"0545"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6821,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_syn6805,
      ADR3 => Ucore_Uusb_syn27389,
      O => Ucore_Uusb_syn27389_GROM
    );
  Ucore_Uusb_syn27389_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27389_FROM,
      O => Ucore_Uusb_syn27389
    );
  Ucore_Uusb_syn27389_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27389_GROM,
      O => Ucore_Uusb_Uuc_ADXWR
    );
  Ucore_Uusb_C3265 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Urst_cnt(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Urst_cnt(3),
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FROM
    );
  Ucore_Uusb_C3256 : X_LUT4
    generic map(
      INIT => X"28A0"
    )
    port map (
      ADR0 => Ucore_urx0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(4),
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(5),
      ADR3 => Ucore_Uusb_syn7088,
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N29
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_5_CEMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C0_N3,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_CEMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FROM,
      O => Ucore_Uusb_syn7088
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3193 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5344,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FROM
    );
  Ucore_Uusb_C3075 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7410,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1697,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474,
      ADR3 => Ucore_Uusb_syn27986,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1999
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FROM,
      O => Ucore_Uusb_syn27986
    );
  Ucore_Uusb_C3185 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      O => Ucore_Uusb_syn5325_FROM
    );
  Ucore_Uusb_C3184 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR2 => Ucore_Uusb_syn5313,
      ADR3 => Ucore_Uusb_syn5325,
      O => Ucore_Uusb_syn5325_GROM
    );
  Ucore_Uusb_syn5325_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5325_FROM,
      O => Ucore_Uusb_syn5325
    );
  Ucore_Uusb_syn5325_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5325_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C570
    );
  Ucore_Uusb_C3177 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn5301,
      ADR2 => Ucore_Uusb_syn5290,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FROM
    );
  Ucore_Uusb_C3173 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C705,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C746,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C756,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C756
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1437
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3592 : X_LUT4
    generic map(
      INIT => X"E00E"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C683,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR2 => Ucore_Uusb_syn23120,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C424_C0_C3,
      O => Ucore_Uusb_syn6264_FROM
    );
  Ucore_Uusb_C3610 : X_LUT4
    generic map(
      INIT => X"C832"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C683,
      ADR1 => Ucore_Uusb_syn23109,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR3 => Ucore_Uusb_syn26461,
      O => Ucore_Uusb_syn6264_GROM
    );
  Ucore_Uusb_syn6264_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6264_FROM,
      O => Ucore_Uusb_syn6264
    );
  Ucore_Uusb_syn6264_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6264_GROM,
      O => Ucore_Uusb_syn6225
    );
  Ucore_Uusb_C3715 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C319,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(15),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C325,
      O => Ucore_Uusb_syn26592_FROM
    );
  Ucore_Uusb_C3602 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_Uuc_DPTRO(10),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C325,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C319,
      O => Ucore_Uusb_syn26592_GROM
    );
  Ucore_Uusb_syn26592_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26592_FROM,
      O => Ucore_Uusb_syn26592
    );
  Ucore_Uusb_syn26592_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26592_GROM,
      O => Ucore_Uusb_syn26857
    );
  Ucore_Uusb_C3530 : X_LUT4
    generic map(
      INIT => X"2A3F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(4),
      O => Ucore_Uusb_syn27104_FROM
    );
  Ucore_Uusb_C3529 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn27103,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn27104,
      O => Ucore_Uusb_syn27104_GROM
    );
  Ucore_Uusb_syn27104_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27104_FROM,
      O => Ucore_Uusb_syn27104
    );
  Ucore_Uusb_syn27104_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27104_GROM,
      O => Ucore_Uusb_syn6478
    );
  Ucore_Uusb_C3522 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_FROM
    );
  Ucore_Uusb_C3032 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C481,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C456_GROM,
      O => Ucore_Uusb_syn28105
    );
  Ucore_Uusb_C3514 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_FROM
    );
  Ucore_Uusb_C3509 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C483_GROM,
      O => Ucore_Uusb_syn6444
    );
  Ucore_Uusb_C3465 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N372,
      ADR1 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(0),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N6_FROM
    );
  Ucore_Uusb_C3450 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_N387,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(15),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N6_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N6_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N6
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N6_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N96
    );
  Ucore_Uusb_C3371 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6514,
      ADR1 => Ucore_Uusb_syn6527,
      ADR2 => Ucore_Uusb_syn6524,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_Uuc_P0WR_FROM
    );
  Ucore_Uusb_C3370 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6514,
      ADR1 => Ucore_Uusb_syn6524,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_Uuc_P0WR_GROM
    );
  Ucore_Uusb_Uuc_P0WR_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_P0WR_FROM,
      O => Ucore_Uusb_Uuc_P0WR
    );
  Ucore_Uusb_Uuc_P0WR_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_P0WR_GROM,
      O => Ucore_Uusb_N1471
    );
  Ucore_Uusb_C3362 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_FROM
    );
  Ucore_Uusb_C3044 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487_GROM,
      O => Ucore_Uusb_syn28062
    );
  Ucore_Uusb_C3354 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6524,
      ADR1 => Ucore_Uusb_syn6519,
      ADR2 => Ucore_Uusb_syn6779,
      ADR3 => Ucore_Uusb_syn6514,
      O => Ucore_Uusb_Uuc_Udmux_C743_FROM
    );
  Ucore_Uusb_C3353 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6831,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C743,
      O => Ucore_Uusb_Uuc_Udmux_C743_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C743_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C743_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C743
    );
  Ucore_Uusb_Uuc_Udmux_C743_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C743_GROM,
      O => Ucore_Uusb_N1494
    );
  Ucore_Uusb_C3194 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR1 => Ucore_Uusb_syn5299,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      O => Ucore_Uusb_syn5344_FROM
    );
  Ucore_Uusb_C3080 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR3 => Ucore_Uusb_syn5344,
      O => Ucore_Uusb_syn5344_GROM
    );
  Ucore_Uusb_syn5344_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5344_FROM,
      O => Ucore_Uusb_syn5344
    );
  Ucore_Uusb_syn5344_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5344_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C558
    );
  Ucore_Uusb_C3178 : X_LUT4
    generic map(
      INIT => X"0303"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5290_FROM
    );
  Ucore_Uusb_C3175 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5290,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      O => Ucore_Uusb_syn5290_GROM
    );
  Ucore_Uusb_syn5290_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5290_FROM,
      O => Ucore_Uusb_syn5290
    );
  Ucore_Uusb_syn5290_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5290_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C705
    );
  Ucore_Uusb_C3768 : X_LUT4
    generic map(
      INIT => X"55FF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(6),
      O => Ucore_Uusb_syn5751_FROM
    );
  Ucore_Uusb_C3611 : X_LUT4
    generic map(
      INIT => X"1B1B"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_syn20278,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5751_GROM
    );
  Ucore_Uusb_syn5751_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5751_FROM,
      O => Ucore_Uusb_syn5751
    );
  Ucore_Uusb_syn5751_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5751_GROM,
      O => Ucore_Uusb_syn23109
    );
  Ucore_Uusb_C3718 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_OP2(7),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR3 => Ucore_Uusb_Uuc_OP3(7),
      O => Ucore_Uusb_syn26591_FROM
    );
  Ucore_Uusb_C3603 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_OP3(2),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR3 => Ucore_Uusb_Uuc_OP2(2),
      O => Ucore_Uusb_syn26591_GROM
    );
  Ucore_Uusb_syn26591_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26591_FROM,
      O => Ucore_Uusb_syn26591
    );
  Ucore_Uusb_syn26591_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26591_GROM,
      O => Ucore_Uusb_syn26856
    );
  Ucore_Uusb_C3507 : X_LUT4
    generic map(
      INIT => X"4C00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(1),
      ADR1 => Ucore_Uusb_syn27084,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      ADR3 => Ucore_Uusb_syn6444,
      O => Ucore_Uusb_syn27086_FROM
    );
  Ucore_Uusb_C3506 : X_LUT4
    generic map(
      INIT => X"8A00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn23576,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C555,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(1),
      ADR3 => Ucore_Uusb_syn27086,
      O => Ucore_Uusb_syn27086_GROM
    );
  Ucore_Uusb_syn27086_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27086_FROM,
      O => Ucore_Uusb_syn27086
    );
  Ucore_Uusb_syn27086_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27086_GROM,
      O => Ucore_Uusb_syn6451
    );
  Ucore_Uusb_C3464 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(1),
      ADR1 => Ucore_Uusb_Uuc_Ubuf_N373,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_relf,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N12_FROM
    );
  Ucore_Uusb_C3451 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ubuf_N386,
      ADR2 => Ucore_Uusb_Uuc_BUFO8(14),
      ADR3 => Ucore_Uusb_Uuc_Ubuf_relf,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N12_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N12_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N12_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N12
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N12_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N12_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N90
    );
  Ucore_Uusb_C3443 : X_LUT4
    generic map(
      INIT => X"2AAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FROM
    );
  Ucore_Uusb_C3442 : X_LUT4
    generic map(
      INIT => X"0047"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR3 => Ucore_Uusb_syn6629,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FROM,
      O => Ucore_Uusb_syn6629
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3419 : X_LUT4
    generic map(
      INIT => X"3010"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      O => Ucore_Uusb_syn6673_FROM
    );
  Ucore_Uusb_C3418 : X_LUT4
    generic map(
      INIT => X"A800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      ADR1 => Ucore_Uusb_Uusb_Usie_NET1024,
      ADR2 => Ucore_Uusb_Uusb_Usie_NET1035,
      ADR3 => Ucore_Uusb_syn6673,
      O => Ucore_Uusb_syn6673_GROM
    );
  Ucore_Uusb_syn6673_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6673_FROM,
      O => Ucore_Uusb_syn6673
    );
  Ucore_Uusb_syn6673_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6673_GROM,
      O => Ucore_Uusb_syn6690
    );
  Ucore_Uusb_C3259 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Urst_cnt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Urst_cnt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Urst_cnt(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FROM
    );
  Ucore_Uusb_C3258 : X_LUT4
    generic map(
      INIT => X"4488"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Urst_cnt(3),
      ADR1 => Ucore_urx0,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Urst_C67_C3_C1,
      O => Ucore_Uusb_Uusb_Usie_Urst_C68_N19
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_3_CEMUX : X_INV
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C0_N3,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_CEMUXNOT
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FROM,
      O => Ucore_Uusb_Uusb_Usie_Urst_C67_C3_C1
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3187 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR2 => Ucore_Uusb_syn5301,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FROM
    );
  Ucore_Uusb_C3137 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C568,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C588,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C588
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N311
    );
  Ucore_Uusb_C3099 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C584,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Uuop_C597,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_N26,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_N103,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FROM
    );
  Ucore_Uusb_C3098 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N485,
      ADR1 => Ucore_Uusb_syn5249,
      ADR2 => Ucore_Uusb_syn7544,
      ADR3 => Ucore_Uusb_syn27944,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2904
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FROM,
      O => Ucore_Uusb_syn27944
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2803 : X_LUT4
    generic map(
      INIT => X"3330"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0,
      ADR2 => Ucore_Uusb_syn28585,
      ADR3 => Ucore_Uusb_syn5329,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FROM
    );
  Ucore_Uusb_C2794 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2),
      ADR1 => Ucore_urx0,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR3 => Ucore_Uusb_syn8421,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N39
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FROM,
      O => Ucore_Uusb_syn8421
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3681 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C319,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C325,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(6),
      ADR3 => Ucore_Uusb_Uuc_DPTRO(14),
      O => Ucore_Uusb_syn26646_FROM
    );
  Ucore_Uusb_C3620 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(11),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C319,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C325,
      O => Ucore_Uusb_syn26646_GROM
    );
  Ucore_Uusb_syn26646_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26646_FROM,
      O => Ucore_Uusb_syn26646
    );
  Ucore_Uusb_syn26646_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26646_GROM,
      O => Ucore_Uusb_syn26807
    );
  Ucore_Uusb_C3701 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_SPO(7),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C345,
      ADR3 => Ucore_Uusb_Uuc_PO(7),
      O => Ucore_Uusb_syn26595_FROM
    );
  Ucore_Uusb_C3540 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR1 => Ucore_Uusb_Uuc_PO(0),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C345,
      ADR3 => Ucore_Uusb_Uuc_SPO(0),
      O => Ucore_Uusb_syn26595_GROM
    );
  Ucore_Uusb_syn26595_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26595_FROM,
      O => Ucore_Uusb_syn26595
    );
  Ucore_Uusb_syn26595_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26595_GROM,
      O => Ucore_Uusb_syn27013
    );
  Ucore_Uusb_C3532 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_FROM
    );
  Ucore_Uusb_C3531 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C479_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541
    );
  Ucore_Uusb_C3534 : X_LUT4
    generic map(
      INIT => X"135F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(4),
      O => Ucore_Uusb_syn27103_FROM
    );
  Ucore_Uusb_C3524 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(3),
      O => Ucore_Uusb_syn27103_GROM
    );
  Ucore_Uusb_syn27103_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27103_FROM,
      O => Ucore_Uusb_syn27103
    );
  Ucore_Uusb_syn27103_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27103_GROM,
      O => Ucore_Uusb_syn27072
    );
  Ucore_Uusb_C3516 : X_LUT4
    generic map(
      INIT => X"D7F7"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C569,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      O => Ucore_Uusb_syn23575_FROM
    );
  Ucore_Uusb_C3515 : X_LUT4
    generic map(
      INIT => X"7F00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5539,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR3 => Ucore_Uusb_syn23575,
      O => Ucore_Uusb_syn23575_GROM
    );
  Ucore_Uusb_syn23575_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23575_FROM,
      O => Ucore_Uusb_syn23575
    );
  Ucore_Uusb_syn23575_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23575_GROM,
      O => Ucore_Uusb_syn23576
    );
  Ucore_Uusb_C3508 : X_LUT4
    generic map(
      INIT => X"135F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(1),
      O => Ucore_Uusb_syn27084_GROM
    );
  Ucore_Uusb_syn27084_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27084_GROM,
      O => Ucore_Uusb_syn27084
    );
  Ucore_Uusb_C3463 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N374,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_relf,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N18_FROM
    );
  Ucore_Uusb_C3460 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR1 => Ucore_Uusb_Uuc_Ubuf_N377,
      ADR2 => Ucore_Uusb_Uuc_BUFO8(5),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N18_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N18_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N18_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N18
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N18_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N18_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N36
    );
  Ucore_Uusb_C3462 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUFO8(3),
      ADR3 => Ucore_Uusb_Uuc_Ubuf_N375,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N24_FROM
    );
  Ucore_Uusb_C3452 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(13),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_N385,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N24_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N24_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N24_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N24
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N24_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N24_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N84
    );
  Ucore_Uusb_C3428 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5333_FROM
    );
  Ucore_Uusb_C3405 : X_LUT4
    generic map(
      INIT => X"AE0C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_C1471,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_in_en,
      ADR3 => Ucore_Uusb_syn5333,
      O => Ucore_Uusb_syn5333_GROM
    );
  Ucore_Uusb_syn5333_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5333_FROM,
      O => Ucore_Uusb_syn5333
    );
  Ucore_Uusb_syn5333_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5333_GROM,
      O => Ucore_Uusb_syn6707
    );
  Ucore_Uusb_C3380 : X_LUT4
    generic map(
      INIT => X"FECC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C1454,
      ADR1 => Ucore_Uusb_syn27327,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_C1450,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C11_C1,
      O => Ucore_Uusb_syn27328_FROM
    );
  Ucore_Uusb_C3379 : X_LUT4
    generic map(
      INIT => X"FF20"
    )
    port map (
      ADR0 => Ucore_Uusb_NET3345,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR3 => Ucore_Uusb_syn27328,
      O => Ucore_Uusb_syn27328_GROM
    );
  Ucore_Uusb_syn27328_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27328_FROM,
      O => Ucore_Uusb_syn27328
    );
  Ucore_Uusb_syn27328_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27328_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C33_N15
    );
  Ucore_Uusb_C3356 : X_LUT4
    generic map(
      INIT => X"50D0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6805,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_syn6821,
      ADR3 => Ucore_Uusb_syn27389,
      O => Ucore_Uusb_Uuc_DPTRO_14_FROM
    );
  Ucore_Uusb_C3340 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ABUS(14),
      ADR2 => Ucore_Uusb_Uuc_DBUS(6),
      ADR3 => Ucore_Uusb_syn6831,
      O => Ucore_Uusb_Uuc_Udptr_C30_N6
    );
  Ucore_Uusb_Uuc_DPTRO_14_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_DPTRO_14_FROM,
      O => Ucore_Uusb_syn6831
    );
  Ucore_Uusb_Uuc_DPTRO_14_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_DPTRO_14_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3188 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5328,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5301_FROM
    );
  Ucore_Uusb_C3105 : X_LUT4
    generic map(
      INIT => X"8200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR3 => Ucore_Uusb_syn5301,
      O => Ucore_Uusb_syn5301_GROM
    );
  Ucore_Uusb_syn5301_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5301_FROM,
      O => Ucore_Uusb_syn5301
    );
  Ucore_Uusb_syn5301_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5301_GROM,
      O => Ucore_Uusb_syn27929
    );
  Ucore_Uusb_C2812 : X_LUT4
    generic map(
      INIT => X"88CC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      O => Ucore_Uusb_CLK12I_FROM
    );
  Ucore_Uusb_C2811 : X_LUT4
    generic map(
      INIT => X"B3A2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C220,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C23_N12
    );
  Ucore_Uusb_CLK12I_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_CLK12I_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C220
    );
  Ucore_Uusb_CLK12I_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_CLK12I_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3682 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_OP3(6),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR3 => Ucore_Uusb_Uuc_OP2(6),
      O => Ucore_Uusb_syn26645_FROM
    );
  Ucore_Uusb_C3621 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR1 => Ucore_Uusb_Uuc_OP3(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR3 => Ucore_Uusb_Uuc_OP2(3),
      O => Ucore_Uusb_syn26645_GROM
    );
  Ucore_Uusb_syn26645_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26645_FROM,
      O => Ucore_Uusb_syn26645
    );
  Ucore_Uusb_syn26645_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26645_GROM,
      O => Ucore_Uusb_syn26806
    );
  Ucore_Uusb_C3613 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26810,
      ADR1 => Ucore_Uusb_syn26811,
      ADR2 => Ucore_Uusb_syn26809,
      ADR3 => Ucore_Uusb_syn26808,
      O => Ucore_Uusb_Uuc_SPO_3_FROM
    );
  Ucore_Uusb_C3612 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26816,
      ADR1 => Ucore_Uusb_syn6177,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR3 => Ucore_Uusb_syn26817,
      O => Ucore_Uusb_Uuc_SPO_3_GROM
    );
  Ucore_Uusb_Uuc_SPO_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_3_FROM,
      O => Ucore_Uusb_syn26817
    );
  Ucore_Uusb_Uuc_SPO_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_3_GROM,
      O => Ucore_Uusb_Uuc_DBUS(3)
    );
  Ucore_Uusb_Uuc_SPO_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3605 : X_LUT4
    generic map(
      INIT => X"DDD8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR1 => Ucore_Uusb_syn6213,
      ADR2 => Ucore_Uusb_syn5237,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C675,
      O => Ucore_Uusb_syn26839_FROM
    );
  Ucore_Uusb_C3604 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn20278,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => Ucore_Uusb_syn26838,
      ADR3 => Ucore_Uusb_syn26839,
      O => Ucore_Uusb_syn26839_GROM
    );
  Ucore_Uusb_syn26839_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26839_FROM,
      O => Ucore_Uusb_syn26839
    );
  Ucore_Uusb_syn26839_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26839_GROM,
      O => Ucore_Uusb_syn26841
    );
  Ucore_Uusb_C3704 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR1 => Ucore_Uusb_Uuc_RO(7),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(7),
      O => Ucore_Uusb_syn26594_FROM
    );
  Ucore_Uusb_C3541 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR2 => Ucore_Uusb_Uuc_BUFO8(0),
      ADR3 => Ucore_Uusb_Uuc_RO(0),
      O => Ucore_Uusb_syn26594_GROM
    );
  Ucore_Uusb_syn26594_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26594_FROM,
      O => Ucore_Uusb_syn26594
    );
  Ucore_Uusb_syn26594_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26594_GROM,
      O => Ucore_Uusb_syn27012
    );
  Ucore_Uusb_C3459 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N378,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(6),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N42_FROM
    );
  Ucore_Uusb_C3461 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(4),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_N376,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N42_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N42_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N42_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N42
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N42_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N42_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N30
    );
  Ucore_Uusb_C3458 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N379,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(7),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N48_FROM
    );
  Ucore_Uusb_C3453 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N384,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(12),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N48_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N48_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N48_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N48
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N48_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N48_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N78
    );
  Ucore_Uusb_C3810 : X_LUT4
    generic map(
      INIT => X"FAFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5645_FROM
    );
  Ucore_Uusb_C3373 : X_LUT4
    generic map(
      INIT => X"C4CC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR1 => Ucore_Uusb_syn6478,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C929,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(0),
      O => Ucore_Uusb_syn5645_GROM
    );
  Ucore_Uusb_syn5645_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5645_FROM,
      O => Ucore_Uusb_syn5645
    );
  Ucore_Uusb_syn5645_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5645_GROM,
      O => Ucore_Uusb_syn6779
    );
  Ucore_Uusb_C3365 : X_LUT4
    generic map(
      INIT => X"EAFF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27376,
      ADR1 => Ucore_Uusb_syn21091,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      O => Ucore_Uusb_syn6817_FROM
    );
  Ucore_Uusb_C3363 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6805,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C153,
      ADR2 => Ucore_Uusb_syn6818,
      ADR3 => Ucore_Uusb_syn6817,
      O => Ucore_Uusb_syn6817_GROM
    );
  Ucore_Uusb_syn6817_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6817_FROM,
      O => Ucore_Uusb_syn6817
    );
  Ucore_Uusb_syn6817_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6817_GROM,
      O => Ucore_Uusb_syn6821
    );
  Ucore_Uusb_C3357 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6519,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_syn6524,
      O => Ucore_Uusb_Uuc_T1WR_GROM
    );
  Ucore_Uusb_Uuc_T1WR_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_T1WR_GROM,
      O => Ucore_Uusb_Uuc_T1WR
    );
  Ucore_Uusb_C3293 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR3 => Ucore_Uusb_syn7015,
      O => Ucore_Uusb_Uuc_BUFO8_8_FROM
    );
  Ucore_Uusb_C3286 : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5306,
      ADR1 => Ucore_Uusb_Uuc_DBUS(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn27574,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N74
    );
  Ucore_Uusb_Uuc_BUFO8_8_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_8_FROM,
      O => Ucore_Uusb_syn5306
    );
  Ucore_Uusb_C3277 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6519,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_syn5317,
      O => Ucore_Uusb_Uuc_Ubuf_C69_FROM
    );
  Ucore_Uusb_C3276 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(10),
      ADR1 => Ucore_Uusb_Uuc_DBUS(2),
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_C69,
      O => Ucore_Uusb_Uuc_Ubuf_C69_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C69_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C69_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C69
    );
  Ucore_Uusb_Uuc_Ubuf_C69_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C69_GROM,
      O => Ucore_Uusb_syn27599
    );
  Ucore_Uusb_C3269 : X_LUT4
    generic map(
      INIT => X"AAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(9),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C755,
      ADR2 => Ucore_Uusb_Uuc_DBUS(1),
      ADR3 => Ucore_Uusb_syn7015,
      O => Ucore_Uusb_Uuc_BUFO8_9_FROM
    );
  Ucore_Uusb_C3268 : X_LUT4
    generic map(
      INIT => X"EECC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5306,
      ADR1 => Ucore_Uusb_syn27619,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_DBUS(6),
      O => Ucore_Uusb_Uuc_Ubuf_C1_N81
    );
  Ucore_Uusb_Uuc_BUFO8_9_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_9_FROM,
      O => Ucore_Uusb_syn27619
    );
  Ucore_Uusb_C3197 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(7),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FROM
    );
  Ucore_Uusb_C3096 : X_LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5326,
      ADR1 => Ucore_Uusb_syn5302,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1049,
      ADR3 => Ucore_Uusb_syn5327,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N572
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FROM,
      O => Ucore_Uusb_syn5327
    );
  Ucore_Uusb_C3702 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5659,
      ADR1 => Ucore_Uusb_syn5653,
      ADR2 => Ucore_Uusb_syn5632,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_Uuc_Udmux_C345_FROM
    );
  Ucore_Uusb_C3580 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR1 => Ucore_Uusb_Uuc_PO(1),
      ADR2 => Ucore_Uusb_Uuc_SPO(1),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C345,
      O => Ucore_Uusb_Uuc_Udmux_C345_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C345_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C345_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C345
    );
  Ucore_Uusb_Uuc_Udmux_C345_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C345_GROM,
      O => Ucore_Uusb_syn26909
    );
  Ucore_Uusb_C3630 : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5913,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn26775,
      O => Ucore_Uusb_syn6158_FROM
    );
  Ucore_Uusb_C3629 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR1 => Ucore_Uusb_syn5190,
      ADR2 => Ucore_Uusb_syn6158,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(3),
      O => Ucore_Uusb_syn6158_GROM
    );
  Ucore_Uusb_syn6158_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6158_FROM,
      O => Ucore_Uusb_syn6158
    );
  Ucore_Uusb_syn6158_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6158_GROM,
      O => Ucore_Uusb_syn6162
    );
  Ucore_Uusb_C3676 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BO(6),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C357,
      ADR3 => Ucore_Uusb_Uuc_AO(6),
      O => Ucore_Uusb_syn26650_FROM
    );
  Ucore_Uusb_C3614 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR1 => Ucore_Uusb_Uuc_AO(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C357,
      ADR3 => Ucore_Uusb_Uuc_BO(3),
      O => Ucore_Uusb_syn26650_GROM
    );
  Ucore_Uusb_syn26650_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26650_FROM,
      O => Ucore_Uusb_syn26650
    );
  Ucore_Uusb_syn26650_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26650_GROM,
      O => Ucore_Uusb_syn26811
    );
  Ucore_Uusb_C3550 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26937,
      ADR1 => Ucore_Uusb_syn26933,
      ADR2 => Ucore_Uusb_syn26932,
      ADR3 => Ucore_Uusb_syn26988,
      O => Ucore_Uusb_syn26989_FROM
    );
  Ucore_Uusb_C3549 : X_LUT4
    generic map(
      INIT => X"FFE0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26948,
      ADR1 => Ucore_Uusb_syn20067,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR3 => Ucore_Uusb_syn26989,
      O => Ucore_Uusb_syn26989_GROM
    );
  Ucore_Uusb_syn26989_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26989_FROM,
      O => Ucore_Uusb_syn26989
    );
  Ucore_Uusb_syn26989_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26989_GROM,
      O => Ucore_Uusb_syn26992
    );
  Ucore_Uusb_C3679 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(14),
      ADR1 => Ucore_Uusb_Uuc_DPTRO(6),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C331,
      O => Ucore_Uusb_syn26647_FROM
    );
  Ucore_Uusb_C3542 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(8),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C331,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR3 => Ucore_Uusb_Uuc_DPTRO(0),
      O => Ucore_Uusb_syn26647_GROM
    );
  Ucore_Uusb_syn26647_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26647_FROM,
      O => Ucore_Uusb_syn26647
    );
  Ucore_Uusb_syn26647_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26647_GROM,
      O => Ucore_Uusb_syn27011
    );
  Ucore_Uusb_C3526 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      O => Ucore_Uusb_syn7732_FROM
    );
  Ucore_Uusb_C3525 : X_LUT4
    generic map(
      INIT => X"4404"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214,
      ADR3 => Ucore_Uusb_syn7732,
      O => Ucore_Uusb_syn7732_GROM
    );
  Ucore_Uusb_syn7732_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7732_FROM,
      O => Ucore_Uusb_syn7732
    );
  Ucore_Uusb_syn7732_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7732_GROM,
      O => Ucore_Uusb_syn23597
    );
  Ucore_Uusb_C3518 : X_LUT4
    generic map(
      INIT => X"0101"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_FROM
    );
  Ucore_Uusb_C3517 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C569
    );
  Ucore_Uusb_C3457 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N380,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(8),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N54_FROM
    );
  Ucore_Uusb_C3454 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_N383,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(11),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N54_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N54_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N54_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N54
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N54_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N54_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N72
    );
  Ucore_Uusb_C3446 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      ADR1 => Ucore_Uusb_Uusb_Usie_BUS1153(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_FROM
    );
  Ucore_Uusb_C2870 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uglue_bytecount(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_GROM
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_FROM,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3_GROM,
      O => Ucore_Uusb_syn5304
    );
  Ucore_Uusb_C3374 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6514,
      ADR1 => Ucore_Uusb_syn6524,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5316_FROM
    );
  Ucore_Uusb_C3372 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6527,
      ADR1 => Ucore_Uusb_syn6519,
      ADR2 => Ucore_Uusb_syn6779,
      ADR3 => Ucore_Uusb_syn5316,
      O => Ucore_Uusb_syn5316_GROM
    );
  Ucore_Uusb_syn5316_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5316_FROM,
      O => Ucore_Uusb_syn5316
    );
  Ucore_Uusb_syn5316_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5316_GROM,
      O => Ucore_Uusb_Uuc_BWR
    );
  Ucore_Uusb_C3294 : X_LUT4
    generic map(
      INIT => X"5010"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6821,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C487,
      ADR2 => Ucore_Uusb_syn6805,
      ADR3 => Ucore_Uusb_syn27389,
      O => Ucore_Uusb_Uuc_BUFO8_6_FROM
    );
  Ucore_Uusb_C3272 : X_LUT4
    generic map(
      INIT => X"F088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(6),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C763,
      ADR2 => Ucore_Uusb_Uuc_ABUS(6),
      ADR3 => Ucore_Uusb_syn7015,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N59
    );
  Ucore_Uusb_Uuc_BUFO8_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_6_FROM,
      O => Ucore_Uusb_syn7015
    );
  Ucore_Uusb_C3358 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6514,
      ADR3 => Ucore_Uusb_syn6524,
      O => Ucore_Uusb_syn5315_FROM
    );
  Ucore_Uusb_C3297 : X_LUT4
    generic map(
      INIT => X"0B03"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6527,
      ADR1 => Ucore_Uusb_syn6779,
      ADR2 => Ucore_Uusb_syn6519,
      ADR3 => Ucore_Uusb_syn5315,
      O => Ucore_Uusb_syn5315_GROM
    );
  Ucore_Uusb_syn5315_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5315_FROM,
      O => Ucore_Uusb_syn5315
    );
  Ucore_Uusb_syn5315_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5315_GROM,
      O => Ucore_Uusb_Uuc_SPWR
    );
  Ucore_Uusb_C2910 : X_LUT4
    generic map(
      INIT => X"030C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc(15),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FROM
    );
  Ucore_Uusb_C2890 : X_LUT4
    generic map(
      INIT => X"7FBF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(15),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0),
      ADR3 => Ucore_Uusb_syn8063,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N81
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FROM,
      O => Ucore_Uusb_syn8063
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2822 : X_LUT4
    generic map(
      INIT => X"F8FF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      O => Ucore_Uusb_syn28539_FROM
    );
  Ucore_Uusb_C2821 : X_LUT4
    generic map(
      INIT => X"FF1F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR3 => Ucore_Uusb_syn28539,
      O => Ucore_Uusb_syn28539_GROM
    );
  Ucore_Uusb_syn28539_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28539_FROM,
      O => Ucore_Uusb_syn28539
    );
  Ucore_Uusb_syn28539_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28539_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21
    );
  Ucore_Uusb_C2829 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_FROM
    );
  Ucore_Uusb_C2814 : X_LUT4
    generic map(
      INIT => X"050A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312_GROM,
      O => Ucore_Uusb_syn28560
    );
  Ucore_Uusb_C2806 : X_LUT4
    generic map(
      INIT => X"0044"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR1 => vp_p10_c,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_FROM
    );
  Ucore_Uusb_C2805 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0),
      ADR1 => Ucore_urx0,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C6_C0_GROM,
      O => Ucore_Uusb_syn5329
    );
  Ucore_Ufunc_high_temp2_fast_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_high_temp2_fast_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3709 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => Ucore_Uusb_syn5659,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_Uuc_Udmux_C331_FROM
    );
  Ucore_Uusb_C3703 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => Ucore_Uusb_syn5659,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_Uuc_Udmux_C331_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C331_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C331_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C331
    );
  Ucore_Uusb_Uuc_Udmux_C331_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C331_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C351
    );
  Ucore_Uusb_C3783 : X_LUT4
    generic map(
      INIT => X"0F96"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5697,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C447_C18,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(2),
      O => Ucore_Uusb_syn23133_FROM
    );
  Ucore_Uusb_C3631 : X_LUT4
    generic map(
      INIT => X"6090"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C447_C18,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR3 => Ucore_Uusb_syn5697,
      O => Ucore_Uusb_syn23133_GROM
    );
  Ucore_Uusb_syn23133_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23133_FROM,
      O => Ucore_Uusb_syn23133
    );
  Ucore_Uusb_syn23133_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23133_GROM,
      O => Ucore_Uusb_syn6176
    );
  Ucore_Uusb_C3623 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6007,
      ADR1 => Ucore_Uusb_syn26789,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR3 => Ucore_Uusb_syn6176,
      O => Ucore_Uusb_syn26791_FROM
    );
  Ucore_Uusb_C3622 : X_LUT4
    generic map(
      INIT => X"FF90"
    )
    port map (
      ADR0 => Ucore_Uusb_syn23133,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C424_C2_C5,
      ADR2 => Ucore_Uusb_syn6004,
      ADR3 => Ucore_Uusb_syn26791,
      O => Ucore_Uusb_syn26791_GROM
    );
  Ucore_Uusb_syn26791_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26791_FROM,
      O => Ucore_Uusb_syn26791
    );
  Ucore_Uusb_syn26791_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26791_GROM,
      O => Ucore_Uusb_syn6177
    );
  Ucore_Uusb_C3677 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C345,
      ADR1 => Ucore_Uusb_Uuc_PO(6),
      ADR2 => Ucore_Uusb_Uuc_SPO(6),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C351,
      O => Ucore_Uusb_syn26649_FROM
    );
  Ucore_Uusb_C3615 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_SPO(3),
      ADR1 => Ucore_Uusb_Uuc_PO(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C345,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C351,
      O => Ucore_Uusb_syn26649_GROM
    );
  Ucore_Uusb_syn26649_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26649_FROM,
      O => Ucore_Uusb_syn26649
    );
  Ucore_Uusb_syn26649_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26649_GROM,
      O => Ucore_Uusb_syn26810
    );
  Ucore_Uusb_C3535 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_FROM
    );
  Ucore_Uusb_C3505 : X_LUT4
    generic map(
      INIT => X"135F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C191_GROM,
      O => Ucore_Uusb_syn27093
    );
  Ucore_Uusb_C3527 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_FROM
    );
  Ucore_Uusb_C3521 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C458_GROM,
      O => Ucore_Uusb_syn23598
    );
  Ucore_Uusb_C3456 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR1 => Ucore_Uusb_Uuc_Ubuf_N381,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(9),
      O => Ucore_Uusb_Uuc_Ubuf_C380_N60_FROM
    );
  Ucore_Uusb_C3455 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ubuf_relf,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(10),
      ADR2 => Ucore_Uusb_Uuc_Ubuf_N382,
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N60_GROM
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N60_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N60_FROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N60
    );
  Ucore_Uusb_Uuc_Ubuf_C380_N60_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C380_N60_GROM,
      O => Ucore_Uusb_Uuc_Ubuf_C380_N66
    );
  Ucore_Uusb_C3439 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5544,
      ADR1 => Ucore_Uusb_syn6607,
      ADR2 => Ucore_Uusb_BUS141(0),
      ADR3 => Ucore_Uusb_BUS141(1),
      O => Ucore_Uusb_Uglue_C0_N39_FROM
    );
  Ucore_Uusb_C3447 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6607,
      ADR1 => Ucore_Uusb_BUS141(1),
      ADR2 => Ucore_Uusb_syn5544,
      ADR3 => Ucore_Uusb_BUS141(0),
      O => Ucore_Uusb_Uglue_C0_N39_GROM
    );
  Ucore_Uusb_Uglue_C0_N39_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C0_N39_FROM,
      O => Ucore_Uusb_Uglue_C0_N39
    );
  Ucore_Uusb_Uglue_C0_N39_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C0_N39_GROM,
      O => Ucore_Uusb_Uglue_C0_N64
    );
  Ucore_Uusb_C3383 : X_LUT4
    generic map(
      INIT => X"A3E0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FROM
    );
  Ucore_Uusb_C3377 : X_LUT4
    generic map(
      INIT => X"6A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR3 => Ucore_Uusb_syn6739,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N15
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FROM,
      O => Ucore_Uusb_syn6739
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3367 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_syn5309_FROM
    );
  Ucore_Uusb_C3366 : X_LUT4
    generic map(
      INIT => X"13FF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(2),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(1),
      ADR3 => Ucore_Uusb_syn5309,
      O => Ucore_Uusb_syn5309_GROM
    );
  Ucore_Uusb_syn5309_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5309_FROM,
      O => Ucore_Uusb_syn5309
    );
  Ucore_Uusb_syn5309_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5309_GROM,
      O => Ucore_Uusb_syn27376
    );
  Ucore_Uusb_C3295 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6519,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn6524,
      ADR3 => Ucore_Uusb_syn6527,
      O => Ucore_Uusb_Uuc_Udmux_C755_FROM
    );
  Ucore_Uusb_C3287 : X_LUT4
    generic map(
      INIT => X"E2C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DBUS(0),
      ADR1 => Ucore_Uusb_syn7015,
      ADR2 => Ucore_Uusb_Uuc_ABUS(8),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C755,
      O => Ucore_Uusb_Uuc_Udmux_C755_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C755_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C755_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C755
    );
  Ucore_Uusb_Uuc_Udmux_C755_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C755_GROM,
      O => Ucore_Uusb_syn27574
    );
  Ucore_Uusb_C3199 : X_LUT4
    generic map(
      INIT => X"0A08"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR1 => Ucore_Uusb_syn27752,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(2),
      ADR3 => Ucore_Uusb_syn27751,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FROM
    );
  Ucore_Uusb_C3186 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5302,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5327,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uuop_C765,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C765
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2474
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2917 : X_LUT4
    generic map(
      INIT => X"A6A6"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_FROM
    );
  Ucore_Uusb_C2911 : X_LUT4
    generic map(
      INIT => X"00E7"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR3 => Ucore_Uusb_syn6629,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C1_N6
    );
  Ucore_Uusb_C2831 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5349_FROM
    );
  Ucore_Uusb_C2819 : X_LUT4
    generic map(
      INIT => X"A020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s,
      ADR3 => Ucore_Uusb_syn5349,
      O => Ucore_Uusb_syn5349_GROM
    );
  Ucore_Uusb_syn5349_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5349_FROM,
      O => Ucore_Uusb_syn5349
    );
  Ucore_Uusb_syn5349_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5349_GROM,
      O => Ucore_Uusb_syn8374
    );
  Ucore_Uusb_C2823 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_FROM
    );
  Ucore_Uusb_C2818 : X_LUT4
    generic map(
      INIT => X"0501"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C308_GROM,
      O => Ucore_Uusb_syn24763
    );
  Ucore_Uusb_C2807 : X_LUT4
    generic map(
      INIT => X"5545"
    )
    port map (
      ADR0 => Ucore_urx0,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR2 => vp_p10_c,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_FROM
    );
  Ucore_Uusb_C2792 : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_S_8_cell0_GROM,
      O => Ucore_Uusb_syn28608
    );
  Ucore_Uusb_C3800 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5293_FROM
    );
  Ucore_Uusb_C3749 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => Ucore_Uusb_syn5293,
      O => Ucore_Uusb_syn5293_GROM
    );
  Ucore_Uusb_syn5293_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5293_FROM,
      O => Ucore_Uusb_syn5293
    );
  Ucore_Uusb_syn5293_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5293_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C593
    );
  Ucore_Uusb_C3801 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5653,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => Ucore_Uusb_syn5664,
      ADR3 => Ucore_Uusb_syn5659,
      O => Ucore_Uusb_Uuc_Udmux_C353_FROM
    );
  Ucore_Uusb_C3720 : X_LUT4
    generic map(
      INIT => X"000C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn5664,
      ADR2 => Ucore_Uusb_syn5653,
      ADR3 => Ucore_Uusb_syn5659,
      O => Ucore_Uusb_Uuc_Udmux_C353_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C353_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C353_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C353
    );
  Ucore_Uusb_Uuc_Udmux_C353_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C353_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C317
    );
  Ucore_Uusb_C3712 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR3 => VCC,
      O => Ucore_Uusb_syn26313_FROM
    );
  Ucore_Uusb_C3711 : X_LUT4
    generic map(
      INIT => X"EE40"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR1 => Ucore_Uusb_syn5945,
      ADR2 => Ucore_Uusb_syn26313,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      O => Ucore_Uusb_syn26313_GROM
    );
  Ucore_Uusb_syn26313_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26313_FROM,
      O => Ucore_Uusb_syn26313
    );
  Ucore_Uusb_syn26313_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26313_GROM,
      O => Ucore_Uusb_syn5952
    );
  Ucore_Uusb_C3661 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(13),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C325,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C319,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_BUS15211(5),
      O => Ucore_Uusb_syn26697_FROM
    );
  Ucore_Uusb_C3640 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(12),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_BUS15211(4),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C325,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C319,
      O => Ucore_Uusb_syn26697_GROM
    );
  Ucore_Uusb_syn26697_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26697_FROM,
      O => Ucore_Uusb_syn26697
    );
  Ucore_Uusb_syn26697_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26697_GROM,
      O => Ucore_Uusb_syn26753
    );
  Ucore_Uusb_C3678 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(6),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR3 => Ucore_Uusb_Uuc_RO(6),
      O => Ucore_Uusb_syn26648_FROM
    );
  Ucore_Uusb_C3616 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR3 => Ucore_Uusb_Uuc_RO(3),
      O => Ucore_Uusb_syn26648_GROM
    );
  Ucore_Uusb_syn26648_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26648_FROM,
      O => Ucore_Uusb_syn26648
    );
  Ucore_Uusb_syn26648_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26648_GROM,
      O => Ucore_Uusb_syn26809
    );
  Ucore_Uusb_C3608 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR1 => Ucore_Uusb_syn5310,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR3 => Ucore_Uusb_Uuc_Ualu_C665,
      O => Ucore_Uusb_syn26837_FROM
    );
  Ucore_Uusb_C3607 : X_LUT4
    generic map(
      INIT => X"FFE0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26824,
      ADR1 => Ucore_Uusb_syn6158,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(2),
      ADR3 => Ucore_Uusb_syn26837,
      O => Ucore_Uusb_syn26837_GROM
    );
  Ucore_Uusb_syn26837_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26837_FROM,
      O => Ucore_Uusb_syn26837
    );
  Ucore_Uusb_syn26837_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26837_GROM,
      O => Ucore_Uusb_syn26838
    );
  Ucore_Uusb_C3544 : X_LUT4
    generic map(
      INIT => X"D800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5952,
      ADR1 => Ucore_Uusb_Uuc_Uport0_pad(0),
      ADR2 => Ucore_Uusb_BUS131(0),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C339,
      O => Ucore_Uusb_syn27015_FROM
    );
  Ucore_Uusb_C3543 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn27009,
      ADR2 => Ucore_Uusb_syn27010,
      ADR3 => Ucore_Uusb_syn27015,
      O => Ucore_Uusb_syn27015_GROM
    );
  Ucore_Uusb_syn27015_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27015_FROM,
      O => Ucore_Uusb_syn27015
    );
  Ucore_Uusb_syn27015_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27015_GROM,
      O => Ucore_Uusb_syn27019
    );
  Ucore_Uusb_C3528 : X_LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_FROM
    );
  Ucore_Uusb_C3364 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214,
      O => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214
    );
  Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uactrl_C214_GROM,
      O => Ucore_Uusb_syn6818
    );
  Ucore_Uusb_C3448 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS1610_14_Q,
      ADR1 => Ucore_Uusb_BUS1610_12_Q,
      ADR2 => Ucore_Uusb_BUS1610_13_Q,
      ADR3 => Ucore_Uusb_BUS1610_15_Q,
      O => Ucore_Uusb_syn6607_FROM
    );
  Ucore_Uusb_C2768 : X_LUT4
    generic map(
      INIT => X"AAFF"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS141(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6607,
      O => Ucore_Uusb_syn6607_GROM
    );
  Ucore_Uusb_syn6607_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6607_FROM,
      O => Ucore_Uusb_syn6607
    );
  Ucore_Uusb_syn6607_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6607_GROM,
      O => Ucore_Uusb_Uglue_N101
    );
  Ucore_Uusb_C3376 : X_LUT4
    generic map(
      INIT => X"33FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FROM
    );
  Ucore_Uusb_C3375 : X_LUT4
    generic map(
      INIT => X"8828"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6739,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(3),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2),
      ADR3 => Ucore_Uusb_syn23827,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N20
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FROM,
      O => Ucore_Uusb_syn23827
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3296 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6527,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn6524,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_Uuc_BUFO8_0_FROM
    );
  Ucore_Uusb_C3270 : X_LUT4
    generic map(
      INIT => X"ACA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ABUS(0),
      ADR1 => Ucore_Uusb_Uuc_DBUS(0),
      ADR2 => Ucore_Uusb_syn7015,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C763,
      O => Ucore_Uusb_Uuc_Ubuf_C1_N11
    );
  Ucore_Uusb_Uuc_BUFO8_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUFO8_0_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C763
    );
  Ucore_Uusb_C2840 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FROM
    );
  Ucore_Uusb_C2835 : X_LUT4
    generic map(
      INIT => X"4800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C1_C0,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(1),
      ADR3 => Ucore_Uusb_syn8070,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N9
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FROM,
      O => Ucore_Uusb_syn8070
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3705 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5659,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => Ucore_Uusb_syn5653,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_Uuc_Udmux_C333_FROM
    );
  Ucore_Uusb_C3581 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(1),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR2 => Ucore_Uusb_Uuc_RO(1),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C333,
      O => Ucore_Uusb_Uuc_Udmux_C333_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C333_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C333_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C333
    );
  Ucore_Uusb_Uuc_Udmux_C333_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C333_GROM,
      O => Ucore_Uusb_syn26908
    );
  Ucore_Uusb_C3662 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_OP2(5),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR3 => Ucore_Uusb_Uuc_OP3(5),
      O => Ucore_Uusb_syn26696_FROM
    );
  Ucore_Uusb_C3641 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR1 => Ucore_Uusb_Uuc_OP2(4),
      ADR2 => Ucore_Uusb_Uuc_OP3(4),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C313,
      O => Ucore_Uusb_syn26696_GROM
    );
  Ucore_Uusb_syn26696_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26696_FROM,
      O => Ucore_Uusb_syn26696
    );
  Ucore_Uusb_syn26696_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26696_GROM,
      O => Ucore_Uusb_syn26752
    );
  Ucore_Uusb_C3625 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5341,
      ADR1 => Ucore_Uusb_syn26785,
      ADR2 => Ucore_Uusb_syn5322,
      ADR3 => Ucore_Uusb_syn26786,
      O => Ucore_Uusb_syn26788_FROM
    );
  Ucore_Uusb_C3624 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6162,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(3),
      ADR3 => Ucore_Uusb_syn26788,
      O => Ucore_Uusb_syn26788_GROM
    );
  Ucore_Uusb_syn26788_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26788_FROM,
      O => Ucore_Uusb_syn26788
    );
  Ucore_Uusb_syn26788_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26788_GROM,
      O => Ucore_Uusb_syn26789
    );
  Ucore_Uusb_C3659 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(5),
      ADR2 => Ucore_Uusb_Uuc_BUFO8(13),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C331,
      O => Ucore_Uusb_syn26698_FROM
    );
  Ucore_Uusb_C3617 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(11),
      ADR1 => Ucore_Uusb_Uuc_DPTRO(3),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C331,
      O => Ucore_Uusb_syn26698_GROM
    );
  Ucore_Uusb_syn26698_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26698_FROM,
      O => Ucore_Uusb_syn26698
    );
  Ucore_Uusb_syn26698_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26698_GROM,
      O => Ucore_Uusb_syn26808
    );
  Ucore_Uusb_C3734 : X_LUT4
    generic map(
      INIT => X"7700"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5913,
      O => Ucore_Uusb_syn5190_FROM
    );
  Ucore_Uusb_C3609 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR1 => Ucore_Uusb_syn5342,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR3 => Ucore_Uusb_syn5913,
      O => Ucore_Uusb_syn5190_GROM
    );
  Ucore_Uusb_syn5190_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5190_FROM,
      O => Ucore_Uusb_syn5190
    );
  Ucore_Uusb_syn5190_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5190_GROM,
      O => Ucore_Uusb_syn26824
    );
  Ucore_Uusb_C3561 : X_LUT4
    generic map(
      INIT => X"FE32"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26961,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => Ucore_Uusb_syn26960,
      ADR3 => Ucore_Uusb_syn6329,
      O => Ucore_Uusb_syn23519_FROM
    );
  Ucore_Uusb_C3560 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5324,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn23519,
      O => Ucore_Uusb_syn23519_GROM
    );
  Ucore_Uusb_syn23519_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23519_FROM,
      O => Ucore_Uusb_syn23519
    );
  Ucore_Uusb_syn23519_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23519_GROM,
      O => Ucore_Uusb_syn23522
    );
  Ucore_Uusb_C3468 : X_LUT4
    generic map(
      INIT => X"1BFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C464,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_syn6805_FROM
    );
  Ucore_Uusb_C3369 : X_LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_syn6805_GROM
    );
  Ucore_Uusb_syn6805_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6805_FROM,
      O => Ucore_Uusb_syn6805
    );
  Ucore_Uusb_syn6805_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6805_GROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C153
    );
  Ucore_Uusb_C2833 : X_LUT4
    generic map(
      INIT => X"6A6A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FROM
    );
  Ucore_Uusb_C2832 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8070,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2,
      ADR2 => Ucore_Uusb_syn24588,
      ADR3 => Ucore_Uusb_syn26137,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N15
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FROM,
      O => Ucore_Uusb_syn26137
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2825 : X_LUT4
    generic map(
      INIT => X"FEFC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      ADR1 => Ucore_Uusb_syn28530,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FROM
    );
  Ucore_Uusb_C2824 : X_LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C328,
      ADR2 => Ucore_Uusb_syn28531,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C312,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N48
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FROM,
      O => Ucore_Uusb_syn28531
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2817 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s,
      ADR3 => Ucore_Uusb_syn24763,
      O => Ucore_Uusb_syn28551_FROM
    );
  Ucore_Uusb_C2816 : X_LUT4
    generic map(
      INIT => X"FF8A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1),
      ADR1 => Ucore_Uusb_syn8374,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      ADR3 => Ucore_Uusb_syn28551,
      O => Ucore_Uusb_syn28551_GROM
    );
  Ucore_Uusb_syn28551_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28551_FROM,
      O => Ucore_Uusb_syn28551
    );
  Ucore_Uusb_syn28551_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28551_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C25_N12
    );
  Ucore_Uusb_C3802 : X_LUT4
    generic map(
      INIT => X"70F0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5608,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR2 => Ucore_Uusb_syn26290,
      ADR3 => Ucore_Uusb_syn5624,
      O => Ucore_Uusb_syn5664_FROM
    );
  Ucore_Uusb_C3699 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5653,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5659,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_syn5664_GROM
    );
  Ucore_Uusb_syn5664_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5664_FROM,
      O => Ucore_Uusb_syn5664
    );
  Ucore_Uusb_syn5664_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5664_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C357
    );
  Ucore_Uusb_C3688 : X_LUT4
    generic map(
      INIT => X"AAFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(1),
      O => Ucore_Uusb_syn5342_FROM
    );
  Ucore_Uusb_C3730 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(1),
      O => Ucore_Uusb_syn5342_GROM
    );
  Ucore_Uusb_syn5342_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5342_FROM,
      O => Ucore_Uusb_syn5342
    );
  Ucore_Uusb_syn5342_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5342_GROM,
      O => Ucore_Uusb_syn5322
    );
  Ucore_Uusb_C3722 : X_LUT4
    generic map(
      INIT => X"0CC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C433_C2_C5,
      ADR3 => Ucore_Uusb_syn26076,
      O => Ucore_Uusb_syn27492_FROM
    );
  Ucore_Uusb_C3721 : X_LUT4
    generic map(
      INIT => X"F3F2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C683,
      ADR1 => Ucore_Uusb_syn20388,
      ADR2 => Ucore_Uusb_syn26580,
      ADR3 => Ucore_Uusb_syn27492,
      O => Ucore_Uusb_syn27492_GROM
    );
  Ucore_Uusb_syn27492_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27492_FROM,
      O => Ucore_Uusb_syn27492
    );
  Ucore_Uusb_syn27492_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27492_GROM,
      O => Ucore_Uusb_syn26582
    );
  Ucore_Uusb_C3714 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5659,
      ADR1 => Ucore_Uusb_syn5664,
      ADR2 => Ucore_Uusb_syn5653,
      ADR3 => Ucore_Uusb_syn5632,
      O => Ucore_Uusb_Uuc_Udmux_C339_FROM
    );
  Ucore_Uusb_C3583 : X_LUT4
    generic map(
      INIT => X"B800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uport0_pad(1),
      ADR1 => Ucore_Uusb_syn5952,
      ADR2 => Ucore_Uusb_BUS131(1),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C339,
      O => Ucore_Uusb_Uuc_Udmux_C339_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C339_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C339_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C339
    );
  Ucore_Uusb_Uuc_Udmux_C339_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C339_GROM,
      O => Ucore_Uusb_syn26911
    );
  Ucore_Uusb_C3717 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5659,
      ADR1 => Ucore_Uusb_syn5664,
      ADR2 => Ucore_Uusb_syn5632,
      ADR3 => Ucore_Uusb_syn5653,
      O => Ucore_Uusb_Uuc_Udmux_C325_FROM
    );
  Ucore_Uusb_C3706 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5653,
      ADR1 => Ucore_Uusb_syn5659,
      ADR2 => Ucore_Uusb_syn5632,
      ADR3 => Ucore_Uusb_syn5664,
      O => Ucore_Uusb_Uuc_Udmux_C325_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C325_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C325_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C325
    );
  Ucore_Uusb_Uuc_Udmux_C325_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C325_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C341
    );
  Ucore_Uusb_C3642 : X_LUT4
    generic map(
      INIT => X"FF84"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26082,
      ADR1 => Ucore_Uusb_syn6004,
      ADR2 => Ucore_Uusb_syn23149,
      ADR3 => Ucore_Uusb_syn26737,
      O => Ucore_Uusb_Uuc_SPO_4_FROM
    );
  Ucore_Uusb_C3632 : X_LUT4
    generic map(
      INIT => X"FEEE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26763,
      ADR1 => Ucore_Uusb_syn26762,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR3 => Ucore_Uusb_syn6127,
      O => Ucore_Uusb_Uuc_SPO_4_GROM
    );
  Ucore_Uusb_Uuc_SPO_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_4_FROM,
      O => Ucore_Uusb_syn6127
    );
  Ucore_Uusb_Uuc_SPO_4_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_4_GROM,
      O => Ucore_Uusb_Uuc_DBUS(4)
    );
  Ucore_Uusb_Uuc_SPO_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3634 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BO(4),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR2 => Ucore_Uusb_Uuc_AO(4),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C357,
      O => Ucore_Uusb_syn26757_FROM
    );
  Ucore_Uusb_C3633 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26756,
      ADR1 => Ucore_Uusb_syn26754,
      ADR2 => Ucore_Uusb_syn26755,
      ADR3 => Ucore_Uusb_syn26757,
      O => Ucore_Uusb_syn26757_GROM
    );
  Ucore_Uusb_syn26757_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26757_FROM,
      O => Ucore_Uusb_syn26757
    );
  Ucore_Uusb_syn26757_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26757_GROM,
      O => Ucore_Uusb_syn26763
    );
  Ucore_Uusb_C3557 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10875(6),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(7),
      O => Ucore_Uusb_syn26932_FROM
    );
  Ucore_Uusb_C3626 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(3),
      ADR1 => Ucore_Uusb_syn5310,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR3 => Ucore_Uusb_syn6110,
      O => Ucore_Uusb_syn26932_GROM
    );
  Ucore_Uusb_syn26932_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26932_FROM,
      O => Ucore_Uusb_syn26932
    );
  Ucore_Uusb_syn26932_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26932_GROM,
      O => Ucore_Uusb_syn26786
    );
  Ucore_Uusb_C3570 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR3 => Ucore_Uusb_Uuc_BUS10881(5),
      O => Ucore_Uusb_syn26980_FROM
    );
  Ucore_Uusb_C3569 : X_LUT4
    generic map(
      INIT => X"3020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26979,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_syn5324,
      ADR3 => Ucore_Uusb_syn26980,
      O => Ucore_Uusb_syn26980_GROM
    );
  Ucore_Uusb_syn26980_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26980_FROM,
      O => Ucore_Uusb_syn26980
    );
  Ucore_Uusb_syn26980_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26980_GROM,
      O => Ucore_Uusb_syn6350
    );
  Ucore_Uusb_C3651 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn6106_FROM
    );
  Ucore_Uusb_C3562 : X_LUT4
    generic map(
      INIT => X"3120"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_Uuc_BUS10875(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(0),
      O => Ucore_Uusb_syn6106_GROM
    );
  Ucore_Uusb_syn6106_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6106_FROM,
      O => Ucore_Uusb_syn6106
    );
  Ucore_Uusb_syn6106_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6106_GROM,
      O => Ucore_Uusb_syn26961
    );
  Ucore_Uusb_C3554 : X_LUT4
    generic map(
      INIT => X"A00A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C603,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(5),
      ADR3 => Ucore_Uusb_Uuc_BUS10881(5),
      O => Ucore_Uusb_syn26931_FROM
    );
  Ucore_Uusb_C3552 : X_LUT4
    generic map(
      INIT => X"9000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_Uuc_BUS10875(0),
      ADR2 => Ucore_Uusb_syn26934,
      ADR3 => Ucore_Uusb_syn26931,
      O => Ucore_Uusb_syn26931_GROM
    );
  Ucore_Uusb_syn26931_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26931_FROM,
      O => Ucore_Uusb_syn26931
    );
  Ucore_Uusb_syn26931_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26931_GROM,
      O => Ucore_Uusb_syn26937
    );
  Ucore_Uusb_C3538 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27014,
      ADR1 => Ucore_Uusb_syn27013,
      ADR2 => Ucore_Uusb_syn27011,
      ADR3 => Ucore_Uusb_syn27012,
      O => Ucore_Uusb_Uuc_SPO_0_FROM
    );
  Ucore_Uusb_C3537 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn27019,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR2 => Ucore_Uusb_syn20073,
      ADR3 => Ucore_Uusb_syn27020,
      O => Ucore_Uusb_Uuc_SPO_0_GROM
    );
  Ucore_Uusb_Uuc_SPO_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_0_FROM,
      O => Ucore_Uusb_syn27020
    );
  Ucore_Uusb_Uuc_SPO_0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_0_GROM,
      O => Ucore_Uusb_Uuc_DBUS(0)
    );
  Ucore_Uusb_Uuc_SPO_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3490 : X_LUT4
    generic map(
      INIT => X"80A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6493,
      ADR1 => Ucore_Uusb_syn6505,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C921,
      ADR3 => Ucore_Uusb_syn6498,
      O => Ucore_Uusb_syn6527_FROM
    );
  Ucore_Uusb_C3290 : X_LUT4
    generic map(
      INIT => X"04FF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6519,
      ADR1 => Ucore_Uusb_syn6514,
      ADR2 => Ucore_Uusb_syn6527,
      ADR3 => Ucore_Uusb_Uuc_Ubuf_N29,
      O => Ucore_Uusb_syn6527_GROM
    );
  Ucore_Uusb_syn6527_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6527_FROM,
      O => Ucore_Uusb_syn6527
    );
  Ucore_Uusb_syn6527_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6527_GROM,
      O => Ucore_Uusb_N1512
    );
  Ucore_Uusb_C3482 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6513,
      ADR1 => Ucore_Uusb_syn6464,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C939,
      O => Ucore_Uusb_syn6519_FROM
    );
  Ucore_Uusb_C3336 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6527,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6519,
      O => Ucore_Uusb_syn6519_GROM
    );
  Ucore_Uusb_syn6519_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6519_FROM,
      O => Ucore_Uusb_syn6519
    );
  Ucore_Uusb_syn6519_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6519_GROM,
      O => Ucore_Uusb_syn5332
    );
  Ucore_Uusb_C2930 : X_LUT4
    generic map(
      INIT => X"00A8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      ADR1 => Ucore_Uusb_syn28299,
      ADR2 => Ucore_Uusb_syn28298,
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      O => Ucore_Uusb_syn8001_FROM
    );
  Ucore_Uusb_C2929 : X_LUT4
    generic map(
      INIT => X"2320"
    )
    port map (
      ADR0 => Ucore_Uusb_DI(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      ADR2 => Ucore_Uusb_Uusb_Usie_BUS1153(7),
      ADR3 => Ucore_Uusb_syn8001,
      O => Ucore_Uusb_syn8001_GROM
    );
  Ucore_Uusb_syn8001_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8001_FROM,
      O => Ucore_Uusb_syn8001
    );
  Ucore_Uusb_syn8001_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8001_GROM,
      O => Ucore_Uusb_syn8006
    );
  Ucore_Uusb_C3386 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_N210,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_C1469,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_out_en,
      ADR3 => Ucore_Uusb_syn6707,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FROM
    );
  Ucore_Uusb_C3385 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_C1465,
      ADR1 => Ucore_Uusb_syn6704,
      ADR2 => Ucore_Uusb_Uusb_in_trac(0),
      ADR3 => Ucore_Uusb_syn27319,
      O => Ucore_Uusb_Uusb_Uep0ctrl_C38_N40
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FROM,
      O => Ucore_Uusb_syn27319
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2922 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(3),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FROM
    );
  Ucore_Uusb_C2921 : X_LUT4
    generic map(
      INIT => X"A888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR2 => Ucore_Uusb_syn28318,
      ADR3 => Ucore_Uusb_syn28319,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N27
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FROM,
      O => Ucore_Uusb_syn28319
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2914 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn8037,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C604_C6,
      ADR3 => Ucore_Uusb_syn8044,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FROM
    );
  Ucore_Uusb_C2913 : X_LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR1 => Ucore_Uusb_syn8037,
      ADR2 => Ucore_Uusb_Uusb_Usie_Uepdec_C603_C6,
      ADR3 => Ucore_Uusb_syn28337,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N20
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FROM,
      O => Ucore_Uusb_syn28337
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2770 : X_LUT4
    generic map(
      INIT => X"0202"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6607,
      ADR1 => Ucore_Uusb_BUS141(0),
      ADR2 => Ucore_Uusb_BUS141(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uglue_cell17_FROM
    );
  Ucore_Uusb_C2761 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_din(0),
      ADR1 => VCC,
      ADR2 => Ucore_din(8),
      ADR3 => Ucore_Uusb_Uglue_cell17,
      O => Ucore_Uusb_Uglue_cell17_GROM
    );
  Ucore_Uusb_Uglue_cell17_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_cell17_FROM,
      O => Ucore_Uusb_Uglue_cell17
    );
  Ucore_Uusb_Uglue_cell17_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_cell17_GROM,
      O => Ucore_Uusb_Uglue_C36_N6
    );
  Ucore_Uusb_C2769 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_din(9),
      ADR1 => Ucore_din(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uglue_cell17,
      O => Ucore_Uusb_Uglue_C36_N12_FROM
    );
  Ucore_Uusb_C2762 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_din(12),
      ADR2 => Ucore_din(4),
      ADR3 => Ucore_Uusb_Uglue_cell17,
      O => Ucore_Uusb_Uglue_C36_N12_GROM
    );
  Ucore_Uusb_Uglue_C36_N12_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N12_FROM,
      O => Ucore_Uusb_Uglue_C36_N12
    );
  Ucore_Uusb_Uglue_C36_N12_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N12_GROM,
      O => Ucore_Uusb_Uglue_C36_N30
    );
  Ucore_Ufunc_high_temp2_fast_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_high_temp2_fast_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3657 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(5),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR2 => Ucore_Uusb_Uuc_SPO(5),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C345,
      O => Ucore_Uusb_syn26700_FROM
    );
  Ucore_Uusb_C3635 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(4),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR2 => Ucore_Uusb_Uuc_SPO(4),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C345,
      O => Ucore_Uusb_syn26700_GROM
    );
  Ucore_Uusb_syn26700_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26700_FROM,
      O => Ucore_Uusb_syn26700
    );
  Ucore_Uusb_syn26700_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26700_GROM,
      O => Ucore_Uusb_syn26756
    );
  Ucore_Uusb_C3725 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR2 => Ucore_Uusb_syn5340,
      ADR3 => Ucore_Uusb_syn5322,
      O => Ucore_Uusb_syn26578_FROM
    );
  Ucore_Uusb_C3627 : X_LUT4
    generic map(
      INIT => X"DC50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(7),
      O => Ucore_Uusb_syn26578_GROM
    );
  Ucore_Uusb_syn26578_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26578_FROM,
      O => Ucore_Uusb_syn26578
    );
  Ucore_Uusb_syn26578_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26578_GROM,
      O => Ucore_Uusb_syn26785
    );
  Ucore_Uusb_C3619 : X_LUT4
    generic map(
      INIT => X"A088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR1 => Ucore_Uusb_BUS131(3),
      ADR2 => Ucore_Uusb_Uuc_Uport0_pad(3),
      ADR3 => Ucore_Uusb_syn5952,
      O => Ucore_Uusb_syn26812_FROM
    );
  Ucore_Uusb_C3618 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn26806,
      ADR2 => Ucore_Uusb_syn26807,
      ADR3 => Ucore_Uusb_syn26812,
      O => Ucore_Uusb_syn26812_GROM
    );
  Ucore_Uusb_syn26812_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26812_FROM,
      O => Ucore_Uusb_syn26812
    );
  Ucore_Uusb_syn26812_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26812_GROM,
      O => Ucore_Uusb_syn26816
    );
  Ucore_Uusb_C3687 : X_LUT4
    generic map(
      INIT => X"F300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR3 => Ucore_Uusb_syn5913,
      O => Ucore_Uusb_syn5191_FROM
    );
  Ucore_Uusb_C3571 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR3 => Ucore_Uusb_Uuc_BUS10881(2),
      O => Ucore_Uusb_syn5191_GROM
    );
  Ucore_Uusb_syn5191_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5191_FROM,
      O => Ucore_Uusb_syn5191
    );
  Ucore_Uusb_syn5191_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5191_GROM,
      O => Ucore_Uusb_syn26979
    );
  Ucore_Uusb_C3539 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C357,
      ADR1 => Ucore_Uusb_Uuc_BO(0),
      ADR2 => Ucore_Uusb_Uuc_AO(0),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C359,
      O => Ucore_Uusb_syn27014_GROM
    );
  Ucore_Uusb_syn27014_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27014_GROM,
      O => Ucore_Uusb_syn27014
    );
  Ucore_Uusb_C3467 : X_LUT4
    generic map(
      INIT => X"A5C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_syn27151_FROM
    );
  Ucore_Uusb_C3466 : X_LUT4
    generic map(
      INIT => X"FF22"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6532,
      ADR1 => Ucore_Uusb_syn6805,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn27151,
      O => Ucore_Uusb_syn27151_GROM
    );
  Ucore_Uusb_syn27151_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27151_FROM,
      O => Ucore_Uusb_syn27151
    );
  Ucore_Uusb_syn27151_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27151_GROM,
      O => Ucore_Uusb_Uuc_ASEL(0)
    );
  Ucore_Uusb_C3299 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_FROM
    );
  Ucore_Uusb_C3068 : X_LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491_GROM,
      O => Ucore_Uusb_syn7644
    );
  Ucore_Uusb_C3848 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2),
      ADR2 => Ucore_Uusb_BUS141(2),
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_BUS59_2_FROM
    );
  Ucore_Uusb_C2931 : X_LUT4
    generic map(
      INIT => X"7DBE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(3),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_n(2),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_n(3),
      O => Ucore_Uusb_Uusb_BUS59_2_GROM
    );
  Ucore_Uusb_Uusb_BUS59_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_2_FROM,
      O => Ucore_Uusb_Uusb_BUS59(2)
    );
  Ucore_Uusb_Uusb_BUS59_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_2_GROM,
      O => Ucore_Uusb_syn28299
    );
  Ucore_Uusb_C2867 : X_LUT4
    generic map(
      INIT => X"B830"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      O => Ucore_Uusb_syn28418_FROM
    );
  Ucore_Uusb_C2923 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(1),
      O => Ucore_Uusb_syn28418_GROM
    );
  Ucore_Uusb_syn28418_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28418_FROM,
      O => Ucore_Uusb_syn28418
    );
  Ucore_Uusb_syn28418_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28418_GROM,
      O => Ucore_Uusb_syn28318
    );
  Ucore_Uusb_C2915 : X_LUT4
    generic map(
      INIT => X"0B08"
    )
    port map (
      ADR0 => Ucore_Uusb_TI(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_BUS1153(7),
      ADR2 => Ucore_Uusb_Uusb_Usie_BUS1153(8),
      ADR3 => Ucore_Uusb_Uusb_TG(0),
      O => Ucore_Uusb_syn8044_GROM
    );
  Ucore_Uusb_syn8044_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8044_GROM,
      O => Ucore_Uusb_syn8044
    );
  Ucore_Uusb_C2907 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => Ucore_Uusb_syn24588,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(1),
      O => Ucore_Uusb_syn8079_FROM
    );
  Ucore_Uusb_C2906 : X_LUT4
    generic map(
      INIT => X"0044"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn8079,
      O => Ucore_Uusb_syn8079_GROM
    );
  Ucore_Uusb_syn8079_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8079_FROM,
      O => Ucore_Uusb_syn8079
    );
  Ucore_Uusb_syn8079_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8079_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0
    );
  Ucore_Uusb_C2851 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5303,
      ADR1 => Ucore_din(6),
      ADR2 => Ucore_din(14),
      ADR3 => Ucore_Uusb_syn5304,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FROM
    );
  Ucore_Uusb_C2850 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5164,
      ADR1 => Ucore_Uusb_Uusb_BUS8585(6),
      ADR2 => Ucore_Uusb_syn28463,
      ADR3 => Ucore_Uusb_syn28465,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N42
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FROM,
      O => Ucore_Uusb_syn28465
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2827 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2),
      O => Ucore_Uusb_syn8331_FROM
    );
  Ucore_Uusb_C2826 : X_LUT4
    generic map(
      INIT => X"FE0E"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR3 => Ucore_Uusb_syn8331,
      O => Ucore_Uusb_syn8331_GROM
    );
  Ucore_Uusb_syn8331_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8331_FROM,
      O => Ucore_Uusb_syn8331
    );
  Ucore_Uusb_syn8331_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8331_GROM,
      O => Ucore_Uusb_syn28530
    );
  Ucore_Uusb_C2767 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uglue_cell17,
      ADR2 => Ucore_din(5),
      ADR3 => Ucore_din(13),
      O => Ucore_Uusb_Uglue_C36_N36_FROM
    );
  Ucore_Uusb_C2763 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uglue_cell17,
      ADR2 => Ucore_din(14),
      ADR3 => Ucore_din(6),
      O => Ucore_Uusb_Uglue_C36_N36_GROM
    );
  Ucore_Uusb_Uglue_C36_N36_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N36_FROM,
      O => Ucore_Uusb_Uglue_C36_N36
    );
  Ucore_Uusb_Uglue_C36_N36_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N36_GROM,
      O => Ucore_Uusb_Uglue_C36_N42
    );
  Ucore_Uusb_C3820 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_AO(0),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(0),
      O => Ucore_Uusb_Uuc_BUS10875_0_FROM
    );
  Ucore_Uusb_C3795 : X_LUT4
    generic map(
      INIT => X"A08A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(0),
      O => Ucore_Uusb_Uuc_BUS10875_0_GROM
    );
  Ucore_Uusb_Uuc_BUS10875_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_0_FROM,
      O => Ucore_Uusb_Uuc_BUS10875(0)
    );
  Ucore_Uusb_Uuc_BUS10875_0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_0_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C419_C0_C4
    );
  Ucore_Uusb_C3804 : X_LUT4
    generic map(
      INIT => X"8C00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5608,
      ADR1 => Ucore_Uusb_syn5652,
      ADR2 => Ucore_Uusb_Uuc_DSEL(2),
      ADR3 => Ucore_Uusb_syn26306,
      O => Ucore_Uusb_syn5659_FROM
    );
  Ucore_Uusb_C3700 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5653,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5659,
      O => Ucore_Uusb_syn5659_GROM
    );
  Ucore_Uusb_syn5659_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5659_FROM,
      O => Ucore_Uusb_syn5659
    );
  Ucore_Uusb_syn5659_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5659_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C359
    );
  Ucore_Uusb_C3740 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5292,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(1),
      O => Ucore_Uusb_Uuc_Ualu_C683_FROM
    );
  Ucore_Uusb_C3694 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C683,
      O => Ucore_Uusb_Uuc_Ualu_C683_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C683_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C683_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C683
    );
  Ucore_Uusb_Uuc_Ualu_C683_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C683_GROM,
      O => Ucore_Uusb_syn6004
    );
  Ucore_Uusb_C3732 : X_LUT4
    generic map(
      INIT => X"FF0A"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5913,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR3 => Ucore_Uusb_syn26775,
      O => Ucore_Uusb_syn5917_FROM
    );
  Ucore_Uusb_C3686 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5191,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR3 => Ucore_Uusb_syn5917,
      O => Ucore_Uusb_syn5917_GROM
    );
  Ucore_Uusb_syn5917_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5917_FROM,
      O => Ucore_Uusb_syn5917
    );
  Ucore_Uusb_syn5917_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5917_GROM,
      O => Ucore_Uusb_syn6012
    );
  Ucore_Uusb_C3628 : X_LUT4
    generic map(
      INIT => X"3320"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(7),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C617,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C611,
      O => Ucore_Uusb_syn5341_GROM
    );
  Ucore_Uusb_syn5341_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5341_GROM,
      O => Ucore_Uusb_syn5341
    );
  Ucore_Uusb_C3724 : X_LUT4
    generic map(
      INIT => X"EEEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26578,
      ADR1 => Ucore_Uusb_Uuc_BUS10875(7),
      ADR2 => Ucore_Uusb_syn5917,
      ADR3 => Ucore_Uusb_syn5190,
      O => Ucore_Uusb_syn26579_FROM
    );
  Ucore_Uusb_C3723 : X_LUT4
    generic map(
      INIT => X"F3F2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_syn26579,
      ADR3 => Ucore_Uusb_syn5903,
      O => Ucore_Uusb_syn26579_GROM
    );
  Ucore_Uusb_syn26579_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26579_FROM,
      O => Ucore_Uusb_syn26579
    );
  Ucore_Uusb_syn26579_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26579_GROM,
      O => Ucore_Uusb_syn26580
    );
  Ucore_Uusb_C3716 : X_LUT4
    generic map(
      INIT => X"000A"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5632,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5653,
      ADR3 => Ucore_Uusb_syn5659,
      O => Ucore_Uusb_Uuc_Udmux_C319_FROM
    );
  Ucore_Uusb_C3545 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DPTRO(8),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C325,
      ADR2 => Ucore_Uusb_Uuc_Uctrl_BUS15211(0),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C319,
      O => Ucore_Uusb_Uuc_Udmux_C319_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C319_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C319_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C319
    );
  Ucore_Uusb_Uuc_Udmux_C319_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C319_GROM,
      O => Ucore_Uusb_syn27010
    );
  Ucore_Uusb_C3708 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5659,
      ADR1 => Ucore_Uusb_syn5632,
      ADR2 => Ucore_Uusb_syn5664,
      ADR3 => Ucore_Uusb_syn5653,
      O => Ucore_Uusb_Uuc_Udmux_C327_FROM
    );
  Ucore_Uusb_C3582 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUFO8(9),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C331,
      ADR2 => Ucore_Uusb_Uuc_DPTRO(1),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C327,
      O => Ucore_Uusb_Uuc_Udmux_C327_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C327_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C327_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C327
    );
  Ucore_Uusb_Uuc_Udmux_C327_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C327_GROM,
      O => Ucore_Uusb_syn26907
    );
  Ucore_Uusb_C3680 : X_LUT4
    generic map(
      INIT => X"E020"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(6),
      ADR1 => Ucore_Uusb_syn5952,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR3 => Ucore_Uusb_Uuc_Uport0_pad(6),
      O => Ucore_Uusb_syn26651_FROM
    );
  Ucore_Uusb_C3660 : X_LUT4
    generic map(
      INIT => X"D080"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5952,
      ADR1 => Ucore_Uusb_Uuc_Uport0_pad(5),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR3 => Ucore_Uusb_BUS131(5),
      O => Ucore_Uusb_syn26651_GROM
    );
  Ucore_Uusb_syn26651_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26651_FROM,
      O => Ucore_Uusb_syn26651
    );
  Ucore_Uusb_syn26651_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26651_GROM,
      O => Ucore_Uusb_syn26702
    );
  Ucore_Uusb_C3755 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_syn5324,
      O => Ucore_Uusb_Uuc_Ualu_C661_FROM
    );
  Ucore_Uusb_C3652 : X_LUT4
    generic map(
      INIT => X"5353"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR1 => Ucore_Uusb_syn20364,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Ualu_C661_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C661_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C661_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C661
    );
  Ucore_Uusb_Uuc_Ualu_C661_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C661_GROM,
      O => Ucore_Uusb_syn23149
    );
  Ucore_Uusb_C3644 : X_LUT4
    generic map(
      INIT => X"FAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26735,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR3 => Ucore_Uusb_syn6007,
      O => Ucore_Uusb_syn26736_FROM
    );
  Ucore_Uusb_C3643 : X_LUT4
    generic map(
      INIT => X"FCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn20364,
      ADR2 => Ucore_Uusb_syn26736,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C690,
      O => Ucore_Uusb_syn26736_GROM
    );
  Ucore_Uusb_syn26736_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26736_FROM,
      O => Ucore_Uusb_syn26736
    );
  Ucore_Uusb_syn26736_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26736_GROM,
      O => Ucore_Uusb_syn26737
    );
  Ucore_Uusb_C3658 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(5),
      ADR2 => Ucore_Uusb_Uuc_RO(5),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C341,
      O => Ucore_Uusb_syn26699_FROM
    );
  Ucore_Uusb_C3636 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_RO(4),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR3 => Ucore_Uusb_Uuc_BUFO8(4),
      O => Ucore_Uusb_syn26699_GROM
    );
  Ucore_Uusb_syn26699_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26699_FROM,
      O => Ucore_Uusb_syn26699
    );
  Ucore_Uusb_syn26699_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26699_GROM,
      O => Ucore_Uusb_syn26755
    );
  Ucore_Uusb_C3548 : X_LUT4
    generic map(
      INIT => X"FFF2"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6352,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_syn23522,
      ADR3 => Ucore_Uusb_syn26992,
      O => Ucore_Uusb_syn26994_FROM
    );
  Ucore_Uusb_C3547 : X_LUT4
    generic map(
      INIT => X"FFF4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_syn6341,
      ADR2 => Ucore_Uusb_syn26990,
      ADR3 => Ucore_Uusb_syn26994,
      O => Ucore_Uusb_syn26994_GROM
    );
  Ucore_Uusb_syn26994_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26994_FROM,
      O => Ucore_Uusb_syn26994
    );
  Ucore_Uusb_syn26994_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26994_GROM,
      O => Ucore_Uusb_syn20073
    );
  Ucore_Uusb_C3492 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_FROM
    );
  Ucore_Uusb_C3488 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C485_GROM,
      O => Ucore_Uusb_syn6431
    );
  Ucore_Uusb_C3846 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS141(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_BUS59_0_FROM
    );
  Ucore_Uusb_C2932 : X_LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_n(1),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_n(0),
      O => Ucore_Uusb_Uusb_BUS59_0_GROM
    );
  Ucore_Uusb_Uusb_BUS59_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_0_FROM,
      O => Ucore_Uusb_Uusb_BUS59(0)
    );
  Ucore_Uusb_Uusb_BUS59_0_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_0_GROM,
      O => Ucore_Uusb_syn28298
    );
  Ucore_Uusb_C2908 : X_LUT4
    generic map(
      INIT => X"50FA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcen,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc(15),
      O => Ucore_Uusb_syn24588_FROM
    );
  Ucore_Uusb_C2836 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn24588,
      O => Ucore_Uusb_syn24588_GROM
    );
  Ucore_Uusb_syn24588_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn24588_FROM,
      O => Ucore_Uusb_syn24588
    );
  Ucore_Uusb_syn24588_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn24588_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C1_C0
    );
  Ucore_Uusb_C2860 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_din(11),
      ADR1 => Ucore_Uusb_syn5304,
      ADR2 => Ucore_din(3),
      ADR3 => Ucore_Uusb_syn5303,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FROM
    );
  Ucore_Uusb_C2859 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28436,
      ADR1 => Ucore_Uusb_Uusb_BUS8585(3),
      ADR2 => Ucore_Uusb_syn5164,
      ADR3 => Ucore_Uusb_syn28438,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N24
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FROM,
      O => Ucore_Uusb_syn28438
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2864 : X_LUT4
    generic map(
      INIT => X"B380"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(3),
      O => Ucore_Uusb_syn28427_FROM
    );
  Ucore_Uusb_C2852 : X_LUT4
    generic map(
      INIT => X"22F0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(7),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_syn28427_GROM
    );
  Ucore_Uusb_syn28427_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28427_FROM,
      O => Ucore_Uusb_syn28427
    );
  Ucore_Uusb_syn28427_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28427_GROM,
      O => Ucore_Uusb_syn28463
    );
  Ucore_Uusb_C2881 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      O => Ucore_Uusb_N1553
    );
  Ucore_Uusb_C2844 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn8288,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C12_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2828 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C304
    );
  Ucore_Uusb_C2780 : X_LUT4
    generic map(
      INIT => X"880C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(3),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FROM
    );
  Ucore_Uusb_C2779 : X_LUT4
    generic map(
      INIT => X"FF14"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_N1552,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR3 => Ucore_Uusb_syn28641,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N22
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FROM,
      O => Ucore_Uusb_syn28641
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2766 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uglue_cell17,
      ADR1 => VCC,
      ADR2 => Ucore_din(7),
      ADR3 => Ucore_din(15),
      O => Ucore_Uusb_Uglue_C36_N48_FROM
    );
  Ucore_Uusb_C2764 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uglue_cell17,
      ADR1 => Ucore_din(2),
      ADR2 => VCC,
      ADR3 => Ucore_din(10),
      O => Ucore_Uusb_Uglue_C36_N48_GROM
    );
  Ucore_Uusb_Uglue_C36_N48_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N48_FROM,
      O => Ucore_Uusb_Uglue_C36_N48
    );
  Ucore_Uusb_Uglue_C36_N48_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N48_GROM,
      O => Ucore_Uusb_Uglue_C36_N18
    );
  Ucore_Uusb_C3821 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Utmp2_TMP2(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_AO(1),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_sel,
      O => Ucore_Uusb_Uuc_BUS10875_1_FROM
    );
  Ucore_Uusb_C3553 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR1 => Ucore_Uusb_Uuc_BUS10875(2),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(1),
      O => Ucore_Uusb_Uuc_BUS10875_1_GROM
    );
  Ucore_Uusb_Uuc_BUS10875_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_1_FROM,
      O => Ucore_Uusb_Uuc_BUS10875(1)
    );
  Ucore_Uusb_Uuc_BUS10875_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_1_GROM,
      O => Ucore_Uusb_syn26934
    );
  Ucore_Uusb_C3813 : X_LUT4
    generic map(
      INIT => X"70FF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5624,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR2 => Ucore_Uusb_syn5608,
      ADR3 => Ucore_Uusb_Uuc_DSEL(1),
      O => Ucore_Uusb_syn26285_FROM
    );
  Ucore_Uusb_C3812 : X_LUT4
    generic map(
      INIT => X"BF00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5320,
      ADR1 => Ucore_Uusb_syn5608,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR3 => Ucore_Uusb_syn26285,
      O => Ucore_Uusb_syn26285_GROM
    );
  Ucore_Uusb_syn26285_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26285_FROM,
      O => Ucore_Uusb_syn26285
    );
  Ucore_Uusb_syn26285_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26285_GROM,
      O => Ucore_Uusb_syn5632
    );
  Ucore_Uusb_C3637 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C327,
      ADR1 => Ucore_Uusb_Uuc_DPTRO(4),
      ADR2 => Ucore_Uusb_Uuc_BUFO8(12),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C331,
      O => Ucore_Uusb_syn26754_GROM
    );
  Ucore_Uusb_syn26754_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26754_GROM,
      O => Ucore_Uusb_syn26754
    );
  Ucore_Uusb_C3573 : X_LUT4
    generic map(
      INIT => X"FAEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6158,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_syn5913,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(0),
      O => Ucore_Uusb_syn6360_FROM
    );
  Ucore_Uusb_C3572 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C424_C0_C3,
      ADR1 => Ucore_Uusb_Uuc_BUS10875(0),
      ADR2 => Ucore_Uusb_syn6004,
      ADR3 => Ucore_Uusb_syn6360,
      O => Ucore_Uusb_syn6360_GROM
    );
  Ucore_Uusb_syn6360_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6360_FROM,
      O => Ucore_Uusb_syn6360
    );
  Ucore_Uusb_syn6360_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6360_GROM,
      O => Ucore_Uusb_syn26990
    );
  Ucore_Uusb_C3565 : X_LUT4
    generic map(
      INIT => X"5404"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_BUS10875(4),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(5),
      O => Ucore_Uusb_syn26969_FROM
    );
  Ucore_Uusb_C3564 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn26969,
      ADR3 => Ucore_Uusb_syn26968,
      O => Ucore_Uusb_syn26969_GROM
    );
  Ucore_Uusb_syn26969_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26969_FROM,
      O => Ucore_Uusb_syn26969
    );
  Ucore_Uusb_syn26969_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26969_GROM,
      O => Ucore_Uusb_syn6329
    );
  Ucore_Uusb_C3499 : X_LUT4
    generic map(
      INIT => X"F77F"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5624,
      ADR1 => Ucore_Uusb_syn6505,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(1),
      O => Ucore_Uusb_syn6513_FROM
    );
  Ucore_Uusb_C3493 : X_LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5624,
      ADR1 => Ucore_Uusb_syn6505,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(1),
      O => Ucore_Uusb_syn6513_GROM
    );
  Ucore_Uusb_syn6513_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6513_FROM,
      O => Ucore_Uusb_syn6513
    );
  Ucore_Uusb_syn6513_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6513_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C921
    );
  Ucore_Uusb_C3397 : X_LUT4
    generic map(
      INIT => X"0222"
    )
    port map (
      ADR0 => Ucore_Uusb_NET136,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_syn6653,
      O => Ucore_Uusb_Uusb_Uep0ctrl_N484_GROM
    );
  Ucore_Uusb_Uusb_Uep0ctrl_N484_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_N484_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_N484
    );
  Ucore_Uusb_C2872 : X_LUT4
    generic map(
      INIT => X"B830"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      O => Ucore_Uusb_syn28409_FROM
    );
  Ucore_Uusb_C2925 : X_LUT4
    generic map(
      INIT => X"3232"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR3 => VCC,
      O => Ucore_Uusb_syn28409_GROM
    );
  Ucore_Uusb_syn28409_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28409_FROM,
      O => Ucore_Uusb_syn28409
    );
  Ucore_Uusb_syn28409_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28409_GROM,
      O => Ucore_Uusb_syn28314
    );
  Ucore_Uusb_C2858 : X_LUT4
    generic map(
      INIT => X"2E22"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(5),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      O => Ucore_Uusb_syn28445_FROM
    );
  Ucore_Uusb_C2861 : X_LUT4
    generic map(
      INIT => X"E222"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(4),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(3),
      O => Ucore_Uusb_syn28445_GROM
    );
  Ucore_Uusb_syn28445_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28445_FROM,
      O => Ucore_Uusb_syn28445
    );
  Ucore_Uusb_syn28445_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28445_GROM,
      O => Ucore_Uusb_syn28436
    );
  Ucore_Uusb_C2765 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uglue_cell17,
      ADR2 => Ucore_din(11),
      ADR3 => Ucore_din(3),
      O => Ucore_Uusb_Uglue_C36_N24_GROM
    );
  Ucore_Uusb_Uglue_C36_N24_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uglue_C36_N24_GROM,
      O => Ucore_Uusb_Uglue_C36_N24
    );
  Ucore_Uusb_C3822 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_AO(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(2),
      O => Ucore_Uusb_Uuc_BUS10875_2_FROM
    );
  Ucore_Uusb_C3563 : X_LUT4
    generic map(
      INIT => X"A280"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => Ucore_Uusb_Uuc_BUS10875(3),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(2),
      O => Ucore_Uusb_Uuc_BUS10875_2_GROM
    );
  Ucore_Uusb_Uuc_BUS10875_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_2_FROM,
      O => Ucore_Uusb_Uuc_BUS10875(2)
    );
  Ucore_Uusb_Uuc_BUS10875_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_2_GROM,
      O => Ucore_Uusb_syn26960
    );
  Ucore_Uusb_C3814 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(6),
      ADR2 => Ucore_Uusb_syn5618,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(5),
      O => Ucore_Uusb_syn5624_FROM
    );
  Ucore_Uusb_C3811 : X_LUT4
    generic map(
      INIT => X"55FF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5608,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5624,
      O => Ucore_Uusb_syn5624_GROM
    );
  Ucore_Uusb_syn5624_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5624_FROM,
      O => Ucore_Uusb_syn5624
    );
  Ucore_Uusb_syn5624_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5624_GROM,
      O => Ucore_Uusb_Uuc_Udmux_C461
    );
  Ucore_Uusb_C3806 : X_LUT4
    generic map(
      INIT => X"FAFF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn5161,
      ADR3 => Ucore_Uusb_Uuc_BUS12659(4),
      O => Ucore_Uusb_syn5338_FROM
    );
  Ucore_Uusb_C3805 : X_LUT4
    generic map(
      INIT => X"BF0F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR1 => Ucore_Uusb_syn5624,
      ADR2 => Ucore_Uusb_syn5608,
      ADR3 => Ucore_Uusb_syn5338,
      O => Ucore_Uusb_syn5338_GROM
    );
  Ucore_Uusb_syn5338_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5338_FROM,
      O => Ucore_Uusb_syn5338
    );
  Ucore_Uusb_syn5338_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5338_GROM,
      O => Ucore_Uusb_syn26306
    );
  Ucore_Uusb_C3761 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5293,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_Uuc_Ualu_C690_FROM
    );
  Ucore_Uusb_C3750 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5293,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(4),
      O => Ucore_Uusb_Uuc_Ualu_C690_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C690_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C690_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C690
    );
  Ucore_Uusb_Uuc_Ualu_C690_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C690_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C589
    );
  Ucore_Uusb_C3670 : X_LUT4
    generic map(
      INIT => X"A0AA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5913,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10881(0),
      O => Ucore_Uusb_syn6257_FROM
    );
  Ucore_Uusb_C3591 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR1 => Ucore_Uusb_syn6158,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_syn6257,
      O => Ucore_Uusb_syn6257_GROM
    );
  Ucore_Uusb_syn6257_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6257_FROM,
      O => Ucore_Uusb_syn6257
    );
  Ucore_Uusb_syn6257_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6257_GROM,
      O => Ucore_Uusb_syn6260
    );
  Ucore_Uusb_C3654 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26702,
      ADR1 => Ucore_Uusb_syn26707,
      ADR2 => Ucore_Uusb_syn26696,
      ADR3 => Ucore_Uusb_syn26697,
      O => Ucore_Uusb_Uuc_SPO_5_FROM
    );
  Ucore_Uusb_C3653 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6075,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR3 => Ucore_Uusb_syn26708,
      O => Ucore_Uusb_Uuc_SPO_5_GROM
    );
  Ucore_Uusb_Uuc_SPO_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_5_FROM,
      O => Ucore_Uusb_syn26708
    );
  Ucore_Uusb_Uuc_SPO_5_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_5_GROM,
      O => Ucore_Uusb_Uuc_DBUS(5)
    );
  Ucore_Uusb_Uuc_SPO_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3646 : X_LUT4
    generic map(
      INIT => X"CDCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR1 => Ucore_Uusb_syn26733,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_syn5340,
      O => Ucore_Uusb_syn26734_FROM
    );
  Ucore_Uusb_C3645 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10875(4),
      ADR1 => Ucore_Uusb_syn5917,
      ADR2 => Ucore_Uusb_syn26719,
      ADR3 => Ucore_Uusb_syn26734,
      O => Ucore_Uusb_syn26734_GROM
    );
  Ucore_Uusb_syn26734_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26734_FROM,
      O => Ucore_Uusb_syn26734
    );
  Ucore_Uusb_syn26734_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26734_GROM,
      O => Ucore_Uusb_syn26735
    );
  Ucore_Uusb_C3494 : X_LUT4
    generic map(
      INIT => X"EB00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C929,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR3 => Ucore_Uusb_syn27134,
      O => Ucore_Uusb_syn6524_FROM
    );
  Ucore_Uusb_C3489 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn6527,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn6524,
      O => Ucore_Uusb_syn6524_GROM
    );
  Ucore_Uusb_syn6524_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6524_FROM,
      O => Ucore_Uusb_syn6524
    );
  Ucore_Uusb_syn6524_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6524_GROM,
      O => Ucore_Uusb_syn5317
    );
  Ucore_Uusb_C2854 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_din(13),
      ADR1 => Ucore_Uusb_syn5303,
      ADR2 => Ucore_din(5),
      ADR3 => Ucore_Uusb_syn5304,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FROM
    );
  Ucore_Uusb_C2853 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5164,
      ADR1 => Ucore_Uusb_Uusb_BUS8585(5),
      ADR2 => Ucore_Uusb_syn28454,
      ADR3 => Ucore_Uusb_syn28456,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N36
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FROM,
      O => Ucore_Uusb_syn28456
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2846 : X_LUT4
    generic map(
      INIT => X"A050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxd2,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FROM
    );
  Ucore_Uusb_C2841 : X_LUT4
    generic map(
      INIT => X"5A40"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      ADR3 => Ucore_Uusb_syn8288,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N34
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FROM,
      O => Ucore_Uusb_syn8288
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_high_temp2_fast_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_high_temp2_fast_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3831 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_FROM
    );
  Ucore_Uusb_C3830 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(3),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89_GROM,
      O => Ucore_Uusb_syn26236
    );
  Ucore_Uusb_C3823 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_AO(3),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_TMP2(3),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_sel,
      O => Ucore_Uusb_Uuc_BUS10875_3_FROM
    );
  Ucore_Uusb_C3556 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10875(4),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(3),
      O => Ucore_Uusb_Uuc_BUS10875_3_GROM
    );
  Ucore_Uusb_Uuc_BUS10875_3_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_3_FROM,
      O => Ucore_Uusb_Uuc_BUS10875(3)
    );
  Ucore_Uusb_Uuc_BUS10875_3_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_3_GROM,
      O => Ucore_Uusb_syn26933
    );
  Ucore_Uusb_C3487 : X_LUT4
    generic map(
      INIT => X"FFBB"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR1 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5161,
      O => Ucore_Uusb_syn27118_FROM
    );
  Ucore_Uusb_C3486 : X_LUT4
    generic map(
      INIT => X"C8C0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6505,
      ADR1 => Ucore_Uusb_syn6431,
      ADR2 => Ucore_Uusb_syn6437,
      ADR3 => Ucore_Uusb_syn27118,
      O => Ucore_Uusb_syn27118_GROM
    );
  Ucore_Uusb_syn27118_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27118_FROM,
      O => Ucore_Uusb_syn27118
    );
  Ucore_Uusb_syn27118_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27118_GROM,
      O => Ucore_Uusb_syn27122
    );
  Ucore_Uusb_C3735 : X_LUT4
    generic map(
      INIT => X"CA00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5323,
      ADR1 => Ucore_Uusb_syn5298,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(3),
      O => Ucore_Uusb_syn5913_FROM
    );
  Ucore_Uusb_C3650 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR1 => Ucore_Uusb_syn6106,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR3 => Ucore_Uusb_syn5913,
      O => Ucore_Uusb_syn5913_GROM
    );
  Ucore_Uusb_syn5913_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5913_FROM,
      O => Ucore_Uusb_syn5913
    );
  Ucore_Uusb_syn5913_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5913_GROM,
      O => Ucore_Uusb_syn26719
    );
  Ucore_Uusb_C3727 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C611,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C617,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_PO(7),
      O => Ucore_Uusb_syn5910_FROM
    );
  Ucore_Uusb_C3590 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR3 => Ucore_Uusb_syn5910,
      O => Ucore_Uusb_syn5910_GROM
    );
  Ucore_Uusb_syn5910_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5910_FROM,
      O => Ucore_Uusb_syn5910
    );
  Ucore_Uusb_syn5910_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5910_GROM,
      O => Ucore_Uusb_syn6265
    );
  Ucore_Uusb_C3719 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5664,
      ADR1 => Ucore_Uusb_syn5653,
      ADR2 => Ucore_Uusb_syn5659,
      ADR3 => Ucore_Uusb_syn5632,
      O => Ucore_Uusb_Uuc_Udmux_C313_FROM
    );
  Ucore_Uusb_C3546 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR1 => Ucore_Uusb_Uuc_OP3(0),
      ADR2 => Ucore_Uusb_Uuc_OP2(0),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C313,
      O => Ucore_Uusb_Uuc_Udmux_C313_GROM
    );
  Ucore_Uusb_Uuc_Udmux_C313_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C313_FROM,
      O => Ucore_Uusb_Uuc_Udmux_C313
    );
  Ucore_Uusb_Uuc_Udmux_C313_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Udmux_C313_GROM,
      O => Ucore_Uusb_syn27009
    );
  Ucore_Uusb_C3671 : X_LUT4
    generic map(
      INIT => X"6090"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR1 => Ucore_Uusb_syn5725,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C458_C8,
      O => Ucore_Uusb_syn6073_GROM
    );
  Ucore_Uusb_syn6073_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6073_GROM,
      O => Ucore_Uusb_syn6073
    );
  Ucore_Uusb_C3639 : X_LUT4
    generic map(
      INIT => X"C808"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(4),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C339,
      ADR2 => Ucore_Uusb_syn5952,
      ADR3 => Ucore_Uusb_Uuc_Uport0_pad(4),
      O => Ucore_Uusb_syn26758_FROM
    );
  Ucore_Uusb_C3638 : X_LUT4
    generic map(
      INIT => X"FFFA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26752,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn26753,
      ADR3 => Ucore_Uusb_syn26758,
      O => Ucore_Uusb_syn26758_GROM
    );
  Ucore_Uusb_syn26758_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26758_FROM,
      O => Ucore_Uusb_syn26758
    );
  Ucore_Uusb_syn26758_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26758_GROM,
      O => Ucore_Uusb_syn26762
    );
  Ucore_Uusb_C3575 : X_LUT4
    generic map(
      INIT => X"AEAE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR2 => Ucore_Uusb_syn20065,
      ADR3 => VCC,
      O => Ucore_Uusb_syn26953_FROM
    );
  Ucore_Uusb_C3574 : X_LUT4
    generic map(
      INIT => X"FF10"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => Ucore_Uusb_syn5910,
      ADR3 => Ucore_Uusb_syn26953,
      O => Ucore_Uusb_syn26953_GROM
    );
  Ucore_Uusb_syn26953_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26953_FROM,
      O => Ucore_Uusb_syn26953
    );
  Ucore_Uusb_syn26953_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26953_GROM,
      O => Ucore_Uusb_syn6341
    );
  Ucore_Uusb_C3559 : X_LUT4
    generic map(
      INIT => X"FCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR2 => Ucore_Uusb_syn6110,
      ADR3 => Ucore_Uusb_Uuc_BUS10875(0),
      O => Ucore_Uusb_syn26947_FROM
    );
  Ucore_Uusb_C3558 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn20065,
      ADR3 => Ucore_Uusb_syn26947,
      O => Ucore_Uusb_syn26947_GROM
    );
  Ucore_Uusb_syn26947_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26947_FROM,
      O => Ucore_Uusb_syn26947
    );
  Ucore_Uusb_syn26947_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26947_GROM,
      O => Ucore_Uusb_syn26948
    );
  Ucore_Uusb_C2986 : X_LUT4
    generic map(
      INIT => X"0404"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_FROM
    );
  Ucore_Uusb_C2943 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C286
    );
  Ucore_Uusb_C2927 : X_LUT4
    generic map(
      INIT => X"0A08"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR1 => Ucore_Uusb_syn8006,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR3 => Ucore_Uusb_syn28306,
      O => Ucore_Uusb_syn8011_FROM
    );
  Ucore_Uusb_C2924 : X_LUT4
    generic map(
      INIT => X"FCEE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28312,
      ADR1 => Ucore_Uusb_syn28314,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C171,
      ADR3 => Ucore_Uusb_syn8011,
      O => Ucore_Uusb_syn8011_GROM
    );
  Ucore_Uusb_syn8011_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8011_FROM,
      O => Ucore_Uusb_syn8011
    );
  Ucore_Uusb_syn8011_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8011_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C13_N18
    );
  Ucore_Uusb_C2991 : X_LUT4
    generic map(
      INIT => X"AAA5"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      O => Ucore_Uusb_N1514_FROM
    );
  Ucore_Uusb_C2919 : X_LUT4
    generic map(
      INIT => X"0050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      O => Ucore_Uusb_N1514_GROM
    );
  Ucore_Uusb_N1514_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_N1514_FROM,
      O => Ucore_Uusb_N1514
    );
  Ucore_Uusb_N1514_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_N1514_GROM,
      O => Ucore_Uusb_syn8037
    );
  Ucore_Uusb_C2863 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5304,
      ADR1 => Ucore_din(10),
      ADR2 => Ucore_Uusb_syn5303,
      ADR3 => Ucore_din(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FROM
    );
  Ucore_Uusb_C2862 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5164,
      ADR1 => Ucore_Uusb_syn28427,
      ADR2 => Ucore_Uusb_Uusb_BUS8585(2),
      ADR3 => Ucore_Uusb_syn28429,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N18
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FROM,
      O => Ucore_Uusb_syn28429
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2888 : X_LUT4
    generic map(
      INIT => X"FF55"
    )
    port map (
      ADR0 => Ucore_Uusb_N1552,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_FROM
    );
  Ucore_Uusb_C2855 : X_LUT4
    generic map(
      INIT => X"50CC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(6),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6_GROM,
      O => Ucore_Uusb_syn28454
    );
  Ucore_Uusb_C2839 : X_LUT4
    generic map(
      INIT => X"0FA5"
    )
    port map (
      ADR0 => Ucore_Uusb_syn24588,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2,
      O => vpo_p13_c_FROM
    );
  Ucore_Uusb_C2783 : X_LUT4
    generic map(
      INIT => X"FDB9"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR2 => Ucore_Uusb_syn8481,
      ADR3 => Ucore_Uusb_syn26135,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C10_N9
    );
  vpo_p13_c_XUSED : X_BUF
    port map (
      I => vpo_p13_c_FROM,
      O => Ucore_Uusb_syn26135
    );
  vpo_p13_c_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => vpo_p13_c_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2791 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3,
      O => Ucore_Uusb_syn28612_FROM
    );
  Ucore_Uusb_C2790 : X_LUT4
    generic map(
      INIT => X"F0A0"
    )
    port map (
      ADR0 => Ucore_Uusb_N1554,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(1),
      ADR3 => Ucore_Uusb_syn28612,
      O => Ucore_Uusb_syn28612_GROM
    );
  Ucore_Uusb_syn28612_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28612_FROM,
      O => Ucore_Uusb_syn28612
    );
  Ucore_Uusb_syn28612_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28612_GROM,
      O => Ucore_Uusb_syn8470
    );
  Ucore_Uusb_C2775 : X_LUT4
    generic map(
      INIT => X"1110"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(3),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      ADR3 => Ucore_Uusb_N1552,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FROM
    );
  Ucore_Uusb_C2774 : X_LUT4
    generic map(
      INIT => X"0F0E"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0),
      ADR3 => Ucore_Uusb_syn8513,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N54
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FROM,
      O => Ucore_Uusb_syn8513
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3847 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS141(1),
      ADR1 => Ucore_Uusb_syn5458,
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_BUS59_1_FROM
    );
  Ucore_Uusb_C3840 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_rxd(2),
      ADR1 => Ucore_Uusb_BUS131(2),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_BUS59_1_GROM
    );
  Ucore_Uusb_Uusb_BUS59_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_1_FROM,
      O => Ucore_Uusb_Uusb_BUS59(1)
    );
  Ucore_Uusb_Uusb_BUS59_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS59_1_GROM,
      O => Ucore_Uusb_Uusb_BUS67(2)
    );
  Ucore_Uusb_C3832 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0),
      O => Ucore_Uusb_syn5539_FROM
    );
  Ucore_Uusb_C3030 : X_LUT4
    generic map(
      INIT => X"88F8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C454,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C491,
      ADR3 => Ucore_Uusb_syn5539,
      O => Ucore_Uusb_syn5539_GROM
    );
  Ucore_Uusb_syn5539_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5539_FROM,
      O => Ucore_Uusb_syn5539
    );
  Ucore_Uusb_syn5539_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5539_GROM,
      O => Ucore_Uusb_syn28104
    );
  Ucore_Uusb_C3816 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_DSEL(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_DSEL(2),
      ADR3 => Ucore_Uusb_Uuc_DSEL(1),
      O => Ucore_Uusb_syn26270_FROM
    );
  Ucore_Uusb_C3815 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_DSEL(0),
      ADR2 => Ucore_Uusb_Uuc_RAM_REG(7),
      ADR3 => Ucore_Uusb_syn26270,
      O => Ucore_Uusb_syn26270_GROM
    );
  Ucore_Uusb_syn26270_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26270_FROM,
      O => Ucore_Uusb_syn26270
    );
  Ucore_Uusb_syn26270_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26270_GROM,
      O => Ucore_Uusb_syn5608
    );
  Ucore_Uusb_C3808 : X_LUT4
    generic map(
      INIT => X"FBBB"
    )
    port map (
      ADR0 => Ucore_Uusb_syn22957,
      ADR1 => Ucore_Uusb_syn5608,
      ADR2 => Ucore_Uusb_syn5645,
      ADR3 => Ucore_Uusb_syn5624,
      O => Ucore_Uusb_syn5652_FROM
    );
  Ucore_Uusb_C3807 : X_LUT4
    generic map(
      INIT => X"2300"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C461,
      ADR1 => Ucore_Uusb_Uuc_DSEL(3),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(1),
      ADR3 => Ucore_Uusb_syn5652,
      O => Ucore_Uusb_syn5652_GROM
    );
  Ucore_Uusb_syn5652_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5652_FROM,
      O => Ucore_Uusb_syn5652
    );
  Ucore_Uusb_syn5652_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5652_GROM,
      O => Ucore_Uusb_syn5653
    );
  Ucore_Uusb_C3760 : X_LUT4
    generic map(
      INIT => X"0A0A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5292_FROM
    );
  Ucore_Uusb_C3758 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn5292,
      O => Ucore_Uusb_syn5292_GROM
    );
  Ucore_Uusb_syn5292_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5292_FROM,
      O => Ucore_Uusb_syn5292
    );
  Ucore_Uusb_syn5292_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5292_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C585
    );
  Ucore_Uusb_C3736 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5323_FROM
    );
  Ucore_Uusb_C3555 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_syn5323,
      O => Ucore_Uusb_syn5323_GROM
    );
  Ucore_Uusb_syn5323_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5323_FROM,
      O => Ucore_Uusb_syn5323
    );
  Ucore_Uusb_syn5323_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5323_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C603
    );
  Ucore_Uusb_C3728 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn5324,
      O => Ucore_Uusb_Uuc_Ualu_C611_FROM
    );
  Ucore_Uusb_C3726 : X_LUT4
    generic map(
      INIT => X"CC80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C617,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR2 => Ucore_Uusb_Uuc_PO(7),
      ADR3 => Ucore_Uusb_Uuc_Ualu_C611,
      O => Ucore_Uusb_Uuc_Ualu_C611_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C611_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C611_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C611
    );
  Ucore_Uusb_Uuc_Ualu_C611_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C611_GROM,
      O => Ucore_Uusb_syn5340
    );
  Ucore_Uusb_C3689 : X_LUT4
    generic map(
      INIT => X"FCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn20067,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C585,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(7),
      O => Ucore_Uusb_syn6007_FROM
    );
  Ucore_Uusb_C3672 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR1 => Ucore_Uusb_Uuc_BUS10875(5),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C585,
      ADR3 => Ucore_Uusb_syn20067,
      O => Ucore_Uusb_syn6007_GROM
    );
  Ucore_Uusb_syn6007_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6007_FROM,
      O => Ucore_Uusb_syn6007
    );
  Ucore_Uusb_syn6007_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6007_GROM,
      O => Ucore_Uusb_syn6059
    );
  Ucore_Uusb_C3664 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26679,
      ADR1 => Ucore_Uusb_syn6059,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR3 => Ucore_Uusb_syn6073,
      O => Ucore_Uusb_syn26681_FROM
    );
  Ucore_Uusb_C3663 : X_LUT4
    generic map(
      INIT => X"FF84"
    )
    port map (
      ADR0 => Ucore_Uusb_syn23094,
      ADR1 => Ucore_Uusb_syn6004,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C433_C0_C3,
      ADR3 => Ucore_Uusb_syn26681,
      O => Ucore_Uusb_syn26681_GROM
    );
  Ucore_Uusb_syn26681_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26681_FROM,
      O => Ucore_Uusb_syn26681
    );
  Ucore_Uusb_syn26681_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26681_GROM,
      O => Ucore_Uusb_syn6075
    );
  Ucore_Uusb_C3656 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_AO(5),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR2 => Ucore_Uusb_Uuc_BO(5),
      ADR3 => Ucore_Uusb_Uuc_Udmux_C357,
      O => Ucore_Uusb_syn26701_FROM
    );
  Ucore_Uusb_C3655 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26699,
      ADR1 => Ucore_Uusb_syn26698,
      ADR2 => Ucore_Uusb_syn26700,
      ADR3 => Ucore_Uusb_syn26701,
      O => Ucore_Uusb_syn26701_GROM
    );
  Ucore_Uusb_syn26701_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26701_FROM,
      O => Ucore_Uusb_syn26701
    );
  Ucore_Uusb_syn26701_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26701_GROM,
      O => Ucore_Uusb_syn26707
    );
  Ucore_Uusb_C3648 : X_LUT4
    generic map(
      INIT => X"D5C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C675,
      O => Ucore_Uusb_syn26732_FROM
    );
  Ucore_Uusb_C3647 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn6110,
      ADR2 => Ucore_Uusb_Uuc_PO(4),
      ADR3 => Ucore_Uusb_syn26732,
      O => Ucore_Uusb_syn26732_GROM
    );
  Ucore_Uusb_syn26732_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26732_FROM,
      O => Ucore_Uusb_syn26732
    );
  Ucore_Uusb_syn26732_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26732_GROM,
      O => Ucore_Uusb_syn26733
    );
  Ucore_Uusb_C3568 : X_LUT4
    generic map(
      INIT => X"C3C3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn20065,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR3 => VCC,
      O => Ucore_Uusb_syn26078_FROM
    );
  Ucore_Uusb_C3567 : X_LUT4
    generic map(
      INIT => X"DCCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(7),
      ADR1 => Ucore_Uusb_syn6350,
      ADR2 => Ucore_Uusb_syn6004,
      ADR3 => Ucore_Uusb_syn26078,
      O => Ucore_Uusb_syn26078_GROM
    );
  Ucore_Uusb_syn26078_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26078_FROM,
      O => Ucore_Uusb_syn26078
    );
  Ucore_Uusb_syn26078_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26078_GROM,
      O => Ucore_Uusb_syn6352
    );
  Ucore_Uusb_C3496 : X_LUT4
    generic map(
      INIT => X"F050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_syn6451,
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C165,
      O => Ucore_Uusb_syn27132_FROM
    );
  Ucore_Uusb_C3495 : X_LUT4
    generic map(
      INIT => X"D500"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6505,
      ADR1 => Ucore_Uusb_syn27130,
      ADR2 => Ucore_Uusb_syn5338,
      ADR3 => Ucore_Uusb_syn27132,
      O => Ucore_Uusb_syn27132_GROM
    );
  Ucore_Uusb_syn27132_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27132_FROM,
      O => Ucore_Uusb_syn27132
    );
  Ucore_Uusb_syn27132_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn27132_GROM,
      O => Ucore_Uusb_syn27134
    );
  Ucore_Uusb_C2994 : X_LUT4
    generic map(
      INIT => X"AE00"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7842,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_cell13,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1),
      O => Ucore_Uusb_syn28193_FROM
    );
  Ucore_Uusb_C2928 : X_LUT4
    generic map(
      INIT => X"7777"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Ucore_Uusb_syn28193_GROM
    );
  Ucore_Uusb_syn28193_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28193_FROM,
      O => Ucore_Uusb_syn28193
    );
  Ucore_Uusb_syn28193_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28193_GROM,
      O => Ucore_Uusb_syn28306
    );
  Ucore_Uusb_C2848 : X_LUT4
    generic map(
      INIT => X"FCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_syn8277,
      ADR2 => Ucore_Uusb_Uusb_BUS8585(7),
      ADR3 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C2,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FROM
    );
  Ucore_Uusb_C2847 : X_LUT4
    generic map(
      INIT => X"3F0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(3),
      ADR3 => Ucore_Uusb_syn8279,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS1411(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FROM,
      O => Ucore_Uusb_syn8279
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3845 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5458,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_BUS131(7),
      ADR3 => Ucore_Uusb_Uusb_rxd(7),
      O => Ucore_Uusb_Uusb_BUS67_7_FROM
    );
  Ucore_Uusb_C3841 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5458,
      ADR1 => Ucore_Uusb_BUS131(3),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_rxd(3),
      O => Ucore_Uusb_Uusb_BUS67_7_GROM
    );
  Ucore_Uusb_Uusb_BUS67_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS67_7_FROM,
      O => Ucore_Uusb_Uusb_BUS67(7)
    );
  Ucore_Uusb_Uusb_BUS67_7_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS67_7_GROM,
      O => Ucore_Uusb_Uusb_BUS67(3)
    );
  Ucore_Uusb_C3833 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(2),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_CSP(4),
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_FROM
    );
  Ucore_Uusb_C3512 : X_LUT4
    generic map(
      INIT => X"0777"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Udctrl_C541,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(0),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(0),
      ADR3 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_GROM
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_FROM,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167_GROM,
      O => Ucore_Uusb_syn27054
    );
  Ucore_Uusb_C3776 : X_LUT4
    generic map(
      INIT => X"00AC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Utmp2_TMP2(5),
      ADR1 => Ucore_Uusb_Uuc_AO(5),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_syn5667,
      O => Ucore_Uusb_Uuc_Ualu_C458_C8_FROM
    );
  Ucore_Uusb_C3825 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_AO(5),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(5),
      O => Ucore_Uusb_Uuc_Ualu_C458_C8_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C458_C8_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C458_C8_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C458_C8
    );
  Ucore_Uusb_Uuc_Ualu_C458_C8_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C458_C8_GROM,
      O => Ucore_Uusb_Uuc_BUS10875(5)
    );
  Ucore_Uusb_C3817 : X_LUT4
    generic map(
      INIT => X"AFAF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5161,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5320_FROM
    );
  Ucore_Uusb_C3803 : X_LUT4
    generic map(
      INIT => X"3233"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR1 => Ucore_Uusb_Uuc_DSEL(0),
      ADR2 => Ucore_Uusb_syn5320,
      ADR3 => Ucore_Uusb_syn5608,
      O => Ucore_Uusb_syn5320_GROM
    );
  Ucore_Uusb_syn5320_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5320_FROM,
      O => Ucore_Uusb_syn5320
    );
  Ucore_Uusb_syn5320_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5320_GROM,
      O => Ucore_Uusb_syn26290
    );
  Ucore_Uusb_C3753 : X_LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_syn5667,
      O => Ucore_Uusb_syn5868_FROM
    );
  Ucore_Uusb_C3752 : X_LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5294,
      ADR1 => Ucore_Uusb_syn5293,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn5868,
      O => Ucore_Uusb_syn5868_GROM
    );
  Ucore_Uusb_syn5868_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5868_FROM,
      O => Ucore_Uusb_syn5868
    );
  Ucore_Uusb_syn5868_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5868_GROM,
      O => Ucore_Uusb_syn5869
    );
  Ucore_Uusb_C3745 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C585,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C681,
      ADR2 => Ucore_Uusb_Uuc_BUS10875(7),
      ADR3 => Ucore_Uusb_syn20067,
      O => Ucore_Uusb_syn26575_FROM
    );
  Ucore_Uusb_C3742 : X_LUT4
    generic map(
      INIT => X"C8C0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C690,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_syn26575,
      ADR3 => Ucore_Uusb_syn26088,
      O => Ucore_Uusb_syn26575_GROM
    );
  Ucore_Uusb_syn26575_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26575_FROM,
      O => Ucore_Uusb_syn26575
    );
  Ucore_Uusb_syn26575_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26575_GROM,
      O => Ucore_Uusb_syn23229
    );
  Ucore_Uusb_C3737 : X_LUT4
    generic map(
      INIT => X"0300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_syn5298_FROM
    );
  Ucore_Uusb_C3731 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR3 => Ucore_Uusb_syn5298,
      O => Ucore_Uusb_syn5298_GROM
    );
  Ucore_Uusb_syn5298_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5298_FROM,
      O => Ucore_Uusb_syn5298
    );
  Ucore_Uusb_syn5298_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5298_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C665
    );
  Ucore_Uusb_C3759 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5292,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_Uuc_Ualu_C681_FROM
    );
  Ucore_Uusb_C3649 : X_LUT4
    generic map(
      INIT => X"2800"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5292,
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_Uuc_ALUOP(4),
      O => Ucore_Uusb_Uuc_Ualu_C681_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C681_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C681_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C681
    );
  Ucore_Uusb_Uuc_Ualu_C681_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C681_GROM,
      O => Ucore_Uusb_syn6110
    );
  Ucore_Uusb_C3593 : X_LUT4
    generic map(
      INIT => X"3355"
    )
    port map (
      ADR0 => Ucore_Uusb_syn20137,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(2),
      O => Ucore_Uusb_syn23120_GROM
    );
  Ucore_Uusb_syn23120_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn23120_GROM,
      O => Ucore_Uusb_syn23120
    );
  Ucore_Uusb_C3585 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C313,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C317,
      ADR2 => Ucore_Uusb_Uuc_OP3(1),
      ADR3 => Ucore_Uusb_Uuc_OP2(1),
      O => Ucore_Uusb_syn26905_GROM
    );
  Ucore_Uusb_syn26905_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26905_GROM,
      O => Ucore_Uusb_syn26905
    );
  Ucore_Uusb_C3577 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26905,
      ADR1 => Ucore_Uusb_syn26916,
      ADR2 => Ucore_Uusb_syn26911,
      ADR3 => Ucore_Uusb_syn26906,
      O => Ucore_Uusb_Uuc_SPO_1_FROM
    );
  Ucore_Uusb_C3576 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6264,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR2 => Ucore_Uusb_syn26890,
      ADR3 => Ucore_Uusb_syn26917,
      O => Ucore_Uusb_Uuc_SPO_1_GROM
    );
  Ucore_Uusb_Uuc_SPO_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_1_FROM,
      O => Ucore_Uusb_syn26917
    );
  Ucore_Uusb_Uuc_SPO_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_1_GROM,
      O => Ucore_Uusb_Uuc_DBUS(1)
    );
  Ucore_Uusb_Uuc_SPO_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2857 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_din(4),
      ADR1 => Ucore_Uusb_syn5303,
      ADR2 => Ucore_Uusb_syn5304,
      ADR3 => Ucore_din(12),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FROM
    );
  Ucore_Uusb_C2856 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28445,
      ADR1 => Ucore_Uusb_Uusb_BUS8585(4),
      ADR2 => Ucore_Uusb_syn5164,
      ADR3 => Ucore_Uusb_syn28447,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N30
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FROM,
      O => Ucore_Uusb_syn28447
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2849 : X_LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Uepdec_C606_C3,
      ADR1 => Ucore_Uusb_Uglue_bytecount(1),
      ADR2 => Ucore_din(7),
      ADR3 => Ucore_din(15),
      O => Ucore_Uusb_syn8277_GROM
    );
  Ucore_Uusb_syn8277_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8277_GROM,
      O => Ucore_Uusb_syn8277
    );
  Ucore_Uusb_C3843 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_rxd(5),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_BUS131(5),
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_BUS67_5_FROM
    );
  Ucore_Uusb_C3842 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_rxd(4),
      ADR1 => Ucore_Uusb_BUS131(4),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_Uusb_BUS67_5_GROM
    );
  Ucore_Uusb_Uusb_BUS67_5_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS67_5_FROM,
      O => Ucore_Uusb_Uusb_BUS67(5)
    );
  Ucore_Uusb_Uusb_BUS67_5_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS67_5_GROM,
      O => Ucore_Uusb_Uusb_BUS67(4)
    );
  Ucore_Uusb_C3826 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(6),
      ADR2 => Ucore_Uusb_Uuc_AO(6),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_sel,
      O => Ucore_Uusb_Uuc_BUS10875_6_FROM
    );
  Ucore_Uusb_C3566 : X_LUT4
    generic map(
      INIT => X"B080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10875(7),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10875(6),
      O => Ucore_Uusb_Uuc_BUS10875_6_GROM
    );
  Ucore_Uusb_Uuc_BUS10875_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_6_FROM,
      O => Ucore_Uusb_Uuc_BUS10875(6)
    );
  Ucore_Uusb_Uuc_BUS10875_6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_BUS10875_6_GROM,
      O => Ucore_Uusb_syn26968
    );
  Ucore_Uusb_C3818 : X_LUT4
    generic map(
      INIT => X"FFDF"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5618,
      ADR1 => Ucore_Uusb_Uuc_BUS12659(0),
      ADR2 => Ucore_Uusb_Uuc_BUS12659(6),
      ADR3 => Ucore_Uusb_Uuc_BUS12659(1),
      O => Ucore_Uusb_syn5161_FROM
    );
  Ucore_Uusb_C3809 : X_LUT4
    generic map(
      INIT => X"00FA"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(4),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(5),
      ADR3 => Ucore_Uusb_syn5161,
      O => Ucore_Uusb_syn5161_GROM
    );
  Ucore_Uusb_syn5161_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5161_FROM,
      O => Ucore_Uusb_syn5161
    );
  Ucore_Uusb_syn5161_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5161_GROM,
      O => Ucore_Uusb_syn22957
    );
  Ucore_Uusb_C3754 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5294_FROM
    );
  Ucore_Uusb_C3733 : X_LUT4
    generic map(
      INIT => X"4080"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR2 => Ucore_Uusb_syn5294,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(3),
      O => Ucore_Uusb_syn5294_GROM
    );
  Ucore_Uusb_syn5294_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5294_FROM,
      O => Ucore_Uusb_syn5294
    );
  Ucore_Uusb_syn5294_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5294_GROM,
      O => Ucore_Uusb_syn26775
    );
  Ucore_Uusb_C3746 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5869,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C661,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C677,
      ADR3 => Ucore_Uusb_syn26572,
      O => Ucore_Uusb_syn20067_FROM
    );
  Ucore_Uusb_C3606 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_syn5292,
      ADR3 => Ucore_Uusb_syn20067,
      O => Ucore_Uusb_syn20067_GROM
    );
  Ucore_Uusb_syn20067_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20067_FROM,
      O => Ucore_Uusb_syn20067
    );
  Ucore_Uusb_syn20067_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20067_GROM,
      O => Ucore_Uusb_syn6213
    );
  Ucore_Uusb_C3666 : X_LUT4
    generic map(
      INIT => X"CECC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5340,
      ADR1 => Ucore_Uusb_syn26677,
      ADR2 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR3 => Ucore_Uusb_Uuc_BUS10881(0),
      O => Ucore_Uusb_syn26678_FROM
    );
  Ucore_Uusb_C3665 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6257,
      ADR1 => Ucore_Uusb_Uuc_BUS10875(5),
      ADR2 => Ucore_Uusb_syn5917,
      ADR3 => Ucore_Uusb_syn26678,
      O => Ucore_Uusb_syn26678_GROM
    );
  Ucore_Uusb_syn26678_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26678_FROM,
      O => Ucore_Uusb_syn26678
    );
  Ucore_Uusb_syn26678_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26678_GROM,
      O => Ucore_Uusb_syn26679
    );
  Ucore_Uusb_C2954 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      O => Ucore_Uusb_syn7962_FROM
    );
  Ucore_Uusb_C2953 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298,
      ADR3 => Ucore_Uusb_syn7962,
      O => Ucore_Uusb_syn7962_GROM
    );
  Ucore_Uusb_syn7962_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7962_FROM,
      O => Ucore_Uusb_syn7962
    );
  Ucore_Uusb_syn7962_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7962_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12
    );
  Ucore_Uusb_C2866 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5304,
      ADR1 => Ucore_din(1),
      ADR2 => Ucore_Uusb_syn5303,
      ADR3 => Ucore_din(9),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FROM
    );
  Ucore_Uusb_C2865 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5164,
      ADR1 => Ucore_Uusb_Uusb_BUS8585(1),
      ADR2 => Ucore_Uusb_syn28418,
      ADR3 => Ucore_Uusb_syn28420,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N12
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FROM,
      O => Ucore_Uusb_syn28420
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_high_temp2_fast_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_high_temp2_fast_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3835 : X_LUT4
    generic map(
      INIT => X"000C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_FROM
    );
  Ucore_Uusb_C3834 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C11_C1
    );
  Ucore_Uusb_C3819 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS12659(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_BUS12659(2),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5618_GROM
    );
  Ucore_Uusb_syn5618_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5618_GROM,
      O => Ucore_Uusb_syn5618
    );
  Ucore_Uusb_C3771 : X_LUT4
    generic map(
      INIT => X"D444"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C461_C0,
      ADR2 => Ucore_Uusb_syn26073,
      ADR3 => Ucore_Uusb_syn5717,
      O => Ucore_Uusb_syn5725_FROM
    );
  Ucore_Uusb_C3770 : X_LUT4
    generic map(
      INIT => X"7D14"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C458_C8,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR3 => Ucore_Uusb_syn5725,
      O => Ucore_Uusb_syn5725_GROM
    );
  Ucore_Uusb_syn5725_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5725_FROM,
      O => Ucore_Uusb_syn5725
    );
  Ucore_Uusb_syn5725_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5725_GROM,
      O => Ucore_Uusb_syn5736
    );
  Ucore_Uusb_C3763 : X_LUT4
    generic map(
      INIT => X"C9C9"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26076,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C433_C2_C5,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => VCC,
      O => Ucore_Uusb_syn26085_FROM
    );
  Ucore_Uusb_C3741 : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn23229,
      ADR1 => Ucore_Uusb_syn20388,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C689,
      ADR3 => Ucore_Uusb_syn26085,
      O => Ucore_Uusb_syn26085_GROM
    );
  Ucore_Uusb_syn26085_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26085_FROM,
      O => Ucore_Uusb_syn26085
    );
  Ucore_Uusb_syn26085_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26085_GROM,
      O => Ucore_Uusb_syn26581
    );
  Ucore_Uusb_C3691 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => Ucore_Uusb_syn5910,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(1),
      O => Ucore_Uusb_syn5237_FROM
    );
  Ucore_Uusb_C3690 : X_LUT4
    generic map(
      INIT => X"AA88"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(2),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn5237,
      O => Ucore_Uusb_syn5237_GROM
    );
  Ucore_Uusb_syn5237_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5237_FROM,
      O => Ucore_Uusb_syn5237
    );
  Ucore_Uusb_syn5237_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5237_GROM,
      O => Ucore_Uusb_syn6018
    );
  Ucore_Uusb_C3683 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn20383,
      ADR1 => Ucore_Uusb_syn6004,
      ADR2 => Ucore_Uusb_syn6023,
      ADR3 => Ucore_Uusb_syn26629,
      O => Ucore_Uusb_Uuc_SPO_6_FROM
    );
  Ucore_Uusb_C3673 : X_LUT4
    generic map(
      INIT => X"FAAA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26657,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR3 => Ucore_Uusb_syn6024,
      O => Ucore_Uusb_Uuc_SPO_6_GROM
    );
  Ucore_Uusb_Uuc_SPO_6_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_6_FROM,
      O => Ucore_Uusb_syn6024
    );
  Ucore_Uusb_Uuc_SPO_6_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_6_GROM,
      O => Ucore_Uusb_Uuc_DBUS(6)
    );
  Ucore_Uusb_Uuc_SPO_6_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_6_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3675 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26648,
      ADR1 => Ucore_Uusb_syn26649,
      ADR2 => Ucore_Uusb_syn26650,
      ADR3 => Ucore_Uusb_syn26647,
      O => Ucore_Uusb_syn26656_FROM
    );
  Ucore_Uusb_C3674 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26646,
      ADR1 => Ucore_Uusb_syn26645,
      ADR2 => Ucore_Uusb_syn26651,
      ADR3 => Ucore_Uusb_syn26656,
      O => Ucore_Uusb_syn26656_GROM
    );
  Ucore_Uusb_syn26656_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26656_FROM,
      O => Ucore_Uusb_syn26656
    );
  Ucore_Uusb_syn26656_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26656_GROM,
      O => Ucore_Uusb_syn26657
    );
  Ucore_Uusb_C3595 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26867,
      ADR1 => Ucore_Uusb_syn26857,
      ADR2 => Ucore_Uusb_syn26862,
      ADR3 => Ucore_Uusb_syn26856,
      O => Ucore_Uusb_Uuc_SPO_2_FROM
    );
  Ucore_Uusb_C3594 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6225,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR2 => Ucore_Uusb_syn26841,
      ADR3 => Ucore_Uusb_syn26868,
      O => Ucore_Uusb_Uuc_SPO_2_GROM
    );
  Ucore_Uusb_Uuc_SPO_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_2_FROM,
      O => Ucore_Uusb_syn26868
    );
  Ucore_Uusb_Uuc_SPO_2_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_2_GROM,
      O => Ucore_Uusb_Uuc_DBUS(2)
    );
  Ucore_Uusb_Uuc_SPO_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3587 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6213,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_syn20137,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C690,
      O => Ucore_Uusb_syn26889_FROM
    );
  Ucore_Uusb_C3586 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10875(1),
      ADR1 => Ucore_Uusb_syn26887,
      ADR2 => Ucore_Uusb_syn6260,
      ADR3 => Ucore_Uusb_syn26889,
      O => Ucore_Uusb_syn26889_GROM
    );
  Ucore_Uusb_syn26889_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26889_FROM,
      O => Ucore_Uusb_syn26889
    );
  Ucore_Uusb_syn26889_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26889_GROM,
      O => Ucore_Uusb_syn26890
    );
  Ucore_Uusb_C3579 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C357,
      ADR1 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR2 => Ucore_Uusb_Uuc_AO(1),
      ADR3 => Ucore_Uusb_Uuc_BO(1),
      O => Ucore_Uusb_syn26910_FROM
    );
  Ucore_Uusb_C3578 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26909,
      ADR1 => Ucore_Uusb_syn26908,
      ADR2 => Ucore_Uusb_syn26907,
      ADR3 => Ucore_Uusb_syn26910,
      O => Ucore_Uusb_syn26910_GROM
    );
  Ucore_Uusb_syn26910_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26910_FROM,
      O => Ucore_Uusb_syn26910
    );
  Ucore_Uusb_syn26910_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26910_GROM,
      O => Ucore_Uusb_syn26916
    );
  Ucore_Uusb_C3836 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_FROM
    );
  Ucore_Uusb_C2978 : X_LUT4
    generic map(
      INIT => X"9911"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12_GROM,
      O => Ucore_Uusb_syn28242
    );
  Ucore_Uusb_C3764 : X_LUT4
    generic map(
      INIT => X"BD18"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_syn5736,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C458_C13,
      O => Ucore_Uusb_syn26076_FROM
    );
  Ucore_Uusb_C3323 : X_LUT4
    generic map(
      INIT => X"45DF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR2 => Ucore_Uusb_Uuc_BUS10875(7),
      ADR3 => Ucore_Uusb_syn26076,
      O => Ucore_Uusb_syn26076_GROM
    );
  Ucore_Uusb_syn26076_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26076_FROM,
      O => Ucore_Uusb_syn26076
    );
  Ucore_Uusb_syn26076_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26076_GROM,
      O => Ucore_Uusb_syn6957
    );
  Ucore_Uusb_C3756 : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(3),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_syn5324_FROM
    );
  Ucore_Uusb_C3334 : X_LUT4
    generic map(
      INIT => X"F500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_syn5324,
      O => Ucore_Uusb_syn5324_GROM
    );
  Ucore_Uusb_syn5324_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5324_FROM,
      O => Ucore_Uusb_syn5324
    );
  Ucore_Uusb_syn5324_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5324_GROM,
      O => Ucore_Uusb_syn6908
    );
  Ucore_Uusb_C3748 : X_LUT4
    generic map(
      INIT => X"EA40"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(7),
      ADR1 => Ucore_Uusb_syn5667,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR3 => Ucore_Uusb_Uuc_Ualu_C593,
      O => Ucore_Uusb_syn26569_FROM
    );
  Ucore_Uusb_C3747 : X_LUT4
    generic map(
      INIT => X"FFE2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C589,
      ADR1 => Ucore_Uusb_Uuc_BUS10875(0),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C597,
      ADR3 => Ucore_Uusb_syn26569,
      O => Ucore_Uusb_syn26569_GROM
    );
  Ucore_Uusb_syn26569_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26569_FROM,
      O => Ucore_Uusb_syn26569
    );
  Ucore_Uusb_syn26569_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26569_GROM,
      O => Ucore_Uusb_syn26572
    );
  Ucore_Uusb_C3692 : X_LUT4
    generic map(
      INIT => X"8777"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5750,
      ADR1 => Ucore_Uusb_syn5751,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C433_C0_C3,
      ADR3 => Ucore_Uusb_syn23094,
      O => Ucore_Uusb_syn20383_GROM
    );
  Ucore_Uusb_syn20383_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20383_GROM,
      O => Ucore_Uusb_syn20383
    );
  Ucore_Uusb_C3668 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(1),
      O => Ucore_Uusb_syn6071_FROM
    );
  Ucore_Uusb_C3667 : X_LUT4
    generic map(
      INIT => X"FFF4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR2 => Ucore_Uusb_syn5310,
      ADR3 => Ucore_Uusb_syn6071,
      O => Ucore_Uusb_syn6071_GROM
    );
  Ucore_Uusb_syn6071_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6071_FROM,
      O => Ucore_Uusb_syn6071
    );
  Ucore_Uusb_syn6071_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn6071_GROM,
      O => Ucore_Uusb_syn26677
    );
  Ucore_Uusb_C2788 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => Ucore_Uusb_syn28617,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N84,
      ADR3 => Ucore_Uusb_syn8470,
      O => Ucore_Uusb_syn28620_FROM
    );
  Ucore_Uusb_C2787 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(0),
      ADR2 => Ucore_Uusb_syn28608,
      ADR3 => Ucore_Uusb_syn28620,
      O => Ucore_Uusb_syn28620_GROM
    );
  Ucore_Uusb_syn28620_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28620_FROM,
      O => Ucore_Uusb_syn28620
    );
  Ucore_Uusb_syn28620_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28620_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C2_N9
    );
  Ucore_Uusb_C3829 : X_LUT4
    generic map(
      INIT => X"3020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Uctrl_Ucsp_C167,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2),
      ADR2 => Ucore_Uusb_syn5539,
      ADR3 => Ucore_Uusb_syn26236,
      O => Ucore_Uusb_syn5544_FROM
    );
  Ucore_Uusb_C3398 : X_LUT4
    generic map(
      INIT => X"0300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2,
      ADR2 => Ucore_Uusb_Uglue_N33,
      ADR3 => Ucore_Uusb_syn5544,
      O => Ucore_Uusb_syn5544_GROM
    );
  Ucore_Uusb_syn5544_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5544_FROM,
      O => Ucore_Uusb_syn5544
    );
  Ucore_Uusb_syn5544_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5544_GROM,
      O => Ucore_Uusb_Uusb_Uep0ctrl_S_1_cell0
    );
  Ucore_Uusb_C3781 : X_LUT4
    generic map(
      INIT => X"1C50"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_syn23133,
      ADR2 => Ucore_Uusb_syn26072,
      ADR3 => Ucore_Uusb_Uuc_Ualu_C424_C2_C5,
      O => Ucore_Uusb_syn26082_FROM
    );
  Ucore_Uusb_C3778 : X_LUT4
    generic map(
      INIT => X"2700"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR2 => Ucore_Uusb_syn20364,
      ADR3 => Ucore_Uusb_syn26082,
      O => Ucore_Uusb_syn26082_GROM
    );
  Ucore_Uusb_syn26082_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26082_FROM,
      O => Ucore_Uusb_syn26082
    );
  Ucore_Uusb_syn26082_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26082_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C433_C0_C3
    );
  Ucore_Uusb_C3757 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(4),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn5292,
      O => Ucore_Uusb_Uuc_Ualu_C677_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C677_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C677_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C677
    );
  Ucore_Uusb_C3685 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6012,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR2 => Ucore_Uusb_syn6007,
      ADR3 => Ucore_Uusb_Uuc_BUS10875(6),
      O => Ucore_Uusb_syn26628_FROM
    );
  Ucore_Uusb_C3684 : X_LUT4
    generic map(
      INIT => X"FFBA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6018,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR3 => Ucore_Uusb_syn26628,
      O => Ucore_Uusb_syn26628_GROM
    );
  Ucore_Uusb_syn26628_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26628_FROM,
      O => Ucore_Uusb_syn26628
    );
  Ucore_Uusb_syn26628_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26628_GROM,
      O => Ucore_Uusb_syn26629
    );
  Ucore_Uusb_C3669 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(7),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C585,
      ADR3 => VCC,
      O => Ucore_Uusb_syn5310_FROM
    );
  Ucore_Uusb_C3551 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR3 => Ucore_Uusb_syn5310,
      O => Ucore_Uusb_syn5310_GROM
    );
  Ucore_Uusb_syn5310_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5310_FROM,
      O => Ucore_Uusb_syn5310
    );
  Ucore_Uusb_syn5310_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5310_GROM,
      O => Ucore_Uusb_syn26988
    );
  Ucore_Uusb_C3597 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_AO(2),
      ADR1 => Ucore_Uusb_Uuc_BO(2),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR3 => Ucore_Uusb_Uuc_Udmux_C357,
      O => Ucore_Uusb_syn26861_FROM
    );
  Ucore_Uusb_C3596 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26859,
      ADR1 => Ucore_Uusb_syn26858,
      ADR2 => Ucore_Uusb_syn26860,
      ADR3 => Ucore_Uusb_syn26861,
      O => Ucore_Uusb_syn26861_GROM
    );
  Ucore_Uusb_syn26861_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26861_FROM,
      O => Ucore_Uusb_syn26861
    );
  Ucore_Uusb_syn26861_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26861_GROM,
      O => Ucore_Uusb_syn26867
    );
  Ucore_Uusb_C3589 : X_LUT4
    generic map(
      INIT => X"88F8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C665,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(5),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C675,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(1),
      O => Ucore_Uusb_syn26885_FROM
    );
  Ucore_Uusb_C3588 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6265,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(4),
      ADR2 => Ucore_Uusb_syn5310,
      ADR3 => Ucore_Uusb_syn26885,
      O => Ucore_Uusb_syn26885_GROM
    );
  Ucore_Uusb_syn26885_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26885_FROM,
      O => Ucore_Uusb_syn26885
    );
  Ucore_Uusb_syn26885_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26885_GROM,
      O => Ucore_Uusb_syn26887
    );
  Ucore_Uusb_C2981 : X_LUT4
    generic map(
      INIT => X"7500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FROM
    );
  Ucore_Uusb_C2979 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5279,
      ADR1 => Ucore_Uusb_syn28235,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290,
      ADR3 => Ucore_Uusb_syn7925,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N50
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FROM,
      O => Ucore_Uusb_syn7925
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2982 : X_LUT4
    generic map(
      INIT => X"0101"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR3 => VCC,
      O => Ucore_Uusb_syn5279_FROM
    );
  Ucore_Uusb_C2957 : X_LUT4
    generic map(
      INIT => X"1164"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      O => Ucore_Uusb_syn5279_GROM
    );
  Ucore_Uusb_syn5279_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5279_FROM,
      O => Ucore_Uusb_syn5279
    );
  Ucore_Uusb_syn5279_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5279_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C23_N9
    );
  Ucore_Uusb_C2869 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5304,
      ADR1 => Ucore_din(0),
      ADR2 => Ucore_Uusb_syn5303,
      ADR3 => Ucore_din(8),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FROM
    );
  Ucore_Uusb_C2868 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5164,
      ADR1 => Ucore_Uusb_syn28409,
      ADR2 => Ucore_Uusb_Uusb_BUS8585(0),
      ADR3 => Ucore_Uusb_syn28411,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N6
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FROM,
      O => Ucore_Uusb_syn28411
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2789 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04,
      O => Ucore_Uusb_syn28617_GROM
    );
  Ucore_Uusb_syn28617_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28617_GROM,
      O => Ucore_Uusb_syn28617
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3790 : X_LUT4
    generic map(
      INIT => X"174D"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR1 => Ucore_Uusb_Uuc_Ualu_C447_C8,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C419_C0_C4,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(0),
      O => Ucore_Uusb_syn5686_FROM
    );
  Ucore_Uusb_C3784 : X_LUT4
    generic map(
      INIT => X"48DE"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => Ucore_Uusb_syn5686,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C447_C13,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(2),
      O => Ucore_Uusb_syn5686_GROM
    );
  Ucore_Uusb_syn5686_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5686_FROM,
      O => Ucore_Uusb_syn5686
    );
  Ucore_Uusb_syn5686_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5686_GROM,
      O => Ucore_Uusb_syn5697
    );
  Ucore_Uusb_C3782 : X_LUT4
    generic map(
      INIT => X"4E27"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(3),
      ADR1 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR2 => Ucore_Uusb_Uuc_Ualu_C447_C18,
      ADR3 => Ucore_Uusb_syn5697,
      O => Ucore_Uusb_syn26072_FROM
    );
  Ucore_Uusb_C3774 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uuc_ALUOP(1),
      ADR3 => Ucore_Uusb_syn26072,
      O => Ucore_Uusb_syn26072_GROM
    );
  Ucore_Uusb_syn26072_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26072_FROM,
      O => Ucore_Uusb_syn26072
    );
  Ucore_Uusb_syn26072_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26072_GROM,
      O => Ucore_Uusb_syn5717
    );
  Ucore_Uusb_C3598 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(2),
      ADR1 => Ucore_Uusb_Uuc_Udmux_C345,
      ADR2 => Ucore_Uusb_Uuc_Udmux_C351,
      ADR3 => Ucore_Uusb_Uuc_SPO(2),
      O => Ucore_Uusb_syn26860_GROM
    );
  Ucore_Uusb_syn26860_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26860_GROM,
      O => Ucore_Uusb_syn26860
    );
  Ucore_Uusb_C2990 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_FROM
    );
  Ucore_Uusb_C2949 : X_LUT4
    generic map(
      INIT => X"FCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9
    );
  Ucore_Uusb_C2974 : X_LUT4
    generic map(
      INIT => X"000A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_FROM
    );
  Ucore_Uusb_C2973 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C302,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_GROM
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C298_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9
    );
  Ucore_Uusb_C2886 : X_LUT4
    generic map(
      INIT => X"55FF"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1),
      O => Ucore_Uusb_syn8151_FROM
    );
  Ucore_Uusb_C2885 : X_LUT4
    generic map(
      INIT => X"F575"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2,
      ADR3 => Ucore_Uusb_syn8151,
      O => Ucore_Uusb_syn8151_GROM
    );
  Ucore_Uusb_syn8151_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8151_FROM,
      O => Ucore_Uusb_syn8151
    );
  Ucore_Uusb_syn8151_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn8151_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N242,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_2_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(2)
    );
  Ucore_Uusb_Uuc_INCO_2_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_2_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N244,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_4_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(4)
    );
  Ucore_Uusb_Uuc_INCO_4_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_4_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N247,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_6_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(7)
    );
  Ucore_Uusb_Uuc_INCO_6_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N246,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_6_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(6)
    );
  Ucore_Uusb_Uuc_INCO_6_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_6_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N249,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_8_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(9)
    );
  Ucore_Uusb_Uuc_INCO_8_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_8_FFY_RST
    );
  Ucore_Uusb_C2878 : X_LUT4
    generic map(
      INIT => X"0044"
    )
    port map (
      ADR0 => Ucore_Uusb_syn6626,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_S_11_cell0,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FROM
    );
  Ucore_Uusb_C2875 : X_LUT4
    generic map(
      INIT => X"5A00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C157,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N10
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C157
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3839 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(1),
      ADR1 => Ucore_Uusb_syn5458,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uusb_rxd(1),
      O => Ucore_Uusb_Uusb_BUS67_1_GROM
    );
  Ucore_Uusb_Uusb_BUS67_1_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_BUS67_1_GROM,
      O => Ucore_Uusb_Uusb_BUS67(1)
    );
  Ucore_Uusb_C3599 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C333,
      ADR1 => Ucore_Uusb_Uuc_BUFO8(2),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C341,
      ADR3 => Ucore_Uusb_Uuc_RO(2),
      O => Ucore_Uusb_syn26859_GROM
    );
  Ucore_Uusb_syn26859_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26859_GROM,
      O => Ucore_Uusb_syn26859
    );
  Ucore_Uusb_C2879 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET1186,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(2),
      O => Ucore_Uusb_N1540_GROM
    );
  Ucore_Uusb_N1540_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_N1540_GROM,
      O => Ucore_Uusb_N1540
    );
  Ucore_Uusb_C3792 : X_LUT4
    generic map(
      INIT => X"202A"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Ualu_C424_C0_C3,
      ADR1 => Ucore_Uusb_Uuc_BUS10881(1),
      ADR2 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR3 => Ucore_Uusb_syn20137,
      O => Ucore_Uusb_syn26461_FROM
    );
  Ucore_Uusb_C3787 : X_LUT4
    generic map(
      INIT => X"048C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(2),
      ADR1 => Ucore_Uusb_syn26461,
      ADR2 => Ucore_Uusb_syn20278,
      ADR3 => Ucore_Uusb_Uuc_BUS10881(2),
      O => Ucore_Uusb_syn26461_GROM
    );
  Ucore_Uusb_syn26461_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26461_FROM,
      O => Ucore_Uusb_syn26461
    );
  Ucore_Uusb_syn26461_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26461_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C424_C2_C5
    );
  Ucore_Uusb_C3696 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26597,
      ADR1 => Ucore_Uusb_syn26602,
      ADR2 => Ucore_Uusb_syn26591,
      ADR3 => Ucore_Uusb_syn26592,
      O => Ucore_Uusb_Uuc_SPO_7_FROM
    );
  Ucore_Uusb_C3695 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C353,
      ADR1 => Ucore_Uusb_syn26582,
      ADR2 => Ucore_Uusb_syn26581,
      ADR3 => Ucore_Uusb_syn26603,
      O => Ucore_Uusb_Uuc_SPO_7_GROM
    );
  Ucore_Uusb_Uuc_SPO_7_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_7_FROM,
      O => Ucore_Uusb_syn26603
    );
  Ucore_Uusb_Uuc_SPO_7_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_SPO_7_GROM,
      O => Ucore_Uusb_Uuc_DBUS(7)
    );
  Ucore_Uusb_Uuc_SPO_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_SPO_7_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2984 : X_LUT4
    generic map(
      INIT => X"4C4C"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2),
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(0),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      ADR3 => VCC,
      O => Ucore_Uusb_syn28225_FROM
    );
  Ucore_Uusb_C2983 : X_LUT4
    generic map(
      INIT => X"FFF7"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292,
      ADR2 => Ucore_Uusb_syn7912,
      ADR3 => Ucore_Uusb_syn28225,
      O => Ucore_Uusb_syn28225_GROM
    );
  Ucore_Uusb_syn28225_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28225_FROM,
      O => Ucore_Uusb_syn28225
    );
  Ucore_Uusb_syn28225_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn28225_GROM,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C17_N11
    );
  Ucore_Uusb_C3849 : X_LUT4
    generic map(
      INIT => X"0207"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2),
      ADR1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3),
      ADR2 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0),
      ADR3 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1),
      O => Ucore_Uusb_syn5458_FROM
    );
  Ucore_Uusb_C3838 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => Ucore_Uusb_BUS131(0),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_rxd(0),
      ADR3 => Ucore_Uusb_syn5458,
      O => Ucore_Uusb_syn5458_GROM
    );
  Ucore_Uusb_syn5458_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5458_FROM,
      O => Ucore_Uusb_syn5458
    );
  Ucore_Uusb_syn5458_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5458_GROM,
      O => Ucore_Uusb_Uusb_BUS67(0)
    );
  Ucore_Uusb_C3786 : X_LUT4
    generic map(
      INIT => X"3210"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR1 => Ucore_Uusb_syn5667,
      ADR2 => Ucore_Uusb_Uuc_AO(3),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(3),
      O => Ucore_Uusb_Uuc_Ualu_C447_C18_FROM
    );
  Ucore_Uusb_C3785 : X_LUT4
    generic map(
      INIT => X"5410"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5667,
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_AO(2),
      ADR3 => Ucore_Uusb_Uuc_Utmp2_TMP2(2),
      O => Ucore_Uusb_Uuc_Ualu_C447_C18_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C447_C18_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C447_C18_FROM,
      O => Ucore_Uusb_Uuc_Ualu_C447_C18
    );
  Ucore_Uusb_Uuc_Ualu_C447_C18_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C447_C18_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C447_C13
    );
  Ucore_Uusb_C3777 : X_LUT4
    generic map(
      INIT => X"00E4"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR1 => Ucore_Uusb_Uuc_AO(6),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_TMP2(6),
      ADR3 => Ucore_Uusb_syn5667,
      O => Ucore_Uusb_Uuc_Ualu_C458_C13_GROM
    );
  Ucore_Uusb_Uuc_Ualu_C458_C13_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uuc_Ualu_C458_C13_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C458_C13
    );
  Ucore_Uusb_C3769 : X_LUT4
    generic map(
      INIT => X"FF96"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_BUS10881(6),
      ADR1 => Ucore_Uusb_syn5736,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C458_C13,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(2),
      O => Ucore_Uusb_syn5750_FROM
    );
  Ucore_Uusb_C3765 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => Ucore_Uusb_syn5751,
      ADR1 => Ucore_Uusb_syn23094,
      ADR2 => Ucore_Uusb_Uuc_Ualu_C433_C0_C3,
      ADR3 => Ucore_Uusb_syn5750,
      O => Ucore_Uusb_syn5750_GROM
    );
  Ucore_Uusb_syn5750_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5750_FROM,
      O => Ucore_Uusb_syn5750
    );
  Ucore_Uusb_syn5750_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5750_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C433_C2_C5
    );
  Ucore_Uusb_C2985 : X_LUT4
    generic map(
      INIT => X"0050"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(3),
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2),
      O => Ucore_Uusb_syn7912_GROM
    );
  Ucore_Uusb_syn7912_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn7912_GROM,
      O => Ucore_Uusb_syn7912
    );
  Ucore_Uusb_C2977 : X_LUT4
    generic map(
      INIT => X"D580"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C292,
      ADR2 => Ucore_Uusb_syn28225,
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FROM
    );
  Ucore_Uusb_C2976 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn7896,
      ADR1 => Ucore_Uusb_syn28242,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn28243,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N22
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FROM,
      O => Ucore_Uusb_syn28243
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3698 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_Udmux_C359,
      ADR1 => Ucore_Uusb_Uuc_AO(7),
      ADR2 => Ucore_Uusb_Uuc_Udmux_C357,
      ADR3 => Ucore_Uusb_Uuc_BO(7),
      O => Ucore_Uusb_syn26596_FROM
    );
  Ucore_Uusb_C3697 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => Ucore_Uusb_syn26594,
      ADR1 => Ucore_Uusb_syn26595,
      ADR2 => Ucore_Uusb_syn26593,
      ADR3 => Ucore_Uusb_syn26596,
      O => Ucore_Uusb_syn26596_GROM
    );
  Ucore_Uusb_syn26596_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26596_FROM,
      O => Ucore_Uusb_syn26596
    );
  Ucore_Uusb_syn26596_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn26596_GROM,
      O => Ucore_Uusb_syn26602
    );
  Ucore_Uusb_C2988 : X_LUT4
    generic map(
      INIT => X"D1D1"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      ADR1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2),
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1),
      ADR3 => VCC,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FROM
    );
  Ucore_Uusb_C2987 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C290,
      ADR1 => Ucore_Uusb_syn7896,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_cell12,
      ADR3 => Ucore_Uusb_syn7900,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N36
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FROM,
      O => Ucore_Uusb_syn7900
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3797 : X_LUT4
    generic map(
      INIT => X"0035"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_AO(0),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_TMP2(0),
      ADR2 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR3 => Ucore_Uusb_syn5667,
      O => Ucore_Uusb_syn20065_FROM
    );
  Ucore_Uusb_C3796 : X_LUT4
    generic map(
      INIT => X"3328"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_PO(7),
      ADR1 => Ucore_Uusb_Uuc_BUS10881(0),
      ADR2 => Ucore_Uusb_syn20065,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(2),
      O => Ucore_Uusb_syn20065_GROM
    );
  Ucore_Uusb_syn20065_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20065_FROM,
      O => Ucore_Uusb_syn20065
    );
  Ucore_Uusb_syn20065_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn20065_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C424_C0_C3
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C3798 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_ALUOP(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_Uuc_ALUOP(1),
      O => Ucore_Uusb_syn5667_FROM
    );
  Ucore_Uusb_C3791 : X_LUT4
    generic map(
      INIT => X"00E2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uuc_AO(1),
      ADR1 => Ucore_Uusb_Uuc_Utmp2_sel,
      ADR2 => Ucore_Uusb_Uuc_Utmp2_TMP2(1),
      ADR3 => Ucore_Uusb_syn5667,
      O => Ucore_Uusb_syn5667_GROM
    );
  Ucore_Uusb_syn5667_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5667_FROM,
      O => Ucore_Uusb_syn5667
    );
  Ucore_Uusb_syn5667_YUSED : X_BUF
    port map (
      I => Ucore_Uusb_syn5667_GROM,
      O => Ucore_Uusb_Uuc_Ualu_C447_C8
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_ie_0 : X_LUT4
    generic map(
      INIT => X"0081"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => Ucore_Ufunc_resize_state(0),
      ADR2 => Ucore_Ufunc_resize_state(1),
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_ie_FROM
    );
  Ucore_Ufunc_un41_nextaddr_offset_i_a2 : X_LUT4
    generic map(
      INIT => X"1001"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(2),
      ADR1 => Ucore_Ufunc_resize_state(1),
      ADR2 => Ucore_Ufunc_resize_state(0),
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_ie_GROM
    );
  Ucore_Ufunc_ie_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ie_FROM,
      O => Ucore_Ufunc_ie
    );
  Ucore_Ufunc_ie_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_ie_GROM,
      O => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n
    );
  Ucore_Ufunc_sram_un3_doingwrite1 : X_LUT4
    generic map(
      INIT => X"0D0D"
    )
    port map (
      ADR0 => Ucore_Ufunc_presstate_3_Q,
      ADR1 => clk48x2,
      ADR2 => Ucore_Ufunc_sram_presstate(2),
      ADR3 => VCC,
      O => un3_doingwrite1_n_GROM
    );
  un3_doingwrite1_n_YUSED : X_BUF
    port map (
      I => un3_doingwrite1_n_GROM,
      O => un3_doingwrite1_n
    );
  Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_499 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => Ucore_Ufunc_r(7),
      ADR1 => Ucore_Ufunc_r(8),
      ADR2 => Ucore_Ufunc_r(9),
      ADR3 => Ucore_Ufunc_r(6),
      O => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_FROM
    );
  Ucore_Ufunc_un1_resize_doWrite27_i : X_LUT4
    generic map(
      INIT => X"DCCC"
    )
    port map (
      ADR0 => Ucore_Ufunc_N_567,
      ADR1 => Ucore_Ufunc_N_500,
      ADR2 => Ucore_Ufunc_N_520,
      ADR3 => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2,
      O => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_GROM
    );
  Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_FROM,
      O => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2
    );
  Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_un1_resize_doWrite27_i_a2_2_GROM,
      O => Ucore_Ufunc_nextresize_state_m2(0)
    );
  Ucore_Uusb_DI_1_BYMUX : X_INV
    port map (
      I => Ucore_Uusb_IT(1),
      O => Ucore_Uusb_DI_1_BYMUXNOT
    );
  Ucore_Uusb_DI_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_DI_1_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_10_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_10_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_N_253_i_500 : X_LUT4
    generic map(
      INIT => X"0454"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_state(3),
      ADR1 => Ucore_Ufunc_resize_doWrite_1,
      ADR2 => Ucore_Ufunc_resize_state(2),
      ADR3 => Ucore_Ufunc_N_429,
      O => Ucore_Ufunc_N_253_i_FROM
    );
  Ucore_Ufunc_nextresize_state_ss0 : X_LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      ADR0 => Ucore_Ufunc_resize_doWrite34,
      ADR1 => Ucore_Ufunc_nextresize_state_m2(0),
      ADR2 => Ucore_Ufunc_un37_nextresize_state,
      ADR3 => Ucore_Ufunc_resize_state(3),
      O => Ucore_Ufunc_N_253_i_GROM
    );
  Ucore_Ufunc_N_253_i_XUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_253_i_FROM,
      O => Ucore_Ufunc_N_253_i
    );
  Ucore_Ufunc_N_253_i_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_253_i_GROM,
      O => Ucore_Ufunc_nextresize_state_ss0_O
    );
  Ucore_Uusb_C2773 : X_LUT4
    generic map(
      INIT => X"FAF2"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1),
      ADR1 => Ucore_Uusb_N1552,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FROM
    );
  Ucore_Uusb_C2772 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Ucore_Uusb_syn8521,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C22_N11
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_XUSED : X_BUF
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FROM,
      O => Ucore_Uusb_syn8521
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_low_temp2_fast_1_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_low_temp2_fast_1_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_low_temp2_fast_3_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_low_temp2_fast_3_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_low_temp2_fast_5_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_low_temp2_fast_5_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_low_temp2_fast_7_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Ufunc_low_temp2_fast_7_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_N_246_i_501 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Ufunc_doneflag,
      ADR2 => VCC,
      ADR3 => Ucore_Ufunc_un1_ram_writeAddr_1,
      O => Ucore_Ufunc_N_246_i_GROM
    );
  Ucore_Ufunc_N_246_i_YUSED : X_BUF
    port map (
      I => Ucore_Ufunc_N_246_i_GROM,
      O => Ucore_Ufunc_N_246_i
    );
  Ucore_Uusb_C3228 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Ucore_Uusb_Uuc_Uctrl_CSP(1),
      ADR2 => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      ADR3 => VCC,
      O => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N129
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_0_BXMUX : X_INV
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP(0),
      O => Ucore_Uusb_Uuc_Uctrl_CSP_0_BXMUXNOT
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_0_SRMUX_OUTPUTNOT
    );
  Ucore_Uusb_C2956 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden(0),
      ADR3 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C22_N9
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_SRMUX : X_INV
    port map (
      I => sw1_p174_c,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_SRMUX_OUTPUTNOT
    );
  Ucore_Ufunc_addr_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_7_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(7)
    );
  Ucore_Ufunc_addr_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_9_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(9)
    );
  Ucore_Ufunc_addr_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_11_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(11)
    );
  Ucore_Ufunc_addr_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_14_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(14)
    );
  Ucore_Ufunc_addr_18_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_18_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_17_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(18)
    );
  Ucore_Ufunc_addr_16_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_16_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(16)
    );
  Ucore_Ufunc_addr_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_13_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(13)
    );
  Ucore_Ufunc_ram_readAddr_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(7),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(7)
    );
  Ucore_Ufunc_ram_readAddr_18_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(18),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_17_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(18)
    );
  Ucore_Ufunc_ram_readAddr_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(9),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(9)
    );
  Ucore_Ufunc_ram_readAddr_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(11),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(11)
    );
  Ucore_Ufunc_ram_readAddr_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(14),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(14)
    );
  Ucore_Ufunc_ram_readAddr_16_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(16),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(16)
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_11_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_11_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(11)
    );
  Ucore_Uusb_Uuc_PCO_11_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_11_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_12_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_12_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(12)
    );
  Ucore_Uusb_Uuc_PCO_12_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_12_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_13_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_13_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(13)
    );
  Ucore_Uusb_Uuc_PCO_13_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_13_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_15_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_15_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(15)
    );
  Ucore_Uusb_Uuc_PCO_15_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_15_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_14_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_14_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(14)
    );
  Ucore_Uusb_Uuc_PCO_14_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_14_FFX_RST
    );
  Ucore_Ufunc_sram_CELeftn : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => ram_ce_LOGIC_ZERO,
      CE => VCC,
      CLK => clk48x2,
      SET => ram_ce_OFF_SET,
      RST => GND,
      O => ram_ce_c
    );
  ram_ce_OFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => ram_ce_SRMUXNOT,
      O => ram_ce_OFF_SET
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_17_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(17),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a17_c_FFX_RST,
      O => a17_c
    );
  a17_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a17_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a17_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_18_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(18),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a18_c_FFX_RST,
      O => a18_c
    );
  a18_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a18_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a18_c_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_8_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_8_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(8)
    );
  Ucore_Uusb_Uuc_PCO_8_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_8_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_9_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_9_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(9)
    );
  Ucore_Uusb_Uuc_PCO_9_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_9_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_10_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_10_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(10)
    );
  Ucore_Uusb_Uuc_PCO_10_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_10_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(11),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a11_c_FFX_RST,
      O => a11_c
    );
  a11_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a11_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a11_c_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_OP_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(4)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_4_FFX_RST
    );
  Ucore_Ufunc_s_cur_oldRow_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(7),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(7)
    );
  Ucore_Ufunc_s_cur_oldRow_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(8),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(8)
    );
  Ucore_Ufunc_s_cur_oldRow_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(9),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(9)
    );
  Ucore_Ufunc_sram_writedatareg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(0),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_1_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(0)
    );
  Ucore_Ufunc_sram_writedatareg_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_1_FFY_RST
    );
  Ucore_Ufunc_sram_writedatareg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(1),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_1_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(1)
    );
  Ucore_Ufunc_sram_writedatareg_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_1_FFX_RST
    );
  Ucore_Ufunc_sram_writedatareg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(2),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_3_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(2)
    );
  Ucore_Ufunc_sram_writedatareg_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_3_FFY_RST
    );
  Ucore_Ufunc_sram_writedatareg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(3),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_3_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(3)
    );
  Ucore_Ufunc_sram_writedatareg_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_3_FFX_RST
    );
  Ucore_Ufunc_sram_writedatareg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(4),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_5_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(4)
    );
  Ucore_Ufunc_sram_writedatareg_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N12,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C13_N18,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFY_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(12),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a12_c_FFX_RST,
      O => a12_c
    );
  a12_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a12_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a12_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(13),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a13_c_FFX_RST,
      O => a13_c
    );
  a13_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a13_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a13_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(14),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a14_c_FFX_RST,
      O => a14_c
    );
  a14_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a14_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a14_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(15),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a15_c_FFX_RST,
      O => a15_c
    );
  a15_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a15_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a15_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_16_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(16),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a16_c_FFX_RST,
      O => a16_c
    );
  a16_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a16_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a16_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(6),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a6_c_FFX_RST,
      O => a6_c
    );
  a6_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a6_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a6_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(7),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a7_c_FFX_RST,
      O => a7_c
    );
  a7_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a7_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a7_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(8),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a8_c_FFX_RST,
      O => a8_c
    );
  a8_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a8_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a8_c_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(9),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a9_c_FFX_RST,
      O => a9_c
    );
  a9_c_FFX_RSTOR : X_OR2
    port map (
      I0 => a9_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a9_c_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_0_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_0_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(0)
    );
  Ucore_Uusb_Uuc_PCO_0_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_0_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_6_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_6_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(6)
    );
  Ucore_Uusb_Uuc_PCO_6_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_6_FFX_RST
    );
  Ucore_Uusb_Uuc_Upc_PC_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_PCO_7_F5MUX,
      CE => Ucore_Uusb_Uuc_PCWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PCO_7_FFX_RST,
      O => Ucore_Uusb_Uuc_PCO(7)
    );
  Ucore_Uusb_Uuc_PCO_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PCO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PCO_7_FFX_RST
    );
  Ucore_Ufunc_ram_readAddr_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(0),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(0)
    );
  Ucore_Ufunc_ram_readAddr_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(2),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(2)
    );
  Ucore_Ufunc_ram_readAddr_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(6),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(6)
    );
  Ucore_Ufunc_ram_readAddr_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(4),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(4)
    );
  Ucore_Ufunc_r_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(8),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(8)
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N241,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_0_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(1)
    );
  Ucore_Uusb_Uuc_INCO_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N240,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_0_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(0)
    );
  Ucore_Uusb_Uuc_INCO_0_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_0_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N243,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_2_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(3)
    );
  Ucore_Uusb_Uuc_INCO_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N245,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_4_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(5)
    );
  Ucore_Uusb_Uuc_INCO_4_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N248,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_8_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(8)
    );
  Ucore_Uusb_Uuc_INCO_8_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_8_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N251,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_10_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(11)
    );
  Ucore_Uusb_Uuc_INCO_10_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_10_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N255,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_14_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(15)
    );
  Ucore_Uusb_Uuc_INCO_14_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_14_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N250,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_10_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(10)
    );
  Ucore_Uusb_Uuc_INCO_10_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_10_FFX_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N253,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_12_FFY_RST,
      O => Ucore_Uusb_Uuc_INCO(13)
    );
  Ucore_Uusb_Uuc_INCO_12_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_12_FFY_RST
    );
  Ucore_Uusb_Uuc_Uinc_inco_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uinc_N252,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_INCO_12_FFX_RST,
      O => Ucore_Uusb_Uuc_INCO(12)
    );
  Ucore_Uusb_Uuc_INCO_12_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_INCO_12_FFX_RST
    );
  Ucore_Ufunc_r_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(1),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(1)
    );
  Ucore_Ufunc_r_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(3),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(3)
    );
  Ucore_Ufunc_r_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(5),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(5)
    );
  Ucore_Ufunc_r_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(0),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(0)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DSEL_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DSEL_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2128,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N3,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(0)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DSEL_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1006,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N9,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(1)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N963,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N14,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(2)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFY_RST
    );
  Ucore_Ufunc_r_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(2),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(2)
    );
  Ucore_Ufunc_r_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(4),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(4)
    );
  Ucore_Ufunc_r_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(7),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(7)
    );
  Ucore_Ufunc_r_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(9),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(9)
    );
  Ucore_Ufunc_r_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_r_s(6),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_r_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_r(6)
    );
  Ucore_Ufunc_i_18_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(18),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_18_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(18)
    );
  Ucore_Ufunc_i_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(14),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(14)
    );
  Ucore_Ufunc_i_16_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(16),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(16)
    );
  Ucore_Ufunc_ram_readAddr_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(1),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(1)
    );
  Ucore_Ufunc_ram_readAddr_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(12),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(12)
    );
  Ucore_Ufunc_ram_readAddr_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(3),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(3)
    );
  Ucore_Ufunc_ram_readAddr_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(5),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(5)
    );
  Ucore_Ufunc_ram_readAddr_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(8),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(8)
    );
  Ucore_Ufunc_ram_readAddr_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_readAddr_s(10),
      CE => Ucore_Ufunc_N_240_1,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_readAddr_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_readAddr(10)
    );
  Ucore_Ufunc_ram_writeAddr_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(10),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(10)
    );
  Ucore_Ufunc_ram_writeAddr_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(12),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(12)
    );
  Ucore_Ufunc_ram_writeAddr_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(15),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(15)
    );
  Ucore_Ufunc_ram_writeAddr_17_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(17),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(17)
    );
  Ucore_Ufunc_ram_writeAddr_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(14),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(14)
    );
  Ucore_Ufunc_i_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(1),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(1)
    );
  Ucore_Ufunc_i_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(5),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(5)
    );
  Ucore_Ufunc_i_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(3),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(3)
    );
  Ucore_Ufunc_i_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(0),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(0)
    );
  Ucore_Ufunc_ram_writeAddr_16_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(16),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(16)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_OP_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1654,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N19,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_3_FFX_RST,
      O => Ucore_Uusb_Uusb_rxd(3)
    );
  Ucore_Uusb_Uusb_rxd_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N24,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_5_FFY_RST,
      O => Ucore_Uusb_Uusb_rxd(4)
    );
  Ucore_Uusb_Uusb_rxd_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N29,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_5_FFX_RST,
      O => Ucore_Uusb_Uusb_rxd(5)
    );
  Ucore_Uusb_Uusb_rxd_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_OP_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1740,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N39,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_7_FFX_RST,
      O => Ucore_Uusb_Uusb_rxd(7)
    );
  Ucore_Uusb_Uusb_rxd_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_7_FFX_RST
    );
  Ucore_Ufunc_sram_writedatareg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(12),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_13_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(12)
    );
  Ucore_Ufunc_sram_writedatareg_13_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_13_FFY_RST
    );
  Ucore_Ufunc_sram_writedatareg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(13),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_13_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(13)
    );
  Ucore_Ufunc_sram_writedatareg_13_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_13_FFX_RST
    );
  Ucore_Ufunc_addr_offset_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(7),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(7)
    );
  Ucore_Ufunc_sram_writedatareg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(14),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_15_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(14)
    );
  Ucore_Ufunc_sram_writedatareg_15_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_15_FFY_RST
    );
  Ucore_Ufunc_addr_offset_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(8),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(8)
    );
  Ucore_Ufunc_sram_writedatareg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(15),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_15_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(15)
    );
  Ucore_Ufunc_sram_writedatareg_15_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_15_FFX_RST
    );
  Ucore_Ufunc_addr_offset_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(9),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(9)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(0)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_1_FFY_RST
    );
  Ucore_Ufunc_sram_presstate_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_presstate_3_GROM,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_presstate_3_FFY_RST,
      O => Ucore_Ufunc_presstate_3_Q
    );
  Ucore_Ufunc_presstate_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_presstate_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_presstate_3_FFY_RST
    );
  Ucore_Ufunc_resize_state_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_nextresize_state(3),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state(3)
    );
  Ucore_Ufunc_resize_state_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_nextresize_state(1),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state(1)
    );
  Ucore_Uusb_Uuc_Ubuf_relf_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_relf_FROM,
      CE => Ucore_Uusb_N1512,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_relf_FFX_RST,
      O => Ucore_Uusb_Uuc_Ubuf_relf
    );
  Ucore_Uusb_Uuc_Ubuf_relf_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Ubuf_relf_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_relf_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DWR_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N37,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_0_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N16,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C2_N3,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => fse0_p17_c_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_stuff2
    );
  fse0_p17_c_FFY_RSTOR : X_OR2
    port map (
      I0 => fse0_p17_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => fse0_p17_c_FFY_RST
    );
  Ucore_Ufunc_addr_offset_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(10),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(10)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N10,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(1)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N20,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(3)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N30,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(5)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_5_FFX_RST
    );
  Ucore_Ufunc_resize_state_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_395_i,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_0_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state(0)
    );
  Ucore_Ufunc_i_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(2),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(2)
    );
  Ucore_Ufunc_i_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(4),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(4)
    );
  Ucore_Ufunc_i_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(7),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(7)
    );
  Ucore_Ufunc_i_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(6),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(6)
    );
  Ucore_Ufunc_i_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(11),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_10_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(11)
    );
  Ucore_Ufunc_i_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_i_s(9),
      CE => Ucore_Ufunc_ie,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_i_8_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_i(9)
    );
  Ucore_Ufunc_s_cur_oldCol_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(7),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(7)
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C22_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_3_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(2)
    );
  Ucore_Uusb_Uuc_DPTRO_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C20_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_3_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(3)
    );
  Ucore_Uusb_Uuc_DPTRO_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_in_en_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C0_N5,
      CE => Ucore_Uusb_N1468,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_in_en_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_in_en
    );
  Ucore_Uusb_Uusb_Uep0ctrl_in_en_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_in_en_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_in_en_FFY_RST
    );
  Ucore_Ufunc_s_cur_oldCol_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(9),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(9)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_in_trac_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C25_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C30_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_NET1039_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_NET1024
    );
  Ucore_Uusb_Uusb_Usie_NET1039_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_NET1039_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_NET1039_FFY_RST
    );
  Ucore_Ufunc_din_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d9_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_9_SRMUX_OUTPUTNOT,
      O => Ucore_din(9)
    );
  Ucore_Ufunc_temp1_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(3),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(11)
    );
  Ucore_Ufunc_temp1_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(4),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(12)
    );
  Ucore_Ufunc_temp1_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(5),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(13)
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_3_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS12659(2)
    );
  Ucore_Uusb_Uuc_BUS12659_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_3_FFY_RST
    );
  Ucore_Ufunc_temp1_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(6),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(14)
    );
  Ucore_Ufunc_temp1_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_dout_15_Q,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(15)
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_1_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS12659(0)
    );
  Ucore_Uusb_Uuc_BUS12659_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_1_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS12659(1)
    );
  Ucore_Uusb_Uuc_BUS12659_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_3_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS12659(3)
    );
  Ucore_Uusb_Uuc_BUS12659_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_5_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS12659(4)
    );
  Ucore_Uusb_Uuc_BUS12659_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(0)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(1)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_5_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS12659(5)
    );
  Ucore_Uusb_Uuc_BUS12659_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(2)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(3)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS12659_6_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS12659(6)
    );
  Ucore_Uusb_Uuc_BUS12659_6_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS12659_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_OP_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1135,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_OP_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N225,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N18,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_5_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(5)
    );
  Ucore_Uusb_Uuc_PO_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DWR_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N36,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_2_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(2)
    );
  Ucore_Uusb_Uuc_PO_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_GROM,
      CE => Ucore_Uusb_N1540,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_valid_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N19,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(3)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_OP_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_OP_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_BC_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2904,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N39,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_0_FFY_RST
    );
  Ucore_Ufunc_high_temp2_fast_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(8),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(0)
    );
  Ucore_Ufunc_high_temp2_fast_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(9),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(1)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N15,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C33_N15,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(2)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N29,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(5)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1999,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DWR_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C30_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_14_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(14)
    );
  Ucore_Uusb_Uuc_DPTRO_14_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_14_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N74,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N26,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_8_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(8)
    );
  Ucore_Uusb_Uuc_BUFO8_8_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_8_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N81,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N26,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_9_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(9)
    );
  Ucore_Uusb_Uuc_BUFO8_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_9_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DSEL_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N572,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DSEL_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_utx0_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C12_N5,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => fse0_p17_c_FFX_RST,
      O => fse0_p17_c
    );
  fse0_p17_c_FFX_RSTOR : X_OR2
    port map (
      I0 => fse0_p17_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => fse0_p17_c_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_10_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N56,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(11)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_12_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N66,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(13)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_11_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N61,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(12)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_12_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_14_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N76,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(15)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_15_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_13_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N71,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(14)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_14_FFX_SET
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_aluop_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N24,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_ALUOP_0_FFY_RST,
      O => Ucore_Uusb_Uuc_ALUOP(0)
    );
  Ucore_Uusb_Uuc_ALUOP_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_ALUOP_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_OP_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_0_Q
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C10_N9,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C11_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crcclr2_0_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C3_N3,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_nrzi2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_GROM,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop2,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N20,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFY_RST
    );
  Ucore_Ufunc_resize_state_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_nextresize_state(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state(2)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_CLASS_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2689,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_OP_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_Q
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_OP_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_Q
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_OP_3_FFX_RST
    );
  Ucore_Ufunc_addr_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol(7),
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(2)
    );
  Ucore_Ufunc_addr_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_un1_nextaddr_s_1_n,
      CE => Ucore_Ufunc_resize_doWrite29,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr(1)
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N30,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_4_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(3)
    );
  Ucore_Uusb_Uuc_PO_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N48,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_1_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(0)
    );
  Ucore_Uusb_Uuc_PO_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N42,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_1_FFX_RST,
      O => Ucore_Uusb_Uuc_PO(1)
    );
  Ucore_Uusb_Uuc_PO_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N24,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_4_FFX_RST,
      O => Ucore_Uusb_Uuc_PO(4)
    );
  Ucore_Uusb_Uuc_PO_4_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_4_FFX_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N6,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_7_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(7)
    );
  Ucore_Uusb_Uuc_PO_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C24_N40,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_7_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(7)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N35,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_3_FFX_RST,
      O => Ucore_Uusb_Uuc_BUFO8(3)
    );
  Ucore_Uusb_Uuc_BUFO8_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_BUS1153_9_FROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_9_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(9)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_9_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_9_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N27,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_3_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(2)
    );
  Ucore_Uusb_Uuc_BUFO8_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_urcv_reg : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N137,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_NET599_FFX_SET
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N51,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_5_FFX_RST,
      O => Ucore_Uusb_Uuc_BUFO8(5)
    );
  Ucore_Uusb_Uuc_BUFO8_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N43,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_5_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(4)
    );
  Ucore_Uusb_Uuc_BUFO8_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N67,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_7_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(7)
    );
  Ucore_Uusb_Uuc_BUFO8_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP33_DSEL_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_Q
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_3_FFX_RST
    );
  Ucore_Uusb_Uglue_in_trac_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uglue_in_trac_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uglue_in_trac_FFX_RST,
      O => Ucore_Uusb_Uglue_in_trac
    );
  Ucore_Uusb_Uglue_in_trac_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uglue_in_trac_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uglue_in_trac_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_usb_reset_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_NET2015_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_NET2015_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_NET2015
    );
  Ucore_Uusb_Uusb_Usie_NET2015_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_NET2015_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_NET2015_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1784,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DWR_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1913,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DWR_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1394,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Urst_C68_N24,
      CE => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_CEMUXNOT,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt(4)
    );
  Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Urst_cnt_4_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N6,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFY_SET
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DSEL_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DSEL_2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_1_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N11,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_2_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_rxvalid1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N16,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_4_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N26,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N5,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(0)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N31,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N10,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(1)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_N163,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N24,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N34,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N29,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N95,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N35,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_11_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(11)
    );
  Ucore_Uusb_Uuc_BUFO8_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_11_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C8_N12,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C9_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Ssync_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N102,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N35,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_13_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(12)
    );
  Ucore_Uusb_Uuc_BUFO8_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_13_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N109,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N35,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_13_FFX_RST,
      O => Ucore_Uusb_Uuc_BUFO8(13)
    );
  Ucore_Uusb_Uuc_BUFO8_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_13_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C26_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_1_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(0)
    );
  Ucore_Uusb_Uuc_DPTRO_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N116,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N35,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_15_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(14)
    );
  Ucore_Uusb_Uuc_BUFO8_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_15_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C24_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_1_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(1)
    );
  Ucore_Uusb_Uuc_DPTRO_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N123,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N35,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_15_FFX_RST,
      O => Ucore_Uusb_Uuc_BUFO8(15)
    );
  Ucore_Uusb_Uuc_BUFO8_15_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_15_FFX_RST
    );
  Ucore_Ufunc_s_cur_oldCol_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_503_i,
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_GROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_3_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FROM,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21,
      CLK => clk48,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N15,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(2)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N20,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(3)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DSEL_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1567,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N30,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(5)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N40,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C14_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_7_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(6)
    );
  Ucore_Uusb_Uuc_DPTRO_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C12_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_7_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(7)
    );
  Ucore_Uusb_Uuc_DPTRO_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_7_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N62,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N5,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(0)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C4_N10,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C5_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr(1)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_dev_addr_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C8_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_9_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(9)
    );
  Ucore_Uusb_Uuc_DPTRO_9_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_9_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N80,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_setup_trac_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C29_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C30_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_NET1039_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_NET1039
    );
  Ucore_Uusb_Uusb_Usie_NET1039_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_NET1039_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_NET1039_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N25,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFY_RST
    );
  Ucore_Uusb_Uglue_bytecount_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uglue_C1075_N11,
      CE => Ucore_Uusb_Uglue_C27_N9,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uglue_bytecount_1_FFX_RST,
      O => Ucore_Uusb_Uglue_bytecount(1)
    );
  Ucore_Uusb_Uglue_bytecount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uglue_bytecount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uglue_bytecount_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FFX_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_uc_wrctrl2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N30,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C18_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_5_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(4)
    );
  Ucore_Uusb_Uuc_DPTRO_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C16_N6,
      CE => Ucore_Uusb_N1483,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_5_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(5)
    );
  Ucore_Uusb_Uuc_DPTRO_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C28_N35,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_7_FFY_RST
    );
  Ucore_Ufunc_sram_OELeftn : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_nextoen,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => ram_oe_c_FFY_RST,
      O => ram_oe_c
    );
  ram_oe_c_FFY_RSTOR : X_OR2
    port map (
      I0 => ram_oe_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => ram_oe_c_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N47,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C12_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N27,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C18_N15,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Seop_2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N21,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C12_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_2_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N3,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_1_FFY_RST,
      O => Ucore_Uusb_Uusb_rxd(0)
    );
  Ucore_Uusb_Uusb_rxd_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd2_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C20_N9,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_rxd_1_FFX_RST,
      O => Ucore_Uusb_Uusb_rxd(1)
    );
  Ucore_Uusb_Uusb_rxd_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_rxd_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_rxd_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_frxd_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C25_N5,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_NET146_FFY_RST
    );
  Ucore_Ufunc_doneflag_502 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_resize_doWrite37,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_doneflag_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_doneflag
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C38_N68,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C39_N30,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(3)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N12,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N3,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N9,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N19,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N20,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(3)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C18_N39,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C21_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxd1_7_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N25,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(4)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_reg_1_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N11,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_1_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N30,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(5)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C1_N16,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_count_2_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Uepdec_C6_N35,
      CE => Ucore_Uusb_Uusb_Usie_Uepdec_C7_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr(6)
    );
  Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Uepdec_tmp_addr_6_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_toggle_reg : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C36_N6,
      CE => Ucore_Uusb_N1467,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_TG_0_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_TG(0)
    );
  Ucore_Uusb_Uusb_TG_0_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_TG_0_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_TG_0_FFY_SET
    );
  Ucore_Uusb_Uglue_txen1_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uglue_txen1_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uglue_txen1_FFX_RST,
      O => Ucore_Uusb_Uglue_txen1
    );
  Ucore_Uusb_Uglue_txen1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uglue_txen1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uglue_txen1_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N5,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C33_N15,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(0)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C6_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_11_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(10)
    );
  Ucore_Uusb_Uuc_DPTRO_11_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_11_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N10,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C33_N15,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(1)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C4_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_11_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(11)
    );
  Ucore_Uusb_Uuc_DPTRO_11_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_11_FFX_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C2_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_13_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(12)
    );
  Ucore_Uusb_Uuc_DPTRO_13_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_13_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C28_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_15_FFY_RST,
      O => Ucore_Uusb_Uuc_DPTRO(15)
    );
  Ucore_Uusb_Uuc_DPTRO_15_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_15_FFY_RST
    );
  Ucore_Uusb_Uuc_Udptr_DPTR_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Udptr_C0_N6,
      CE => Ucore_Uusb_N1494,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DPTRO_13_FFX_RST,
      O => Ucore_Uusb_Uuc_DPTRO(13)
    );
  Ucore_Uusb_Uuc_DPTRO_13_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_DPTRO_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_DPTRO_13_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_3_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N21,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_4_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_6_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N36,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_5_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N31,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_6_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_8_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N46,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(9)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_7_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N41,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(8)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_8_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_GROM,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_9_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N51,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift(10)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_shift_10_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_N303,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12s_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se02,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP33_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N133,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N15,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp2_sel_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Utmp2_sel_FROM,
      CE => Ucore_Uusb_N1511,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_sel_FFX_RST,
      O => Ucore_Uusb_Uuc_Utmp2_sel
    );
  Ucore_Uusb_Uuc_Utmp2_sel_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Utmp2_sel_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_sel_FFX_RST
    );
  Ucore_Ufunc_sram_SRAMLeftAddr_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_addrreg_4(0),
      CE => Ucore_Ufunc_sram_N_231_i,
      CLK => clk48x2,
      SET => GND,
      RST => a0_c_FFY_RST,
      O => a0_c
    );
  a0_c_FFY_RSTOR : X_OR2
    port map (
      I0 => a0_c_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => a0_c_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C34_N12,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_1_FFY_RST,
      O => Ucore_Uusb_BUS126_0_Q
    );
  Ucore_Uusb_BUS126_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C34_N20,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_1_FFX_RST,
      O => Ucore_Uusb_BUS126_1_Q
    );
  Ucore_Uusb_BUS126_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C34_N28,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_3_FFY_RST,
      O => Ucore_Uusb_BUS126_2_Q
    );
  Ucore_Uusb_BUS126_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS126_6_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_6_FFY_RST,
      O => Ucore_Uusb_BUS126_5_Q
    );
  Ucore_Uusb_BUS126_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N59,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_6_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(6)
    );
  Ucore_Uusb_Uuc_BUFO8_6_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_6_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_reg_15_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_C12_N81,
      CE => Ucore_Uusb_N1524,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc(15)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Ucrc16_crc_15_FFY_SET
    );
  Ucore_Ufunc_sram_writedatareg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(10),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_11_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(10)
    );
  Ucore_Ufunc_sram_writedatareg_11_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_11_FFY_RST
    );
  Ucore_Ufunc_addr_offset_16_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(16),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(16)
    );
  Ucore_Ufunc_sram_writedatareg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(11),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_11_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(11)
    );
  Ucore_Ufunc_sram_writedatareg_11_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_11_FFX_RST
    );
  Ucore_Ufunc_addr_offset_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(5),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(5)
    );
  Ucore_Ufunc_addr_offset_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(6),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_6_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(6)
    );
  Ucore_Ufunc_addr_offset_17_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(17),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_17_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(17)
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(0),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(0)
    );
  Ucore_Uusb_Uuc_Uport0_pad_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(1),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(1)
    );
  Ucore_Uusb_Uuc_Uport0_pad_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(3),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(3)
    );
  Ucore_Uusb_Uuc_Uport0_pad_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(5),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_5_FFX_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(5)
    );
  Ucore_Uusb_Uuc_Uport0_pad_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C34_N36,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_3_FFX_RST,
      O => Ucore_Uusb_BUS126_3_Q
    );
  Ucore_Uusb_BUS126_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C34_N53,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_6_FFX_RST,
      O => Ucore_Uusb_BUS126_6_Q
    );
  Ucore_Uusb_BUS126_6_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_6_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_uc_status_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS126_7_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_BUS126_7_FFX_RST,
      O => Ucore_Uusb_BUS126_7_Q
    );
  Ucore_Uusb_BUS126_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_BUS126_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_BUS126_7_FFX_RST
    );
  Ucore_Ufunc_s_cur_oldCol_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(10),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(10)
    );
  Ucore_Ufunc_s_cur_oldCol_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(11),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(11)
    );
  Ucore_Ufunc_s_cur_oldCol_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(12),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(12)
    );
  Ucore_Ufunc_s_cur_oldCol_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(13),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(13)
    );
  Ucore_Ufunc_s_cur_oldCol_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(14),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(14)
    );
  Ucore_Ufunc_s_cur_oldCol_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldCol_5(15),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldCol_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldCol(15)
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_cspii_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N103,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_CSP_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_CSP(2)
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_CSP_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2345,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFX_RST
    );
  Ucore_Ufunc_c_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(9),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(9)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2302,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_cspii_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N77,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_CSP_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_CSP(3)
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_CSP_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1308,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_1_FFX_RST
    );
  Ucore_Ufunc_c_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(0),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C2_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFX_RST
    );
  Ucore_Ufunc_c_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(1),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(1)
    );
  Ucore_Ufunc_c_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(2),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(2)
    );
  Ucore_Ufunc_c_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(3),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(3)
    );
  Ucore_Ufunc_c_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(4),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(4)
    );
  Ucore_Ufunc_c_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(5),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(5)
    );
  Ucore_Ufunc_c_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(6),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(6)
    );
  Ucore_Ufunc_c_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(8),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(8)
    );
  Ucore_Ufunc_c_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_c_5(7),
      CE => Ucore_Ufunc_N_253_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_c_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_c(7)
    );
  Ucore_Ufunc_sram_writedatareg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(6),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_7_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(6)
    );
  Ucore_Ufunc_sram_writedatareg_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_7_FFY_RST
    );
  Ucore_Ufunc_sram_writedatareg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(5),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_5_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(5)
    );
  Ucore_Ufunc_sram_writedatareg_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N19,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C13_N18,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_1_FFX_RST
    );
  Ucore_Ufunc_sram_writedatareg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(7),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_7_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(7)
    );
  Ucore_Ufunc_sram_writedatareg_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_7_FFX_RST
    );
  Ucore_Ufunc_sram_writedatareg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(8),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_9_FFY_RST,
      O => Ucore_Ufunc_sram_writedatareg(8)
    );
  Ucore_Ufunc_sram_writedatareg_9_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_9_FFY_RST
    );
  Ucore_Ufunc_sram_writedatareg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_sram_writeData(9),
      CE => Ucore_Ufunc_sram_doWrite,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_writedatareg_9_FFX_RST,
      O => Ucore_Ufunc_sram_writedatareg(9)
    );
  Ucore_Ufunc_sram_writedatareg_9_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_writedatareg_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_writedatareg_9_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(1),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_N169,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_C2_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(6),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_6_FFX_RST,
      O => Ucore_Uusb_BUS1610_6_Q
    );
  Ucore_Uusb_BUS1610_6_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_6_FFX_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(7),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_8_FFY_RST,
      O => Ucore_Uusb_BUS1610_7_Q
    );
  Ucore_Uusb_BUS1610_8_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_8_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(8),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_8_FFX_RST,
      O => Ucore_Uusb_BUS1610_8_Q
    );
  Ucore_Uusb_BUS1610_8_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_8_FFX_RST
    );
  Ucore_Ufunc_imageloaded_503 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_imageloaded_BYMUXNOT,
      CE => Ucore_Ufunc_N_246_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_imageloaded_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_imageloaded
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(9),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_12_FFY_RST,
      O => Ucore_Uusb_BUS1610_9_Q
    );
  Ucore_Uusb_BUS1610_12_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_12_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(12),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_12_FFX_RST,
      O => Ucore_Uusb_BUS1610_12_Q
    );
  Ucore_Uusb_BUS1610_12_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_12_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_pidreg_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFY_RST
    );
  Ucore_Ufunc_addr_offset_18_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(18),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_18_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(18)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_pidreg_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N10,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_pidreg_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N20,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C31_N12,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_BUS222_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_valid_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_pad_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS1614(7),
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uport0_pad_7_FFX_RST,
      O => Ucore_Uusb_Uuc_Uport0_pad(7)
    );
  Ucore_Uusb_Uuc_Uport0_pad_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uport0_pad_7_FFX_RST
    );
  Ucore_Ufunc_s_prev_cur_oldRow_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(10),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(10)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(11),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(11)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(12),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(12)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(13),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(13)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(14),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(14)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(15),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(15)
    );
  Ucore_Ufunc_ram_writeData_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(10),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(10)
    );
  Ucore_Ufunc_ram_writeData_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(12),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(12)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_out_en_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C2_N5,
      CE => Ucore_Uusb_N1468,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_out_en
    );
  Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_setup_en_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C5_N5,
      CE => Ucore_Uusb_N1468,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFX_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_setup_en
    );
  Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_setup_en_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_OP_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_OP_2_FFX_RST
    );
  Ucore_Ufunc_s_cur_oldRow_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(10),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(10)
    );
  Ucore_Ufunc_s_cur_oldRow_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(12),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(12)
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_3_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS10881(3)
    );
  Ucore_Uusb_Uuc_BUS10881_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_5_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS10881(4)
    );
  Ucore_Uusb_Uuc_BUS10881_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_5_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS10881(5)
    );
  Ucore_Uusb_Uuc_BUS10881_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_BYMUXNOT,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_div_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_7_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS10881(6)
    );
  Ucore_Uusb_Uuc_BUS10881_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_7_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS10881(7)
    );
  Ucore_Uusb_Uuc_BUS10881_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_7_FFX_RST
    );
  Ucore_Ufunc_s_prev_cur_oldRow_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(6),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(6)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(8),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(8)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(7),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(7)
    );
  Ucore_Ufunc_s_prev_cur_oldRow_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow(9),
      CE => Ucore_Ufunc_resize_doWrite35,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_prev_cur_oldRow_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_prev_cur_oldRow(9)
    );
  Ucore_Ufunc_ram_writeData_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(0),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(0)
    );
  Ucore_Ufunc_ram_writeData_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(1),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se03,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N748,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DWR_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N877,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(3)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_3_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N5,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP33_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N90,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DWR_1_FFY_RST
    );
  Ucore_Ufunc_s_cur_oldRow_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(11),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(11)
    );
  Ucore_Ufunc_s_cur_oldRow_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(14),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(14)
    );
  Ucore_Ufunc_s_cur_oldRow_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(13),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(13)
    );
  Ucore_Ufunc_s_cur_oldRow_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_s_cur_oldRow_5(15),
      CE => Ucore_Ufunc_N_7_i_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_s_cur_oldRow_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_s_cur_oldRow(15)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_BC_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2818,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_0_FFY_RST
    );
  Ucore_Ufunc_addr_offset_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(11),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(11)
    );
  Ucore_Ufunc_addr_offset_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(14),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(14)
    );
  Ucore_Ufunc_addr_offset_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(12),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_12_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(12)
    );
  Ucore_Ufunc_addr_offset_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(4),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(4)
    );
  Ucore_Ufunc_addr_offset_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(13),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_14_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(13)
    );
  Ucore_Ufunc_addr_offset_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(3),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_4_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(3)
    );
  Ucore_Ufunc_addr_offset_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_addr_offset_5(15),
      CE => Ucore_Ufunc_un41_nextaddr_offset_i_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_addr_offset_16_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_addr_offset(15)
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_1_FFY_RST,
      O => Ucore_Uusb_Uuc_OP2(0)
    );
  Ucore_Uusb_Uuc_OP2_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_1_FFX_RST,
      O => Ucore_Uusb_Uuc_OP2(1)
    );
  Ucore_Uusb_Uuc_OP2_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_3_FFY_RST,
      O => Ucore_Uusb_Uuc_OP2(2)
    );
  Ucore_Uusb_Uuc_OP2_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_3_FFX_RST,
      O => Ucore_Uusb_Uuc_OP2(3)
    );
  Ucore_Uusb_Uuc_OP2_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_5_FFX_RST,
      O => Ucore_Uusb_Uuc_OP2(5)
    );
  Ucore_Uusb_Uuc_OP2_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op2ii_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C1_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP2_7_FFX_RST,
      O => Ucore_Uusb_Uuc_OP2(7)
    );
  Ucore_Uusb_Uuc_OP2_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP2_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DSEL_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_LOGIC_ONE,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DSEL_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_1_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS10881(0)
    );
  Ucore_Uusb_Uuc_BUS10881_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_3_FFY_RST,
      O => Ucore_Uusb_Uuc_BUS10881(2)
    );
  Ucore_Uusb_Uuc_BUS10881_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp1_TMP1_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_T1WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUS10881_1_FFX_RST,
      O => Ucore_Uusb_Uuc_BUS10881(1)
    );
  Ucore_Uusb_Uuc_BUS10881_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUS10881_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(1)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(2)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(3)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_3_FFX_RST
    );
  Ucore_Ufunc_high_temp2_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(8),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(8)
    );
  Ucore_Ufunc_high_temp2_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(10),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(10)
    );
  Ucore_Ufunc_high_temp2_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(9),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(9)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFY_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(4)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFX_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(5)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_5_FFX_RST
    );
  Ucore_Ufunc_high_temp2_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(11),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(11)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFY_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(6)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFX_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(7)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_7_FFX_RST
    );
  Ucore_Ufunc_high_temp2_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(12),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(12)
    );
  Ucore_Ufunc_high_temp2_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(13),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(13)
    );
  Ucore_Ufunc_high_temp2_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(14),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(14)
    );
  Ucore_Ufunc_imageloaded_fast_504 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_imageloaded_fast_BYMUXNOT,
      CE => Ucore_Ufunc_N_246_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_imageloaded_fast_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_imageloaded_fast
    );
  Ucore_Ufunc_state_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_30_i,
      CE => Ucore_Ufunc_un1_rst_7_i,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_state_2_FFY_RST,
      O => Ucore_Ufunc_state(2)
    );
  Ucore_Ufunc_state_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_state_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N10,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C29_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_adepfrm_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_1_FFY_RST,
      O => Ucore_Uusb_Uuc_BO(0)
    );
  Ucore_Uusb_Uuc_BO_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_1_FFX_RST,
      O => Ucore_Uusb_Uuc_BO(1)
    );
  Ucore_Uusb_Uuc_BO_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_3_FFY_RST,
      O => Ucore_Uusb_Uuc_BO(2)
    );
  Ucore_Uusb_Uuc_BO_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_3_FFX_RST,
      O => Ucore_Uusb_Uuc_BO(3)
    );
  Ucore_Uusb_Uuc_BO_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_5_FFY_RST,
      O => Ucore_Uusb_Uuc_BO(4)
    );
  Ucore_Uusb_Uuc_BO_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_5_FFX_RST,
      O => Ucore_Uusb_Uuc_BO(5)
    );
  Ucore_Uusb_Uuc_BO_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_7_FFY_RST,
      O => Ucore_Uusb_Uuc_BO(6)
    );
  Ucore_Uusb_Uuc_BO_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Ub_reg_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_BWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BO_7_FFX_RST,
      O => Ucore_Uusb_Uuc_BO(7)
    );
  Ucore_Uusb_Uuc_BO_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BO_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_3_FFX_RST,
      O => Ucore_Uusb_BUS131(3)
    );
  Ucore_Uusb_BUS131_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_5_FFY_RST,
      O => Ucore_Uusb_BUS131(4)
    );
  Ucore_Uusb_BUS131_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_5_FFX_RST,
      O => Ucore_Uusb_BUS131(5)
    );
  Ucore_Uusb_BUS131_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_7_FFY_RST,
      O => Ucore_Uusb_BUS131(6)
    );
  Ucore_Uusb_BUS131_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_7_FFX_RST,
      O => Ucore_Uusb_BUS131(7)
    );
  Ucore_Uusb_BUS131_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_7_FFX_RST
    );
  Ucore_Ufunc_imageloaded_rep1_505 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_imageloaded_rep1_BYMUXNOT,
      CE => Ucore_Ufunc_N_246_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_imageloaded_rep1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_imageloaded_rep1
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(2),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS141_2_FFY_RST,
      O => Ucore_Uusb_BUS141(2)
    );
  Ucore_Uusb_BUS141_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS141_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(0),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS141_1_FFY_RST,
      O => Ucore_Uusb_BUS141(0)
    );
  Ucore_Uusb_BUS141_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS141_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(1),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS141_1_FFX_RST,
      O => Ucore_Uusb_BUS141(1)
    );
  Ucore_Uusb_BUS141_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS141_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(2),
      CE => Ucore_Uusb_N1514,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_txstrobe_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(5),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_6_FFY_RST,
      O => Ucore_Uusb_BUS1610_5_Q
    );
  Ucore_Uusb_BUS1610_6_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(4),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_4_FFX_RST,
      O => Ucore_Uusb_BUS1610_4_Q
    );
  Ucore_Uusb_BUS1610_4_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_4_FFX_RST
    );
  Ucore_Ufunc_ram_writeData_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(11),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(11)
    );
  Ucore_Ufunc_ram_writeData_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(13),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_13_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(13)
    );
  Ucore_Ufunc_ram_writeData_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(14),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(14)
    );
  Ucore_Ufunc_ram_writeData_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(15),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(15)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop3,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop4,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_eop5_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C25_N12,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFX_RST
    );
  Ucore_Ufunc_resize_write_data_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d1_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_1_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(1)
    );
  Ucore_Ufunc_resize_write_data_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_1_FFX_RST
    );
  Ucore_Ufunc_low_temp2_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(0),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(0)
    );
  Ucore_Ufunc_low_temp2_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(1),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(1)
    );
  Ucore_Ufunc_resize_write_data_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d2_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_3_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(2)
    );
  Ucore_Ufunc_resize_write_data_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_3_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d3_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_3_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(3)
    );
  Ucore_Ufunc_resize_write_data_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_3_FFX_RST
    );
  Ucore_Ufunc_low_temp2_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(2)
    );
  Ucore_Ufunc_low_temp2_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(3),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(3)
    );
  Ucore_Ufunc_resize_write_data_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d4_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_5_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(4)
    );
  Ucore_Ufunc_resize_write_data_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_5_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d5_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_5_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(5)
    );
  Ucore_Ufunc_resize_write_data_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_5_FFX_RST
    );
  Ucore_Ufunc_low_temp2_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(4),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(4)
    );
  Ucore_Ufunc_low_temp2_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(5),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(5)
    );
  Ucore_Ufunc_resize_write_data_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d6_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_7_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(6)
    );
  Ucore_Ufunc_resize_write_data_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_7_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d7_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_7_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(7)
    );
  Ucore_Ufunc_resize_write_data_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_7_FFX_RST
    );
  Ucore_Ufunc_low_temp2_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(6),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(6)
    );
  Ucore_Ufunc_low_temp2_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(7),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(7)
    );
  Ucore_Ufunc_resize_write_data_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d8_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_9_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(8)
    );
  Ucore_Ufunc_resize_write_data_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_9_FFY_RST
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_T2WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2(0)
    );
  Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Utmp2_TMP2_1_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d9_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_9_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(9)
    );
  Ucore_Ufunc_resize_write_data_9_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_9_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se04,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_se05_FFX_RST
    );
  Ucore_Ufunc_ram_writeData_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(2),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(2)
    );
  Ucore_Ufunc_ram_writeData_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(3),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(3)
    );
  Ucore_Ufunc_ram_writeData_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(4),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(4)
    );
  Ucore_Ufunc_ram_writeData_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(5),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(5)
    );
  Ucore_Ufunc_ram_writeData_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(6),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(6)
    );
  Ucore_Ufunc_ram_writeData_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(7),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(7)
    );
  Ucore_Ufunc_ram_writeData_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(8),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(8)
    );
  Ucore_Ufunc_ram_writeData_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp2(9),
      CE => Ucore_Ufunc_un1_next_write_data37_5_n,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeData_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeData(9)
    );
  Ucore_Ufunc_ram_writeAddr_18_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_ram_writeAddr_s(18),
      CE => Ucore_Ufunc_N_217_i,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_ram_writeAddr_18_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_ram_writeAddr(18)
    );
  Ucore_Ufunc_din_11_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d11_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_11_SRMUX_OUTPUTNOT,
      O => Ucore_din(11)
    );
  Ucore_Uusb_Uglue_doutii_reg_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(7),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_dout_15_FFY_RST,
      O => Ucore_dout_15_Q
    );
  Ucore_dout_15_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_dout_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_dout_15_FFY_RST
    );
  Ucore_Ufunc_din_12_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d12_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_13_SRMUX_OUTPUTNOT,
      O => Ucore_din(12)
    );
  Ucore_Ufunc_din_13_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d13_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_13_SRMUX_OUTPUTNOT,
      O => Ucore_din(13)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_out_trac_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C27_N5,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C30_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_NET1035_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_NET1035
    );
  Ucore_Uusb_Uusb_Usie_NET1035_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_NET1035_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_NET1035_FFY_RST
    );
  Ucore_Ufunc_din_14_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d14_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_15_SRMUX_OUTPUTNOT,
      O => Ucore_din(14)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_CLASS_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2732,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_1_FFY_RST
    );
  Ucore_Ufunc_din_15_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d15_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_15_SRMUX_OUTPUTNOT,
      O => Ucore_din(15)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DSEL_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2085,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_CLASS_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2775,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_CLASS_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_DWR_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_Q(4)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_DWR_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP33_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N179,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_Q
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP33_DSEL_0_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d10_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_11_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(10)
    );
  Ucore_Ufunc_resize_write_data_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_11_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d12_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_13_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(12)
    );
  Ucore_Ufunc_resize_write_data_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_13_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d11_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_11_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(11)
    );
  Ucore_Ufunc_resize_write_data_11_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_11_FFX_RST
    );
  Ucore_Ufunc_resize_write_data_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d13_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_13_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(13)
    );
  Ucore_Ufunc_resize_write_data_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_13_FFX_RST
    );
  Ucore_Ufunc_resize_write_data_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d14_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_15_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(14)
    );
  Ucore_Ufunc_resize_write_data_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_15_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d0_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_1_FFY_RST,
      O => Ucore_Ufunc_resize_write_data(0)
    );
  Ucore_Ufunc_resize_write_data_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_1_FFY_RST
    );
  Ucore_Ufunc_resize_write_data_15_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => d15_in,
      CE => Ucore_Ufunc_un1_rst_2_0_a2_n,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_resize_write_data_15_FFX_RST,
      O => Ucore_Ufunc_resize_write_data(15)
    );
  Ucore_Ufunc_resize_write_data_15_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_resize_write_data_15_FFX_RST
    );
  Ucore_Ufunc_resize_state_fast_0_Q_506 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_395_i,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_fast_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state_fast_0_Q
    );
  Ucore_Ufunc_resize_state_fast_2_Q_507 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_nextresize_state(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_resize_state_fast_2_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_resize_state_fast_2_Q
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_BYMUXNOT,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C25_N12,
      CLK => clk48,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Smux_1_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C4_N27,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_C5_N16,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Utracrt_Strac_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP32_DWR_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N356,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP32_DWR_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(13),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_14_FFY_RST,
      O => Ucore_Uusb_BUS1610_13_Q
    );
  Ucore_Uusb_BUS1610_14_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_14_FFY_RST
    );
  Ucore_Uusb_Uuc_Upadx_adx_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_ABUS(14),
      CE => Ucore_Uusb_Uuc_ADXWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS1610_14_FFX_RST,
      O => Ucore_Uusb_BUS1610_14_Q
    );
  Ucore_Uusb_BUS1610_14_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS1610_14_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_iniii_reg : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_INI_LOGIC_ZERO,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_N89,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uuc_Uctrl_INI_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uuc_Uctrl_INI
    );
  Ucore_Uusb_Uuc_Uctrl_INI_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uuc_Uctrl_INI_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uuc_Uctrl_INI_FFY_SET
    );
  Ucore_Uusb_Uglue_doutii_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(2),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_3_FFY_RST,
      O => sr(2)
    );
  sr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => sr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_3_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_12_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(4),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_5_FFY_RST,
      O => sr(4)
    );
  sr_5_FFY_RSTOR : X_OR2
    port map (
      I0 => sr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_5_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_11_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(3),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_3_FFX_RST,
      O => sr(3)
    );
  sr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => sr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_3_FFX_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_14_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(6),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_6_FFY_RST,
      O => sr(6)
    );
  sr_6_FFY_RSTOR : X_OR2
    port map (
      I0 => sr_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_6_FFY_RST
    );
  Ucore_Ufunc_din_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d10_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_11_SRMUX_OUTPUTNOT,
      O => Ucore_din(10)
    );
  Ucore_Uusb_Uglue_doutii_reg_13_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(5),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_5_FFX_RST,
      O => sr(5)
    );
  sr_5_FFX_RSTOR : X_OR2
    port map (
      I0 => sr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_5_FFX_RST
    );
  Ucore_Ufunc_high_temp2_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(15),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp2_15_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp2(15)
    );
  Ucore_Ufunc_temp1_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(0),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(0)
    );
  Ucore_Ufunc_state_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_N_29_i,
      CE => Ucore_Ufunc_un1_rst_7_i,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_state_1_FFY_RST,
      O => Ucore_Ufunc_state(1)
    );
  Ucore_Ufunc_state_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Ufunc_state_1_FFY_RST
    );
  Ucore_Uusb_Uclk_div_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_CLK24I_BYMUXNOT,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_CLK24I_FFY_RST,
      O => Ucore_Uusb_CLK24I
    );
  Ucore_Uusb_CLK24I_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_CLK24I_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_CLK24I_FFY_RST
    );
  Ucore_Ufunc_temp1_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(1),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(1)
    );
  Ucore_Ufunc_temp1_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(2)
    );
  Ucore_Ufunc_temp1_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(3),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(3)
    );
  Ucore_Ufunc_temp1_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(0),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(8)
    );
  Ucore_Ufunc_temp1_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(4),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(4)
    );
  Ucore_Ufunc_temp1_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(5),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(5)
    );
  Ucore_Ufunc_temp1_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sl(6),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(6)
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_1_FFY_RST,
      O => Ucore_Uusb_BUS131(0)
    );
  Ucore_Uusb_BUS131_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_1_FFY_RST
    );
  Ucore_Ufunc_temp1_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_dout_7_Q,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(7)
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_1_FFX_RST,
      O => Ucore_Uusb_BUS131(1)
    );
  Ucore_Uusb_BUS131_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uport0_reg_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_P0WR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_BUS131_3_FFY_RST,
      O => Ucore_Uusb_BUS131(2)
    );
  Ucore_Uusb_BUS131_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_BUS131_3_FFY_RST
    );
  Ucore_Ufunc_temp1_9_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(1),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_9_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(9)
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_BC_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2861,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_BC_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_aluop_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N41,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_ALUOP_1_FFY_RST,
      O => Ucore_Uusb_Uuc_ALUOP(1)
    );
  Ucore_Uusb_Uuc_ALUOP_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_ALUOP_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DSEL_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2042,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DSEL_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_OP_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_OP_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_aluop_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N74,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_ALUOP_3_FFY_RST,
      O => Ucore_Uusb_Uuc_ALUOP(3)
    );
  Ucore_Uusb_Uuc_ALUOP_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_ALUOP_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_dsel_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N68,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DSEL_2_FFY_RST,
      O => Ucore_Uusb_Uuc_DSEL(2)
    );
  Ucore_Uusb_Uuc_DSEL_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_DSEL_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DSEL_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_Q(0)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DSEL_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_dsel_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N29,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DSEL_0_FFY_RST,
      O => Ucore_Uusb_Uuc_DSEL(0)
    );
  Ucore_Uusb_Uuc_DSEL_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_DSEL_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_cspii_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N51,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_CSP_4_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_CSP(4)
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_CSP_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_dsel_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N48,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DSEL_1_FFY_RST,
      O => Ucore_Uusb_Uuc_DSEL(1)
    );
  Ucore_Uusb_Uuc_DSEL_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_DSEL_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP22_DWR_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_Q(1)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP22_DWR_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_dsel_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C20_N88,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_DSEL_3_FFY_RST,
      O => Ucore_Uusb_Uuc_DSEL(3)
    );
  Ucore_Uusb_Uuc_DSEL_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_DSEL_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Upsw_PSW_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Upsw_C0_N12,
      CE => Ucore_Uusb_N1495,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_PO_6_FFY_RST,
      O => Ucore_Uusb_Uuc_PO(6)
    );
  Ucore_Uusb_Uuc_PO_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_PO_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_PO_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DWR_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N2388,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_aluop_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N58,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_ALUOP_2_FFY_RST,
      O => Ucore_Uusb_Uuc_ALUOP(2)
    );
  Ucore_Uusb_Uuc_ALUOP_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_ALUOP_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C38_N25,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C39_N30,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(0)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_0_FFY_SET
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP31_OP_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_Q(2)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP31_OP_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP23_DWR_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Uuop_C0_N1480,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_Q(4)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP23_DWR_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Udctrl_aluop_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Udctrl_C18_N90,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_ALUOP_4_FFY_RST,
      O => Ucore_Uusb_Uuc_ALUOP(4)
    );
  Ucore_Uusb_Uuc_ALUOP_4_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_ALUOP_4_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C38_N56,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C39_N30,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(2)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_2_FFY_SET
    );
  Ucore_Uusb_Uuc_Uctrl_Uuop_mcode_reg_UOP21_DWR_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_GROM,
      CE => VCC,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_Q(4)
    );
  Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_MCODE_UOP21_DWR_4_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_clk12o_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C23_N12,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_CLK12I_FFY_RST,
      O => Ucore_Uusb_CLK12I
    );
  Ucore_Uusb_CLK12I_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_CLK12I_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_CLK12I_FFY_RST
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_3_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_SPO_3_FFY_RST,
      O => Ucore_Uusb_Uuc_SPO(3)
    );
  Ucore_Uusb_Uuc_SPO_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_SPO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_SPO_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N24,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_3_FFY_RST
    );
  Ucore_Ufunc_high_temp2_fast_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(10),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(2)
    );
  Ucore_Ufunc_high_temp2_fast_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(11),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N15,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C20_N48,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_C21_N21,
      CLK => clk48,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_Sdpll_2_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS1411(7),
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C1434_N20,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C33_N15,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt(3)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_adx_cnt_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_buf_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Ubuf_C1_N11,
      CE => Ucore_Uusb_Uuc_Ubuf_C2_N12,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_BUFO8_0_FFY_RST,
      O => Ucore_Uusb_Uuc_BUFO8(0)
    );
  Ucore_Uusb_Uuc_BUFO8_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_BUFO8_0_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_C4_N9,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzit_cnt_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C0_N54,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Ssynct_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_0_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uuc_SPO_0_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uuc_SPO(0)
    );
  Ucore_Uusb_Uuc_SPO_0_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uuc_SPO_0_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uuc_SPO_0_FFY_SET
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_reg_1_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Uep0ctrl_C38_N40,
      CE => Ucore_Uusb_Uusb_Uep0ctrl_C39_N30,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo(1)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Uep0ctrl_Sfifo_1_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C12_N27,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C13_N18,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_Spakt_2_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_C14_N20,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_N60,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakt_PID_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_4_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_SPO_4_FFY_RST,
      O => Ucore_Uusb_Uuc_SPO(4)
    );
  Ucore_Uusb_Uuc_SPO_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_SPO_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_SPO_4_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N42,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_6_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(7),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(6)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_N1553,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_7_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C16_N22,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Sfrmt_0_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N18,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_utxd_reg : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C10_N9,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => vpo_p13_c_FFY_SET,
      RST => GND,
      O => vpo_p13_c
    );
  vpo_p13_c_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => vpo_p13_c_SRMUX_OUTPUTNOT,
      O => vpo_p13_c_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N12,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_1_FFY_RST
    );
  Ucore_Ufunc_high_temp2_fast_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(14),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(6)
    );
  Ucore_Ufunc_high_temp2_fast_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(15),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(7)
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_5_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_SPO_5_FFY_RST,
      O => Ucore_Uusb_Uuc_SPO(5)
    );
  Ucore_Uusb_Uuc_SPO_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_SPO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_SPO_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N36,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_5_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C11_N34,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_C12_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_Sdec_1_FFY_RST
    );
  Ucore_Ufunc_high_temp2_fast_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(13),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(5)
    );
  Ucore_Ufunc_high_temp2_fast_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(12),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_high_temp2_fast_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_high_temp2_fast(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N50,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C17_N11,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_2_FFY_RST
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_1_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_1_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uuc_SPO_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uuc_SPO(1)
    );
  Ucore_Uusb_Uuc_SPO_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uuc_SPO_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uuc_SPO_1_FFY_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N30,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_4_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(2)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_reg_1_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N36,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C17_N11,
      CLK => Ucore_Uusb_CLK12,
      SET => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_1_FFY_SET
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(3)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(4)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(6)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(5)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(7)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_1_FFY_RST,
      O => Ucore_Uusb_Uuc_OP3(0)
    );
  Ucore_Uusb_Uuc_OP3_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_3_FFY_RST,
      O => Ucore_Uusb_Uuc_OP3(2)
    );
  Ucore_Uusb_Uuc_OP3_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_shift_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C2_N6,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_NET1109_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(0)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op1ii_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C0_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFX_RST,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211(1)
    );
  Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_BUS15211_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_C153_N10,
      CE => Ucore_Uusb_N1541,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspt_count_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_1_FFX_RST,
      O => Ucore_Uusb_Uuc_OP3(1)
    );
  Ucore_Uusb_Uuc_OP3_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_3_FFX_RST,
      O => Ucore_Uusb_Uuc_OP3(3)
    );
  Ucore_Uusb_Uuc_OP3_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_5_FFY_RST,
      O => Ucore_Uusb_Uuc_OP3(4)
    );
  Ucore_Uusb_Uuc_OP3_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_5_FFX_RST,
      O => Ucore_Uusb_Uuc_OP3(5)
    );
  Ucore_Uusb_Uuc_OP3_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_7_FFY_RST,
      O => Ucore_Uusb_Uuc_OP3(6)
    );
  Ucore_Uusb_Uuc_OP3_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ufetch_op3ii_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_Uctrl_Ufetch_C2_N3,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_OP3_7_FFX_RST,
      O => Ucore_Uusb_Uuc_OP3(7)
    );
  Ucore_Uusb_Uuc_OP3_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_OP3_7_FFX_RST
    );
  Ucore_Uusb_Uglue_usb_datain1_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_DI_1_BYMUXNOT,
      CE => Ucore_Uusb_Uglue_C29_N9,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_DI_1_FFY_RST,
      O => Ucore_Uusb_DI(1)
    );
  Ucore_Uusb_DI_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_DI_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_DI_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxadep_reg_10_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C30_N15,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C25_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_BUS1153_10_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_BUS1153(10)
    );
  Ucore_Uusb_Uusb_Usie_BUS1153_10_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_BUS1153_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_BUS1153_10_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_C22_N11,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFY_RST
    );
  Ucore_Ufunc_low_temp2_fast_0_Q_508 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(0),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast_0_Q
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_6_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_SPO_6_FFY_RST,
      O => Ucore_Uusb_Uuc_SPO(6)
    );
  Ucore_Uusb_Uuc_SPO_6_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_SPO_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_SPO_6_FFY_RST
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_2_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_2_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uuc_SPO_2_FFY_SET,
      RST => GND,
      O => Ucore_Uusb_Uuc_SPO(2)
    );
  Ucore_Uusb_Uuc_SPO_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uuc_SPO_2_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uuc_SPO_2_FFY_SET
    );
  Ucore_Uusb_Uuc_Usp_SP_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_SPO_7_GROM,
      CE => Ucore_Uusb_Uuc_SPWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_SPO_7_FFY_RST,
      O => Ucore_Uusb_Uuc_SPO(7)
    );
  Ucore_Uusb_Uuc_SPO_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_SPO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_SPO_7_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C16_N22,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C17_N11,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak_0_FFY_RST
    );
  Ucore_Ufunc_sram_presstate_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_presstate_3_Q,
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => Ucore_Ufunc_sram_presstate_2_FFY_RST,
      O => Ucore_Ufunc_sram_presstate(2)
    );
  Ucore_Ufunc_sram_presstate_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Ufunc_sram_presstate_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Ufunc_sram_presstate_2_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_frxen_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmr_Srfrm(0),
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(0),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_1_FFY_RST,
      O => sl(0)
    );
  sl_1_FFY_RSTOR : X_OR2
    port map (
      I0 => sl_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_1_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(1),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_1_FFX_RST,
      O => sl(1)
    );
  sl_1_FFX_RSTOR : X_OR2
    port map (
      I0 => sl_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_1_FFX_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(2),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_3_FFY_RST,
      O => sl(2)
    );
  sl_3_FFY_RSTOR : X_OR2
    port map (
      I0 => sl_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_3_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(3),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_3_FFX_RST,
      O => sl(3)
    );
  sl_3_FFX_RSTOR : X_OR2
    port map (
      I0 => sl_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_3_FFX_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(4),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_5_FFY_RST,
      O => sl(4)
    );
  sl_5_FFY_RSTOR : X_OR2
    port map (
      I0 => sl_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_5_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(5),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_5_FFX_RST,
      O => sl(5)
    );
  sl_5_FFX_RSTOR : X_OR2
    port map (
      I0 => sl_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_5_FFX_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(6),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sl_6_FFY_RST,
      O => sl(6)
    );
  sl_6_FFY_RSTOR : X_OR2
    port map (
      I0 => sl_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sl_6_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(7),
      CE => Ucore_Uusb_Uglue_C0_N64,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_dout_7_FFY_RST,
      O => Ucore_dout_7_Q
    );
  Ucore_dout_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_dout_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_dout_7_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_8_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(0),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_1_FFY_RST,
      O => sr(0)
    );
  sr_1_FFY_RSTOR : X_OR2
    port map (
      I0 => sr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_NET519,
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Unrzir_frxen2_FFY_RST
    );
  Ucore_Uusb_Uglue_doutii_reg_9_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(1),
      CE => Ucore_Uusb_Uglue_C0_N39,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => sr_1_FFX_RST,
      O => sr(1)
    );
  sr_1_FFX_RSTOR : X_OR2
    port map (
      I0 => sr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => sr_1_FFX_RST
    );
  Ucore_Ufunc_din_0_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d0_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_1_SRMUX_OUTPUTNOT,
      O => Ucore_din(0)
    );
  Ucore_Ufunc_din_1_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d1_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_1_SRMUX_OUTPUTNOT,
      O => Ucore_din(1)
    );
  Ucore_Ufunc_din_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d2_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_3_SRMUX_OUTPUTNOT,
      O => Ucore_din(2)
    );
  Ucore_Ufunc_din_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d3_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_3_SRMUX_OUTPUTNOT,
      O => Ucore_din(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_1_FFX_RST
    );
  Ucore_Ufunc_din_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d4_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_5_SRMUX_OUTPUTNOT,
      O => Ucore_din(4)
    );
  Ucore_Ufunc_din_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d5_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_5_SRMUX_OUTPUTNOT,
      O => Ucore_din(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(3),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(2)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(4),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(3)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_3_FFX_RST
    );
  Ucore_Ufunc_din_6_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d6_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_7_SRMUX_OUTPUTNOT,
      O => Ucore_din(6)
    );
  Ucore_Ufunc_din_7_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d7_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_7_SRMUX_OUTPUTNOT,
      O => Ucore_din(7)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(5),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(4)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFY_RST
    );
  Ucore_Ufunc_temp1_10_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => sr(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_temp1_11_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_temp1(10)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_shift_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(6),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Uspr_C4_N6,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511(5)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_BUS511_5_FFX_RST
    );
  Ucore_Ufunc_din_8_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => d8_in,
      CE => Ucore_Ufunc_dwire6,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_din_9_SRMUX_OUTPUTNOT,
      O => Ucore_din(8)
    );
  Ucore_Ufunc_low_temp2_fast_1_Q_509 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(1),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_1_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast_1_Q
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(1),
      CE => VCC,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Ufrmt_Seopt_0_FFX_RST
    );
  Ucore_Ufunc_low_temp2_fast_2_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(2),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast(2)
    );
  Ucore_Ufunc_low_temp2_fast_3_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(3),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_3_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast(3)
    );
  Ucore_Ufunc_low_temp2_fast_4_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(4),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast(4)
    );
  Ucore_Ufunc_low_temp2_fast_5_Q : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(5),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_5_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast(5)
    );
  Ucore_Ufunc_low_temp2_fast_6_Q_510 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(6),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast_6_Q
    );
  Ucore_Ufunc_low_temp2_fast_7_Q_511 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Ufunc_temp1(7),
      CE => VCC,
      CLK => clk48x2,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => Ucore_Ufunc_low_temp2_fast_7_SRMUX_OUTPUTNOT,
      O => Ucore_Ufunc_low_temp2_fast_7_Q
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_cspii_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_Ucsp_C1_N129,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Uctrl_CSP_0_FFY_RST,
      O => Ucore_Uusb_Uuc_Uctrl_CSP(1)
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_Uctrl_CSP_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_0_FFY_RST
    );
  Ucore_Uusb_Uuc_Uctrl_Ucsp_cspii_reg_0_Q : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Ucore_Uusb_Uuc_Uctrl_CSP_0_BXMUXNOT,
      CE => Ucore_Uusb_Uuc_Uctrl_Ucsp_C2_N16,
      CLK => Ucore_Uusb_CLK24,
      SET => Ucore_Uusb_Uuc_Uctrl_CSP_0_FFX_SET,
      RST => GND,
      O => Ucore_Uusb_Uuc_Uctrl_CSP(0)
    );
  Ucore_Uusb_Uuc_Uctrl_CSP_0_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => Ucore_Uusb_Uuc_Uctrl_CSP_0_SRMUX_OUTPUTNOT,
      O => Ucore_Uusb_Uuc_Uctrl_CSP_0_FFX_SET
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C22_N9,
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C23_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden(1)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_Srpak(0),
      CE => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_C23_N9,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFX_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden(0)
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Upakr_rxden_0_FFX_RST
    );
  Ucore_Uusb_Uuc_Uradx_radx_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_RAWR,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_RAM_REG_7_FFY_RST,
      O => Ucore_Uusb_Uuc_RAM_REG(7)
    );
  Ucore_Uusb_Uuc_RAM_REG_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_RAM_REG_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_5_FFY_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(4)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_5_FFX_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(5)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_7_FFY_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(6)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Ubuf_rel_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_Uuc_Ubuf_C0_N5,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_Ubuf_rel_7_FFX_RST,
      O => Ucore_Uusb_Uuc_Ubuf_rel(7)
    );
  Ucore_Uusb_Uuc_Ubuf_rel_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => Ucore_Uusb_Uuc_Ubuf_rel_7_FFX_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(0),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_1_FFY_RST,
      O => Ucore_Uusb_Uuc_AO(0)
    );
  Ucore_Uusb_Uuc_AO_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_1_FFY_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(2),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_3_FFY_RST,
      O => Ucore_Uusb_Uuc_AO(2)
    );
  Ucore_Uusb_Uuc_AO_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_3_FFY_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(1),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_1_FFX_RST,
      O => Ucore_Uusb_Uuc_AO(1)
    );
  Ucore_Uusb_Uuc_AO_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_1_FFX_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(3),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_3_FFX_RST,
      O => Ucore_Uusb_Uuc_AO(3)
    );
  Ucore_Uusb_Uuc_AO_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_3_FFX_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_4_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(4),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_5_FFY_RST,
      O => Ucore_Uusb_Uuc_AO(4)
    );
  Ucore_Uusb_Uuc_AO_5_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_5_FFY_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_5_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(5),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_5_FFX_RST,
      O => Ucore_Uusb_Uuc_AO(5)
    );
  Ucore_Uusb_Uuc_AO_5_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_5_FFX_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_6_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(6),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_7_FFY_RST,
      O => Ucore_Uusb_Uuc_AO(6)
    );
  Ucore_Uusb_Uuc_AO_7_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_7_FFY_RST
    );
  Ucore_Uusb_Uuc_Uacc_ACC_reg_7_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_Uuc_DBUS(7),
      CE => Ucore_Uusb_N1471,
      CLK => Ucore_Uusb_CLK24,
      SET => GND,
      RST => Ucore_Uusb_Uuc_AO_7_FFX_RST,
      O => Ucore_Uusb_Uuc_AO(7)
    );
  Ucore_Uusb_Uuc_AO_7_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uuc_AO_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uuc_AO_7_FFX_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => vp_p10_c,
      CE => VCC,
      CLK => clk48,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_a_FFY_RST
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_reg : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => vp_p10_c,
      CE => VCC,
      CLK => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_CKMUXNOT,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_FFY_RST,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b
    );
  Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Usie_Utrac_Upak_Usp_Unrzi_Ufrm_Udpll_b_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_reg_2_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(2),
      CE => Ucore_Uusb_Uusb_Uep0ctrl_N484,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n(2)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_n_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_reg_0_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(0),
      CE => Ucore_Uusb_Uusb_Uep0ctrl_N484,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFY_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n(0)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_n_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFY_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_reg_1_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(1),
      CE => Ucore_Uusb_Uusb_Uep0ctrl_N484,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFX_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n(1)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_n_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_1_FFX_RST
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_reg_3_Q : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Ucore_Uusb_BUS131(3),
      CE => Ucore_Uusb_Uusb_Uep0ctrl_N484,
      CLK => Ucore_Uusb_CLK12,
      SET => GND,
      RST => Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFX_RST,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n(3)
    );
  Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Ucore_Uusb_Uusb_Uep0ctrl_n_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Ucore_Uusb_Uusb_Uep0ctrl_n_3_FFX_RST
    );
  clk_p89_BUF : X_CKBUF
    port map (
      I => clk_p89,
      O => Udll_CLKIN_w
    );
  Ucore_Uusb_U1_BUF : X_CKBUF
    port map (
      I => Ucore_Uusb_CLK24I,
      O => Ucore_Uusb_CLK24
    );
  Ucore_Uusb_U2_BUF : X_CKBUF
    port map (
      I => Ucore_Uusb_CLK12I,
      O => Ucore_Uusb_CLK12
    );
  Udll_clk2xg_BUF : X_CKBUF
    port map (
      I => Udll_CLK2X_dll,
      O => clk48x2
    );
  Udll_clkg_BUF : X_CKBUF
    port map (
      I => Udll_CLK0_dll,
      O => clk48
    );
  PWR_VCC_0_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_VCC_0_FROM
    );
  PWR_VCC_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_VCC_0_GROM
    );
  PWR_VCC_0_XUSED : X_BUF
    port map (
      I => PWR_VCC_0_FROM,
      O => GLOBAL_LOGIC1
    );
  PWR_VCC_0_YUSED : X_BUF
    port map (
      I => PWR_VCC_0_GROM,
      O => GLOBAL_LOGIC0_5
    );
  PWR_VCC_1_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_VCC_1_FROM
    );
  PWR_VCC_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_VCC_1_GROM
    );
  PWR_VCC_1_XUSED : X_BUF
    port map (
      I => PWR_VCC_1_FROM,
      O => GLOBAL_LOGIC1_0
    );
  PWR_VCC_1_YUSED : X_BUF
    port map (
      I => PWR_VCC_1_GROM,
      O => GLOBAL_LOGIC0_6
    );
  PWR_GND_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_GROM
    );
  PWR_GND_0_YUSED : X_BUF
    port map (
      I => PWR_GND_0_GROM,
      O => GLOBAL_LOGIC0
    );
  PWR_GND_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_1_GROM
    );
  PWR_GND_1_YUSED : X_BUF
    port map (
      I => PWR_GND_1_GROM,
      O => GLOBAL_LOGIC0_0
    );
  PWR_GND_2_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_2_GROM
    );
  PWR_GND_2_YUSED : X_BUF
    port map (
      I => PWR_GND_2_GROM,
      O => GLOBAL_LOGIC0_1
    );
  PWR_GND_3_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_3_GROM
    );
  PWR_GND_3_YUSED : X_BUF
    port map (
      I => PWR_GND_3_GROM,
      O => GLOBAL_LOGIC0_2
    );
  PWR_GND_4_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_4_GROM
    );
  PWR_GND_4_YUSED : X_BUF
    port map (
      I => PWR_GND_4_GROM,
      O => GLOBAL_LOGIC0_3
    );
  PWR_GND_5_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_5_GROM
    );
  PWR_GND_5_YUSED : X_BUF
    port map (
      I => PWR_GND_5_GROM,
      O => GLOBAL_LOGIC0_4
    );
  NlwBlock_xsvPads_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_xsvPads_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end STRUCTURE;

