The goal of this lab is to introduce you to the XSV300 platform, which has a 300,000 gate Virtex FPGA along with memory, RAMDAC, video and audio codecs, serial and parallel interfaces, Ethernet PHYDEV, USB and PS/2 ports. In this lab you will:
1. Learn about the DW8051 core.
2. Learn how to simulate and synthesize the 8051 for the Virtex FPGA using programs generated by the Keil tools.
3. Download and test 8051 software + hardware systems in the XSV300.
In Lab 3, you will complete a software/hardware system using the 8051 and modules that interface to an ultrasonic sensor or accelerometer and an stereo audio codec.
Make a copy of the example project, \\ifilesrv1\courses\cse477\Spring 2003\example8051, which contains the 8051 along with a ROM for a version of the first program from Lab1. This project also has what you need to synthesize to the Xilinx FPGA. In particular, the FPGA pin connections are specified using a .UCF file, which is also used to specify other constraints like timing constraints. The default .UCF file, which you will find in the project root directory, has an entry for all the devices on the XSV board, but most are commented out. You’ll note that many FPGA pins are shared by multiple devices. For example, the RAMDAC shares pins with the right memory, so they cannot be used at the same time. You’ll also want to make sure that you disable devices that aren’t being used so they don’t interfere with the devices that are being used. The example project will show you how to do this. You should spend some time looking at the manual for the XSV boards. For the moment, you will not be using very much of the board, but you should take a look at where to go for information, in particular for pinouts.
PLEASE NOTE: These XSV boards are no longer being
produced. Of the 7 boards that we have,
several are already partially or completely busted. Please be careful – if we blow out any more boards we’ll be stuck
without a way to do interesting video and audio projects.
FOLLOW THIS PROCEDURE for
connecting any wires to the board, including test equipment:
The board is programmed via the parallel interface using XSLOAD and the .bit file produced by the Xilinx tools. This is done using a Xilinx PLD on the board, which is programmed via a .svf file. XESS has a default PLD program called dwnloadpar.svf, but we use a different one, called UWdownloadpar.svf which allows all the lights and switches to be used, as well as the serial port. If you use the XESS PLD program, these will not work! You can tell which is loaded when you power up the board – the UW version causes the lights to rotate. (You can find this .svf file in the “BIT and SVF files” folder.
There is also a programmable clock generator on the board that allows the 100MHz clock to be divided down. We have set the clock to 50MHz, which is divided down to 4 using a DLL. The example project includes this DLL. Please don’t change this clock – the 8051 requires the slow clock, but the 50MHz clock can be used to make higher performance hardware components as long as you take some care with the interface to the 8051.
The DW8051 comes in the form of an EDIF file, which we can simulate and synthesize. There is also a Verilog file that provides an interface for the synthesis program. Make sure this .v file is not included in the compilation when you simulate. This file is called dw9051_core.v. It can be excluded from simulation by going to Deisgn Flow->options(left of functional simulation).
Compile and simulate the example project and look at the waveforms. You can follow along in the Keil debugger, using the IROM_ADDR to see which instructions are being executed. You will see an initialization part that clears out the data memory. (We have edited the ROM to make this shorter for simulation.) After that, your program will start running, writing values to the P0 port. However, this program has an inner loop to slow it down enough for the lights to be seen when running on the hardware. (The src directory has the Keil project for the program.)
Synthesizing a project is pretty straightforward as long as you follow this procedure:
Include the DW8051_core.v file in the compilation of the project. Synplicity will ignore the DW8051 EDIF file, and requires a Verilog interface file instead. Switching between simulation and synthesis requires that you alternately hide and include this file. The easiest way to do this is to Add the file when simulating, and Detach the file (don’t Delete it!) when synthesizing. You’ll have to make sure it’s removed from the library. You can select which files will be synthesised in synthesis options (make sure you exclude any test fixtures).
Top-Level Unit: ser8051 (Whatever is your top-level
for synthesis)
Make sure the right files have been
included. (Leave out test fixture, for example)
Family: Xilinx51 VIRTEX
Device: V300pq240
Simulation Output: None (Verilog if you want post-synthesis simulation)
Run Mode: Batch
General Tab:
Netlist File: Generally filled in by synthesis
Family/Device: Filled in by synthesis
Run Mode: Batch
Translate Tab:
Unclick “Use default UCF file” and Browse to the ser8051.ucf in the project root
directory
Timing&Configure:
Click “Run bitgen.exe selected command file” and browse to the
bitgen.bat in the project root directory
The Keil compiler produces output files in the form of an Intel .hex format file. This file can be used by programmers to program ROMs and PROMs if you want to use real 8051 processors. (For example, the XS40 boards have 8051 processors with 20K PROMs along with a 4010 FPGA.) We will instead produce a Verilog file for a ROM, which will be synthesized to 4 block RAMs in the Virtex FPGA.
Compile your first program from Lab1 to a ROM.
1. Check the option to produce a .hex file. You can also get the compiler to run the rom.exe program for you automatically by entering the command “rom <name>.hex”. (Project->Options for Target->Output [Tab], check Run User Program #1) Otherwise, you can run it by hand. This produces a file called ROM2kx8_<name>.v If you want to create a new Keil project, you can find Rom.exe in \\ifilesrv1\courses\cse477\Spring 2003\example8051\src
2. Make sure you are running the full version of uVision – the eval version will insist on using a large code space.
3. Take a look at the generated ROM Verilog program. The first instruction is a jump to the initialization start address. Go to this address: this will be a MOV instruction with the value 7F – change this to F for simulation to avoid spending a lot of time simulating unnecessary code.
4. Recompile your project and simulate. Since this program is running faster, you should see the P0 port values being written.
You will now implement the program you wrote in Lab 1. This will mean adding a circuit that connects switches to the P1 port (address 90). This should assert the switch values on the SFR_DATA_IN bus when SFR_READ is asserted and SFR_ADDR is 90. Otherwise it should tri-state bus.
When you synthesize/implement this project you will have to change the UCF file to connect the appropriate switches to your input ports.
Demonstrate your program running on the XSV board – don’t forget to get signed off!