Video
Monitoring with Motion Detection
Preliminary Design Document
Jeremy
Coriell
Ha Kim Le
Jeff
Phillips
INTRODUCTION
Our project consists of a highly integrated video motion detection device. Its purpose is to detect human motion in a given space through a small modular video camera imaging system. This device will record scenes form the incoming video imagery and perform detailed edge detection analysis on that data to detect motion in the scene. This device could be used for security or home monitoring purposes, and thus has a very straightforward application in the real world. Because of its small size, and level of portability, it could easily be adapted to a variety of uses and situations.
Functional Overview
This project consists of three major components: a Spectronix black and white video camera, an FPGA-based control/analysis device, and a VGA monitor for video output. The camera is controlled by a small, onboard microprocessor and takes in 160 by 120 pixel resolution black and white images at a rate of 30 frames per second.
This video data is then fed into the control unit, where it is stored into two separate memory areas: one for analysis and one for video output. This process is controlled by a main memory control unit that performs double buffering for screen display purposes, and communicates with a separate analysis unit for storing images to be analyzed.
This analysis unit controls how and when images will be stored for analysis by the memory management module. It also performs the algorithmic edge detection and image comparison processing that makes up the device’s motion detection capability. This unit can then alert the rest of the system when motion is detected, at which time the system will respond accordingly for its specific use. In security applications, for example, this might consist of setting off an alarm. Likewise, in a common monitoring application, the system may notify parents that a baby is stirring in its room.
System Layout
The basic layout of this design has been kept simple in an effort to achieve the highest level of modularity for the system. Though this system is specialized, we are hoping to keep it packaged tightly enough to allow for many types of applications to take advantage of this particular unit. This desire for simplicity is shown in the block diagram for the overall system in figure 1 below.
Figure 1:
Overall System Block Diagram
REQUIREMENTS
This system requires that many technical and functional requirements be met to ensure proper functionality. These requirements are listed and discussed in detail in the following sections.
Functional Unit Interfaces
The following tables describe the interfaces that occur in the system. The signal names refer to the specific signals as found in the schematic diagrams for each unit.
Table 1: Spectronix RC-1 Unit to Camera Controller Unit Interface
Signal |
Description |
|
QCK |
Image data clock, used to clock data from DATA[7:0]. |
|
DATA[7:0] |
8-bit image and control data bus. The data is valid on the falling edge of the QCK signal. |
|
FST |
Frame start signal. When it goes high, it indicates start of frame capture data. |
|
SDA |
I2C data line used for two-wise serial control. |
|
SCL |
I2C clock line used for two wire serial control. |
Table 2: Camera Controller Unit to Memory Manager Unit Interface
Signal |
Description |
|
DATA_CLK |
Pixel sample clock signal has a negative edge whenever a new pixel value is being asserted on the DATA_OUT bus. |
|
DATA_OUT[7:0] |
8-bit pixel data bus. The data is valid on the falling edge of the DATA_CLK. |
|
FRAME_START |
Frame clock signal has a positive edge sometime between the video frames sent out to the Memory Control. |
Table 3: Analysis Unit to Memory Manager Unit Interface
Signal |
Description |
|
CLK |
System clock. Used for latching data and outputs on the falling edge. |
|
RD |
Read signal to control reading of analysis memory |
|
WR |
Write signal to control writing to analysis memory. |
|
BSY |
Busy signal from memory management unit, to control read and write access to memory, and prevent concurrent read/write activity. |
|
DATA[7:0] |
8-bit pixel data bus for analysis. The data is valid on the falling edge of CLK. |
|
ADDR[14:0] |
Address bus to control addressing of analysis memory. |
|
BANK |
Selects which memory bank to read or write in analysis memory. |
|
DATA_FILL |
Signal to control when analysis memory is filed with an image. A positive edge starts data transfer, and a negative edge ends data transfer. This signal is held low during data analysis. |
|
FRAME_START |
Signal from memory management unit to ensure that data transfers are synchronized with beginning of a new frame. Also used to count number of frames that have passed, for determining frame-pull rate of the analysis unit. |
|
MOTION |
Output signal that indicates when motion has occurred. Signal raised to indicate motion, and is held until next data transfer begins. |
Table 4: Memory Manger Unit to Analysis Unit Interface
Signal |
Description |
|
BANK[2:0] |
Memory bank select. The Analysis Unit qualifies each memory operation as affecting one of eight memory banks. Each bank is structured as 19.2 K x 8 bits. |
|
ADDR[15:0] |
The address of the requested data. Valid values are 0 to 19199, inclusive. |
|
D[8:0] |
The value at the specified address. |
|
RD |
The read signal. Indicates that the address is ready and that the Memory Manager Unit should lookup the value at the location specified by the bank and address values. |
|
WR |
The write signal. Indicates that the address and data busses are ready and that the Memory Manager Unit should store the data at the location specified by the bank and address values. |
|
WR_IMG |
The write image signal. |
Table 5: Memory Manger Unit to VGA Control Unit Interface
Signal |
Description |
|
ADDR[15:0] |
The address of the requested pixel data. Valid values are 0 to 19199, inclusive. |
|
D[8:0] |
The value of the specified pixel. |
|
RD |
The read signal. Indicates that the address is ready and that the Memory Manager Unit should lookup the value of the specified pixel. |
Table 6: VGA Control Unit Interface to RAMDAC Chip and Monitor
Signal |
Description |
|
P[7:0] |
Pixel data bus. |
|
NBLANK |
When low, this signal tells the RAMDAC to generate a blank analog signal. |
|
PIX_CLK |
Pixel clock. Used to clock pixel data to the RAMDAC. |
|
N_RD |
Used to control communication with the RAMDAC when initializing. |
|
N_WR |
Not used in system. Always maintained high. |
|
RS[2:0] |
Register select bus. Used for communicating with the RAMDAC, |
|
D[7:0] |
Data bus. Used when initializing the RAMDAC lookup table. |
|
V_SYNC |
Vertical synchronization for the VGA monitor. |
|
H_SYNC |
Horizontal synchronization for the VGA monitor. |
Overall System Requirements
The video monitoring and motion detection system should be able to take snapshot images with the camera and display these images on the monitor. It should perform image analysis to detect motion in the scene that the camera is monitoring. The overall system also requires its internal units to work with the electrical specifications shown below in table 7.
Table 7: Electrical Specifications for the RC-1 and XSV-300
Component |
Parameter |
Value |
Comments |
RC-1
|
Current Consumption |
50 ma |
Maximum |
Operating Voltage |
9-12 VDC |
Good noise de-coupling required | |
|
Absolute Maximum Supply Voltage |
15 VDC |
| |
|
Maximum cable length |
3 ft |
Maximum length may require static protection | |
|
XSV-300 |
Supply Voltage |
9 VDC |
|
|
Absolute Minimum Supply Current |
1.5 A |
|
VGA Control Unit Requirements
The VGA Control Unit has specific requirements associated with each of its three functional responsibilities.
RAMDAC Initialization
The VGA Control Unit must properly initialize the RAMDAC chip when the system is reset. There are no quantitative requirements associated with this function. The only requirement for this function is that the proper communication protocol is used to communicate with the RAMDAC chip. This protocol is specified in the documentation for the RAMDAC chip (see the References section).
VGA Synchronization Signal Generation
The VGA Control Unit must properly generate horizontal and vertical synchronization signals for the attached VGA monitor. The specific timing requirements for these signals are described in the VGA specification reference (see the References section).
Pixel Data Management
The VGA Control Unit must obtain pixel information from the Memory Manager Unit and pass this information to the RAMDAC. This sequence of events must happen in the timeframe specified by the VGA specification.
Camera Control Unit Requirements
The camera control unit is used to initialize the camera. The RC-1 camera module has many configurable parameters, but we are interested in a small subset only. The required camera configuration is summarized below in table 8. Refer to the VV-5300 chip documentation for details of these settings.
Table 8: RC-1 Camera Settings
Parameter |
Value |
|
Data Format
Select |
8 wire parallel
output |
|
Status Line Data
Output Enable |
|
|
ADC Select |
8 bit |
|
FST/QCK pin
mode |
Normal FST / QCKs
pin |
|
QCK Mode Select |
Memory Manager Unit Requirements
The Memory Manager Unit must monitor the continuous stream of data from the Camera Control Unit and store that data in the proper location. It must also provide the correct data to the VGA Control Unit and the Analysis unit upon request. These two situations can be considered separately.
Incoming Data
The Memory Manager Unit must be able to monitor the incoming data stream from the Camera Control Unit and store it appropriately. Once the Memory Manager Unit begins the storage of an image to a particular destination, it must successfully complete the operation. No data can be lost or modified in the process. Also, the unit will be automatically switching video buffers to achieve the desired double-buffering effect for data being displayed on the monitor. The transition from one destination buffer to the other must only happen between image frames.
The Memory Manager Unit must also handle incoming data from the Analysis Unit. The Analysis unit can request a data storage operation at any time. The Memory Manager Unit must ensure that concurrent read and write operations are handled properly.
Outgoing Data
The Memory Manager Unit must be able to provide pixel data to the VGA Control Unit and the Analysis Unit. Data requested by the VGA Control Unit must always come from the on-screen video buffer. The Memory Manager Unit maintains the logical distinction between which video buffer is the “on-screen” buffer and which is the “off-screen” buffer.
Analysis Unit Requirements
The Analysis Unit performs the main work on the incoming data stream. It must communicate with the memory control unit in order to perform analysis on the data stream on a frame-wise basis. There is a fine balance between the speed at which the unit must run to ensure efficient motion detection for fast motions, and the speed at which the unit can pull frames from the data stream to ensure detection of slow movements. The requirements that must be met by the unit for communication and data analysis are further discussed below.
Communications
The analysis unit must request for the memory management unit to send two frames of image data to the two banks of analysis memory. Because this data will be pulled into the analysis memory one pixel at a time, requests must be synchronized with a new frame start in the memory manager unit to ensure that full frames of data are captured. The rate at which frames are pulled from the incoming data stream must also be controlled, because the frame rate of the camera is too fast to capture slower movements. Once sufficient data has been pulled into the buffer for analysis (two full images), the unit must be able to analyze the data, and allow the memory management unit to continue operating as normal.
Image Analysis
Once the unit has gathered enough data into the analysis memory, it must switch over to analysis mode where it will perform the following tasks. First, the unit will run a discrete edge detection algorithm over each image. Once this edge detection algorithm has been run, the unit must compare placement of edges in the modified images to detect whether objects have moved. This entire analysis must be performed in a short enough time frame to ensure that the incoming data stream is sampled and analyzed at an adequate rate for efficient motion detection to occur. The analysis of the images will require a great deal of communication with the memory management unit, and thus will occur in parallel with the double buffering video memory management side of the memory manager.
DESIGN
The system is implemented with the Xilinx FPGA on the XSV-300 board. The FPGA receives and controls the frame images in pixels from the RC-1, stores and loads the pixels in RAM, outputs video frames to the VGA display, and performs the data analysis. The project is broken down into functional components, each of which can be developed independently of the others. The four different functional modules are:
- VGA Control Unit
- Camera Control Unit
- Memory Manager Unit
- Analysis Unit
The specific details for each design unit are as follows:
VGA Control Unit Design
The VGA Control Unit is responsible for displaying image data on the monitor. It does this by directly controlling the vertical and horizontal synchronization signals to the monitor. The analog color signals for each pixel are generated by using the 8-bit pixel data to look up a corresponding 24-bit color value from a lookup table. The RAMDAC chip on the XSV-300 board implements this lookup table. Because of their close relationship, the VGA Control Unit is also responsible for initially configuring the RAMDAC chip. The block diagram for the VGA Control Unit is show below in figure 2.
Figure 2: VGA Control Unit Block Diagram
RAMDAC Initialization
When the Reset button (SW4) on the XSV-300 board is pressed, the VGA Control Unit initializes the RAMDAC. This initialization process will set the values in the RAMDAC lookup table to allow the output of 253 grayscale colors. The RAMDAC lookup table has room for 256 entries, but we reserve the first three entries in order to represent colors other than grayscale values (RED, GREEN and BLUE). For grayscale image data that would match the first three entries, the fourth entry is used instead. This rounding up of pixel values is performed only on image data being displayed.
Synchronization Signal Generation
The VGA Control Unit uses two signal-generation blocks to produce the horizontal and vertical synchronization signals for the VGA monitor. Each block is made of two counters that work together properly generate the required synchronization signals required by the monitor.
Pixel Data Display
To display the pixel data, the VGA Control Unit asks the Memory Manager Unit for the appropriate pixel. The pixels are addressed linearly. So, for an image of 160 by 120 pixels, the pixel addresses will range from zero to 19199. When the VGA Control Unit needs a pixel, it places the address on the Address Bus and raises the RD line. The Memory Manager Unit will fetch the value at that address and make it available on the Data bus. The VGA Control Unit will then read the data and apply it to the RAMDAC pixel bus. It will then cycle the RAMDAC pixel clock to output this color mapping to the monitor.
Camera Control Unit Design
The Camera Control Unit communicates with the camera via the SCL and SDA serial lines to configure the camera. These two signals implement a bi-directional, 2-wire communications interface that allows the video camera to be configured and its operating status monitored. During normal camera operation, it provides a continuous stream of pixel information as well as frame start and pixel clock signals. The Camera Control Unit obtains the pixel data from the camera and sends it to the Memory Manager Unit. The block diagram for the Camera Control Unit is shown below in figure 3.
Figure
3: Camera
Control Unit
Configuration Set Up
By using the SDA and SCL signals, the Camera Control Unit sets up and configures the RC-1 so that the frame image is 160x120 pixel and the frame rate is 30 frames/sec.
Pixel Data Transfer
The Camera Control Unit does no processing on the data stream from the camera. It simple passes the data and the control signals to the Memory Manager Unit, which is responsible for reading and storing the image information.
Memory Manager Unit Design
The Memory Manager Unit performs the following tasks:
- Collects image data from the camera and buffers it in video memory, analysis memory or both.
- Provides the Analysis Unit with image data upon request.
- Provides the VGA Control Unit with image data upon request.
- Implements double-buffering for the VGA Control Unit.
The block diagram for the Memory Manager Unit is show below in figure 4.
Figure 4: Memory Manager Unit Block Diagram
Video Memory Management
The Memory Manager Unit continuously monitors the data stream and the Frame Start line from the Camera Control Unit. Upon seeing a Frame Start signal, the unit begins writing the image data to the off-screen video memory. Once the image has been buffered, the unit logically swaps the off-screen and on-screen buffers and repeats the process. When the VGA Control Unit requests a particular pixel value, the Memory Manager Unit always ensures that the on-screen data is chosen.
Analysis Memory Management
Occasionally, the Analysis Unit will request the capture of an image. The Memory Manager Unit will see the request signal and will respond with a busy signal. The unit will then wait for the next Frame Start, buffer the following image in the analysis buffer and then lower the busy signal. When the Analysis Unit sees that the busy Signal is clear, it can request individual pixels from the analysis buffer as required.
Analysis Unit Design
The Analysis Unit performs the following tasks:
- Gathers data for two complete video frames by communicating with memory manager.
- Controls the rate at which this data is gathered to ensure sufficient operation.
- Runs a discrete edge detection analysis algorithm over each image to detect the positions of objects in each scene.
- Compares edge placement in the two images to detect if object motion has occurred.
The block diagram for the Analysis Unit is shown below in
Figure 5.
Figure
5:
Analysis Unit Block Diagram.
Data Gathering and Storage
The Analysis Unit continuously monitors the incoming data
stream, watching the stream for the beginning of incoming frames. Upon seeing a
frame start signal, the unit signals the memory management unit to begin filling
the first analysis buffer with the first frame. The unit then waits for 30
frames (about 1 second) to go by, using the frame start signal as a count. Upon
seeing the 31st frame signal, the unit signals
the memory manager to begin filling the second analysis buffer with the second
frame. This is accomplished by properly setting the RD, WR, ADDR[14:0], and BANK
signals on the Analysis Unit, and resetting the counter to 0 each time 30 frames
are seen (READ on FRAMECNT = 0).
Data Rate Control
As stated above, the Analysis will use the frame start
signal to control data capture rate, by counting 30 frames between read
requests. This both ensures that the data will not be sampled too quickly, and
that the Analysis unit will have sufficient time to process each frame inline.
Edge Detection Analysis
After a particular frame has been stored, the Analysis Unit
will immediately begin transforming that frame into an edge image, by using a
discrete threshold edge detection algorithm. This algorithm simply detects
intensity differences between neighboring pixels, and detects an edge where this
intensity difference is greater than or equal to the set threshold. Because this
algorithm simply requires a subtraction of two 8-bit values for each pixel set,
it can be accomplished very quickly on a digital system. The algorithm is run in
both the x and y directions simultaneously, to ensure correct edge detection. In
areas where an edge is detected, the determined edge pixel is set to white, and
in all other areas the pixels are set to black. This greatly simplifies image
comparison and thus adds further speed to the Analysis Unit. This entire
analysis on the frame must be fast enough to occur before the next frame is
gathered; however, the time frame we are looking at (29 frames * 160 pixels *
120 pixels = 556,800 machine cycles) will provide sufficient time for the
analysis.
Motion Detection through Edge Comparison
Once the edge detection algorithm has processed the two
images, motion detection becomes a much easier problem. We now have two binary
images consisting of white edge pixels and black non-edge pixels. Thus, we
simply have to compare the low bit of each pixel position of both memories to
see if the edges have remained in the same place over the change in time. If
every edge pixel and non-edge pixel in the scene is in the same place (i.e.
pixel value is the same for both banks at each location), no motion has
occurred. However, if a single pixel value is different, we know an edge has
moved and thus motion has occurred. This greatly speeds up the motion detection
process, because we can end our analysis on the first instance of differing
pixel values.
PARTS
Table 8 below lists the parts required for this project. All of these parts are available in the hardware lab.
Table 8: Parts
Part |
Comments |
|
Spectronix RC-1 Camera Module |
Module encapsulating a VV-5300 imager chip |
|
Xess XSV-300 Board |
Prototype development board |
|
VGA Monitor |
Standard VGA monitor |
|
Parallel Port Cable |
Used to program Xess XSV-300 board |
|
Xilinx Foundation Software |
Used for design implementation |
ANALYSIS
This section describes the design choices that were made for each portion of the project, and the reasoning behind those choices.
Overall System Analysis
We have chosen the XSV-300 board for our project because it provides a Virtex FPGA with a suitable large number of Control Logic Blocks (300K). This serves all our design purposes. The XSV-300 board also includes the RAMDAC device, which provides a 256-entry, 24-bit color map that is used by the FPGA to output video to a VGA monitor.
Since the XSV 300 board serves all our purposes, all we need to do is program the functional units and put them together. As long as we can setup and configure the RC-1 in order to pass images into the memory and display the image data on the monitor, we would already have a video monitoring system. The other half of the project is to detect the motion, which can be done with our analysis unit. In the following sections, we describe the analysis of each functional unit.
VGA Control Unit Analysis
The VGA Control Unit consists of the following major
phases.
RAMDAC Initialization
The process of programming the RAMDAC is specified in its documentation. Assuming that the chip operates as described, the initialization of the RAMDAC will be successful.
Normal Operation
The VGA Control Unit must properly generate the horizontal and vertical synchronization signals for the monitor. Also, during the correct portion of the horizontal signal, the unit must fetch pixel data and apply it to the RAMDAC to generate the correct analog color value for a particular pixel. These signals are all generated by counters, which are incremented on each clock cycle of the FPGA. So, given a detailed timing specification that we must meet, we only need to choose proper values to count up to. This will be a function of out FPGA clock frequency and is a straightforward calculation.
Camera Control Unit Analysis
The Camera Control Unit simply serves as
a data and control signal conduit between the camera and the rest of the system.
If we configure and set up the RC-1 in the right mode, as specified in the RC-1
documentation (see the References section), the camera should operate as
expected and provide a continuous image data stream.
Memory Manager Unit Analysis
The Memory Manager Unit must direct incoming data from the Camera Control to the appropriate memory block. The data will appear as a steady stream at a fixed rate. The VV-5300 documentation states that the maximum pixel-rate the camera will generate is 1.79 MHz. Our system will be operating at approximately 40MHz, which is about 23 times faster than the incoming data rate. This large difference in speed guarantees that we will be able to process a given byte of data before the next arrives.
Analysis Unit
The Analysis Unit must record two scenes from the incoming data stream and analyze them to see if motion occurred. We will be taking samples from the data stream at a rate of 1 sample/sec, which will provide enough speed to capture human motion as desired and maintain a realistic time frame for analysis to occur. The analysis algorithm provided will ensure that both scene modification and motion detection can occur quickly and efficiently. This combination of a fast algorithm and a large time frame to work in ensure that the Analysis Unit will be able to perform its specified task successfully.
TEST
STRATEGIES
Testing strategies must be developed for any successful digital system. This section discusses the test strategies that will be used to ease the development process for this system.
Overall System Testing
We will test the overall system by splitting it up into two stages. The first stage is to test if the VGA can display the taken data images and the second stage is to test if the analysis can detect any motion from the data images.
First stage
When the camera and the VGA are setup, we will try to download one set of image data taken from the camera, store it in the FPGA memory, and display this image data on the monitor. After the system can display one image, we will allow the camera to keep taking snapshot images and verify that the monitor can display these images as a video monitor. When the first stage works perfectly, we will proceed to the second stage.
Second stage
In the second stage, we will connect the Analysis Unit to the first stage system. The purpose of the second stage is to verify that the analysis algorithm works with the rest of the system. To verify the algorithm’s correctness, we can read the analysis output signal and display it with the LEDs on the XSV-300 board.
VGA Control Unit Testing
The VGA Control Unit is tested in stages during development. Initially, the horizontal and vertical synchronization signals were tested while analog color values were directly generated, bypassing the RAMDAC. This test properly produced a test pattern on the monitor.
The next step in testing is to run the RAMDAC initialization routine and send test data to the RAMDAC. The test data will be chosen so as to access every entry in the RAMDAC lookup table. If the RAMDAC initialization works properly, we should see a test pattern generated by the RAMDAC. The test patterns should correspond to the color distribution that we programmed into the lookup table.
Finally, to test the entire VGA Control Unit, we can construct a test unit that imitates the Memory Management Unit. This test unit will respond exactly as the specified Memory Management Unit, but the resulting data will be a generated test pattern. Again, if this test passes, we expect to see the appropriate test pattern appear on the monitor.
Camera Control Unit Testing
For the Camera Control Unit, first we need to verify that it can output the data with the right frame format. We verify that it can send 19,200 pixels between two asserted frame start signals. Next, we have to wait until the VGA Control Unit and the Memory Control Unit are done and being tested. Similarly, we do the test for the Camera Control Unit like the first stage of the overall system testing.
Memory Manager Unit Testing
Testing of the Memory Management Unit will be performed during its development. The first test will use a test unit that simulates the output of the Camera Control Unit. The Memory Management Unit will be expected to monitor the data and implement the proper double-buffering behavior, as the data is stored in the video buffers. To verify proper operation, we will use the VGA Control Unit to display the data stored in the video buffers. The result should be an alternating pair of test patterns.
Next, we will test integration with the Analysis Module. We will use a test unit that simulates the Analysis Module. This test unit will verify proper operation of the three types of operations associated with the analysis unit: store an image, read a value, write a value. Proper operation of this functionality will be determined by using a special test block that can read the analysis memory block and report its contents via LEDs on the XSV-300 board.
Analysis Unit Testing
Testing of the Analysis Unit will require multiple tests. First, the memory control portion of the analysis unit will be tested by simply performing various reads and writes to addresses in a small memory to ensure proper communication with the memory. This will take care of any timing issues or interface problems that arise with the memory.
Once memory accessing is working properly, the edge detection portion of the machine will be tested by feeding the unit two dummy images, and monitoring the resulting output images from the edge detection process. This will require watching how the addresses in memory are accessed, and what values are being assigned to each position in memory.
Finally, after these two portions are working properly, we will be able to test the motion detection portion of the system. Given that the memory accessing and edge detection algorithm work correctly, this motion detection is a simple addressing and comparison problem that should be easy to test.
DESIGN ISSUES
There are certain elements of our design that we are still investigating. These issues primarily have to do with specific technical details and do not affect the overall system feasibility.
VGA Control Unit Design Issues
The design of the VGA Control Unit faces potential problems in two areas: when to select the proper data to display and how to obtain the data. We will first consider problems related to data timing and then discuss data selection.
Timing
When operating, the VGA Control Unit continuously generates a repeating sequence of horizontal and vertical synchronization signals. This signal pattern repeatedly refreshes the entire 640 by 480 pixel display 60 times each second. However, the images we will be displaying are 160 by 120 pixels, which is one quarter the size of the display area. To properly display an image in its true size, the VGA Control Unit will have to intelligently insert blanking signals for areas of the screen that are not displaying image data. Another possible approach is to dynamically scale the image so that it covers the entire display area.
Data Selection
During normal image display, the VGA Control Unit gets image data from the Memory Manager Unit and presents this information to the RAMDAC for conversion to 24 bit analog color values. However, to allow for additional colors, the lower three RAMDAC table entries are reserved for special color mappings. So, any incoming image data that corresponds to one of these values must be scaled up to the fourth entry. We suspect that the results of this operation will be imperceptible, but there could be a noticeable effect.
We would like to be able to arbitrarily control the location on the screen where the image is displayed. Also, we want to be able to display additional information such as text, borders and indicators. To do this, we will have to have additional control logic in the VGA Control Unit that controls the actual byte stream sent to the RAMDAC for decoding. Most likely, the pixel data manager will be extended to perform this duty.
Camera Control Unit Design Issues
The camera is the source of the image data that we will display on the VGA monitor and analyze in order to detect motion. We will have to properly initialize and use the camera to collect meaningful data. It is necessary to fully understand the capabilities and operation of the video camera we are using. The biggest issue will be the correct initialization of the camera. The VV-5300 chip documentation gives a cursory description of the I2C interface to the camera. This lack of thorough documentation could lead to difficulties initializing the camera.
Memory Manager Unit Design Issues
The Memory Manager Unit will be able to concurrently perform the tasks of data intake and storage, data lookup for the VGA Control Unit and data lookup and storage for the Analysis Unit. The unit will handle performing these tasks in parallel, but care must be taken to prevent any conflicting actions. Specifically, a particular memory bank cannot be written to and read from at the same time. This will not be a problem for the video memory since the Memory Manger Unit will implement a double-buffering scheme that continually maintains the mutually exclusive feature of the video memory. However, since there is only a single analysis memory, there could be a situation where there are concurrent read and write requests. The Memory Manager Unit must be aware of this possibility and handle it accordingly. The most likely solution will be to implement blocking memory access operations that serialize access requests by only allowing one operation to be active at a time.
Analysis Module Unit Design Issues
Two major difficulties arise in the design process for this unit. The first of these obstacles is the memory management portion of the module. Communications with asynchronous rams can be quite difficult if timing restraints are not taken into account. While the brunt of this problem will be placed on the memory management unit, the analysis module will be required to communicate with this module effectively and respect its accessing protocols. Thus, this is one of the areas that will require close attention during the design process.
The other difficult portion of the Analysis Unit design will be ensuring proper functionality of the edge detection algorithm. While this is a very simple procedure to run in software, it may prove more difficult in hardware due to memory addressing issues and timing constraints. This is the most time consuming portion of the analyzer’s job; therefore it must be designed to be as efficient and as precise as possible.
REFERENCES
RoboCam RC-1-BW Module. Spectronix Corporation. 17 April 2001
http://www.spectronix.net/1.htm
VLSI Vision VV5300 Datasheet. STMicroelectronics Corporation. 17 April 2001
http://www.cs.washington.edu/education/courses/477/99sp/docs/vv5300.pdf
XSV-300 Board Manual. Version 1. 24 Sept. 2000. XESS Corporation. 17 April 2001
http://www.xess.com/manuals/xsv-manual-1_0.pdf
Bt481A RAMDA. Nov. 1996. Brooktree Corporation. 17 April 2001
http://www.erc.msstate.edu/~reese/EE4993/data_sheets/btl481a_c.pdf
VGA Timing Information. 19 April 2001
http://www.epanorama.net/documents/pc/vga_timing.html