Brent Mikasa
Daniel Dunham
Curtis Mitchell
The UMI project is close to completion. Much of the design has been implemented and works quite well. As a review team, this fact posed a major challenge, but after checking over the design thoroughly we did find one issue. This document will describe that one problem and give two possible solutions.
Group A requires that a tone be generated within millisecond after unblocking a laser. Using their current design strategy, this is not feasible, because the propagation through the serial lines and the audio codec exceeds 1ms.
Group A is using a slightly modified version of MIDI to communicate between stages II and III. The modification is using a voltage swing instead of a current swing. MIDI requires a serial transport of information at the rate of 1 byte every 320 ms. Since all messages from stage II are 3 bytes long, a transmission takes 960 ms to complete, leaving only 40 ms for other delays.
The audio coded on the XSV 300 board also uses a serial protocol for communication. Using the fastest protocol (resulting in the worst resolution) both the right and the left channels need to be given 16 bit values. This results in a 9 ms transmission time.
The propagation through the audio codec is equal to 14.7 times the sampling period. Group A is using the fastest setting of 20.83 ms (48 kHz.) This results in a propagation delay of 306 ms before the codec generates the tone.
Summing all these delays, we find a total delay of 1.275 ms in the best case. This total ignores any implementation specific delays created by group A, including coding on the Atmel mircocontroller and the logic design on the FPGA.
Since the communication from Stage II to Stage III is already a modified version of MIDI, group A could further modify the communication protocol to allow for a faster transmission rate. By changing from serial to parallel communication, group A can shorten their transmission time to one-eighth their previous.
Taking into account the fact that the XSV 300 board runs much faster than the Atmel mircocontroller’s machine cycle clock, we can transmit a single byte in 3 machine cycles by using a data clock and a rising edge detector on the FPGA. Using an 8-bit bus transmitting at a rate of 3 machine cycles per byte, the total transmission time decreases from 960 ms to 3.4 ms.
This protocol, while being simple to implement on the mircocontroller, also removes the requirement to create a sampling module on the FPGA. Also, this allows for a delay of more than 300 ms in implementation specific modules while still meeting the 1 ms requirement.
The high level requirement of the delay between unblocking a laser and generating a tone is to be imperceptible by the user. A time constraint of 1 ms will meet this requirement, but may be too strict to easily implement. Raising the time constraint by as much 1 ms more will still be imperceptible to the user and allow enough time for propagation and implementation specific delays.