The VGA camera project provides the visual
aspects of our project. A RoboCam RC 2 was used to acquire a black-and-white
image, which is then sent to FPGA 2. FPGA 2 then sends this image,
along with crosshairs at both the touch screen coordinates as well as the
stepper motor coordinates, through a D/A converter. The output of
this D/A converter gets displayed as a black-and-white image on our VGA
monitor.
The core of this module was derived from the VGACAM project given
to us in class. Documentation for this core project can be found
at: www.cs.washington.edu/education/courses/477/00sp/ppt/DesignExamples.
The original design was modified to increase the
image size from 256x256 pixels to 512x480. Logic to draw a pair of
crosshairs was also added.
The original VGACAM project draws a blank pixel when it is outside its 256x256 image region. The first step in drawing a larger image was to change this region so that a blank pixel is drawn outside of the enlarged 512x480 region. This was done by simply watching the Hcnt and Vcnt signals and creating logic that draws a blank pixel when outside the enlarged region.
Next, the way the VGACAM project accesses memory needed to be changed. Since the larger image is simply a 2x magnification of the old image, only one memory read is required for every two pixels along a horizontal row. A simple buffer is used to buffer the pixel, and the low order bit of the Vcnt signal is used to select between the pixel from memory and the pixel that was buffered in the previous cycle.
Finally, logic was added to draw the crosshairs. A module was created that examines the Hcnt, Vcnt, stepper motor coordinates, and touch screen coordinates. At a given Hcnt and Vcnt, the touch screen coordinates and motor coordinates are examined. If Hcnt and Vcnt match up with the touch screen coordinates or the stepper motor coordinates, a “white” signal is asserted. A mux outside of the module checks this white signal and, if the white signal is asserted, displays a white pixel instead of a pixel from memory or our buffer.
As a final note, the above modifications required
more that 100% of the CLBs in our FPGA. One final optimization was
made to fit the modified VGACAM project into FPGA 2. The original
VGACAM project used a 128x8 bit FIFO to buffer the incoming camera image.
This was done because the monitor could be reading from memory for an entire
256 byte-wide row, therefore preventing camera data from being written
into memory. With our modifications, the monitor does a memory read
for every other pixel that is displayed. Since every other cycle
is now free for a memory write, the camera data FIFO was reduced to a 16x8
bit size. The reduction in the FIFO size allowed the entire modified
VGACAM project to fit into FPGA 2.