module BusCon (Strobe,CLK, RST,SHData,Done) ;
input CLK ;
input RST;
input Strobe;
output SHData ; // Shift next nibble into data register
output Done;
reg SHData ;
reg Done;
// FSM states
parameter IDLE = 0, // waiting for first nibble
Data1 = 1, // got first nibble, waiting for second
Data2 = 2, // got second nibble, waiting for third
Data3 = 3, // got third nibble, waiting for fourth
Data4 = 4, // got fourth nibble, waiting for fifth
Data5 = 5, // got fifth nibble, waiting for sixth
Data6 = 6, // got sixth nibble, waiting for seventh
Data7 = 7, // got seventh nibble, waiting for eigth
Data8 = 8; // got eigth nibble; all done
reg [3:0] state;
reg [3:0] nextState;
always @(posedge CLK) begin
if (RST) begin
state <= IDLE;
end else begin
state <= nextState;
end
end
always @(state or Strobe ) begin
// default behavior
Done=0;
nextState = state; // Stay in the same state by
default
SHData = 0;
case (state)
IDLE: // This is the IDLE
state
begin
if(Strobe)
begin
SHData=1;
//the first nibble
nextState=Data1;
end
end
Data8:
begin
nextState=IDLE;
Done = 1;
end
default: // increment next state and shift if we get a
Strobe signal
begin
if(Strobe)begin
SHData=1;
nextState=nextState+1;
end
end
endcase
end
endmodule