Parametized Simple ALU

module alusim(a,b,Carryin,Result,Overflow,Operation);

parameter width =1;

input [width-1:0] a,b;

input Carryin, Operation;

output [width-1:0]Result;

output Overflow;

reg Carryout, Overflow;

reg [width-1:0]Result;

always @(a or b or Carryin or Operation)

if (Operation == 0) Result = a & b;

else if (Operation == 1)

begin

{Carryout,Result}= a + b + Carryin;

Overflow = (~a[width-1]&~b[width-1]&Result[width-1])|(a[width

-1]&b[width-1]&~Result[width-1]);

end

endmodule

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