Testing

verilog alusimple.v testalus.v full1bo.v mux2.v

Compiling source file "alusimple.v"

Compiling source file "testalus.v"

Compiling source file "full1bo.v"

Compiling source file "mux2.v"

Highest level modules:

testalu

Time=0 a = x b = x Carryin = x Result =x Overflow =x Operation = x

Time=1 a = 1 b = 1 Carryin = 1 Result =1 Overflow =0 Operation = 0

Time=2 a = 0 b = 0 Carryin = 1 Result =1 Overflow =1 Operation = 1

Time=3 a = 1 b = 0 Carryin = 1 Result =0 Overflow =0 Operation = 1

L13 "testalus.v": $finish at simulation time 4

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