PPT Slide
calvin% verilog mux4.v testmux4.v
VERILOG-XL 2.5 Sep 28, 1998 18:04:41
Time=0 Select=x in0=x in1=x in2=x in3=x z=x
Time=1 Select=0 in0=0 in1=0 in2=1 in3=1 z=0
Time=2 Select=1 in0=0 in1=1 in2=1 in3=1 z=1
Time=3 Select=2 in0=1 in1=0 in2=0 in3=1 z=0
Time=4 Select=3 in0=1 in1=0 in2=1 in3=1 z=1
L12 "testmux4.v": $finish at simulation time 5
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.4 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.5 Sep 28, 1998 18:04:41