PPT Slide
calvin% verilog mux2.v testmux2.v
VERILOG-XL 2.5 Sep 28, 1998 16:58:53
Compiling source file "mux2.v"
Compiling source file "testmux2.v"
Select=0 in0 = 0 in1 = 1 z = 0
Select=1 in0 = 0 in1 = 1 z = 1
L11 "testmux2.v": $finish at simulation time 3
0 simulation events (use +profile or +listcounts option to count)
CPU time: 1.1 secs to compile + 0.7 secs to link + 0.1 secs in simulation