I/O consistency -- hardware approach
Subset of the shared-bus multiprocessor cache coherence protocol (see Chapter 9 and forthcoming slides)
Cache has duplicate set of tags
Cache controller snoops on the bus
- On input, if there is a match in tags, store in both the cache and main memory
- On output, if there is a match in tags: if WT invalidate the entry; if WB take the cache entry instead of the memory contents and invalidate.