TLB’s

• Cache for PTE’s

• TLB miss handled by hardware or by software (e.g., PAL code in Alpha)

  • TLB miss 10-100 cycles -> no context-switch

• Addressed in parallel with access to the cache

• Since smaller, goes faster

  • It’s on the critical path

• For a given TLB size (number of entries)

  • Larger page size -> larger mapping range

Previous slide

Next slide

Back to first slide

View graphic version