Rambus
Specialized memory controller (scheduler), channel, and DRAM’s
Parallelism and pipelining, e.g.
- independent row , column, and data buses (narrow -- 2 bytes)
- pipelined memory subsystem (several packets/access)
- parallelism within the DRAMs (many banks with 4 possible concurrent operations)
- parallelism among DRAM’s (large number of them)
Great for “streams of data” (Graphics, games)