MSHR’s
Each MSHR must hold:
- a valid (busy) bit
- address of the requested cache block
- index in the cache where the block will go
- comparator (to prevent using the same MSHR for a miss to the same block)
- If data to be forwarded to CPU at the same time as in the cache, needs addresses of registers (one per possible word/byte) and valid bit (for writes)
- Quite a variety of alternatives (Farkas and Jouppi ISCA 94)
- Implemented in MIPS R10000, Alpha 21164, Pentium Pro.