The decode stage (simple case: dual issue and static scheduling)
ID: look for conflicts between the (say) 2 instructions
- Of course need for more than one functional unit
- If one integer unit and one f-p unit, only check for structural hazard, i.e. opcodes since different sets of integer and f-p registers
- Slight difficulty for f-p load/store that use the integer unit (multiple access to f-p register file -- dual port it; and RAW hazard resolved as in single pipelines)
- The load delay (1 cycle) can now delay up to 3 instructions, i.e., 3 issue slots are lost