Impact of superscalar on IF
IF: Need to fetch more than 1 instruction at a time
- Simpler if instructions are of fixed length
- Simpler if restricted not to overlap I-cache lines
Sample of current micros
- Two instruction issue: Alpha 21064, Sparc 2, Pentium, Cyrix
- Three instruction issue: Pentium Pro (but 5 mops from IF/ID to EX; AMD has 4 mops)
- Four instruction issue: Alpha 21164, Power PC 620, Sun UltraSparc, HP PA-8000, MIPS R10000