Integer pipeline (RISC) precise exception
Exceptions can occur in all stages but WB
- IF: memory related (page fault, protection violation, misalignment)
- ID: illegal opcode
- EXE: arithmetic exception (overflow, underflow)
- MEM: memory related
Exceptions must be treated in instruction order
- Instruction I starts at time t
- Exception in MEM stage at time t + 3 (treat it first)
- Instruction I + 1 starts at time t +1
- Exception in IF stage at time t + 1 (occurs earlier but treat in 2nd)