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calvin% verilog test1beh.v ex1beh.v

VERILOG-XL 2.5 Sep 16, 1998 14:54:40

Compiling source file "test1beh.v"

Compiling source file "ex1beh.v"

Highest level modules:

tester

Time=0 in1=0 in2=0 out=0

Time=1 in1=0 in2=1 out=0

Time=2 in1=1 in2=0 out=0

Time=3 in1=1 in2=1 out=1

L11 "test1beh.v": $finish at simulation time 4

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