In this lab you are to build on your lab 1 solution and build a "complete" ARM32 processor. Your processor should support the instructions listed in lab 1. It should not be pipelined, but instead use a multicycle design.
My recommendation is that you take 4 cycles per instruction. In cycle 0 you fetch the instruction, in cycle 2 you read the register file, in cycle 3 you access data memory and do the load or store, and in cycle 4 you write back to the register file. My advice is you do not get tricky. Yes, some instructions can be done in less cycles, but get it working first and then play around with that idea if you feel like it.
For those doing the HW option. You need to demonstrate it working on code that you write. Ideally you would write this code in C, but this may require that you either support pre/post base register updating -- which will require 5 cycles per instruction, or I finish writing my script to remove these instructions from assembly code. I'm working on it...
Do I have to support conditional execution? YES All of the condition codes must be supported.
Do I have to support the shifter? YES on constants and registers when the instruction takes two read operands. No when the instruction takes three operands.
How do I do signed arithmetic in Verilog? I recommend you do it as unsigned and manually take care of the complement and addition of one as needed.
How do I implement the CPSR register? Not in the register file.
Do I need to support writes to r15 (the PC)? YES and be careful with the semantics.
Do I need to support reads of r15 (the PC)? YES and be careful with the semantics.
What is this PC + 8 and PC + 12 thing? Read the ARM documentation very very closely. It is not obvious but part of the learning exercise I want you to do for this lab is learn to read the ISA documentation closely.
Why PC + 8 or PC + 12? That will be explained in lecture. It has to do with pipelining (lab 3).
Do I have to start early? YES. This lab is very hard.
Is Feb 17th really the deadline? YES. We have another lab (lab 3) after this which is to pipeline your design. That will be harder.