Q1:
; Note: zero out high 48(x)/16(w) bits if LDUR used, STUR generally leads to some serious issues...
atoi(char*):
  cbz x0, .L7
  ldrb w1, [x0]
  cmp w1, 45
  bne .L3
  add x0, x0, 1
  mov w4, -1
  b .L4
.L3:
  cmp w1, 43
  bne .L8
  add x0, x0, 1
  mov w4, 1
  b .L4
.L8:
  mov w4, 1
.L4:
  mov w1, 0
.L6:
  ldrb w2, [x0]
  sub w3, w2, #48
  uxtb w3, w3
  cmp w3, 9
  bhi .L5
  lsl w3, w1, 3
  add w1, w3, w1, lsl 1
  add w1, w2, w1
  sub w1, w1, #48
  add x0, x0, 1
  b .L6
.L5:
  mul w0, w1, w4
  ret
.L7:
  mov w0, 0
  ret


Q2:
a) 1111 1111 1101 0011
b) 545
c) A[1 : 0], B[1 : 0] inputs, C carry, R[4 : 0] result
R0 = A0 & B0
R1 = A1 & B0 + A0 & B1 -> C1
R2 = A1 & B1 + C1 -> C2
R3 = C2


Q3:
module calc_block(READ_A, READ_B, WRITE_REG, WRITE_DATA, WRITE_ENABLE, READY, DATA_A, DATA_B, START, CLOCK);
    output reg[4:0] READ_A, READ_B, WRITE_REG;
    output reg[63:0] WRITE_DATA;
    output reg WRITE_ENABLE, READY;
    input[63:0] DATA_A, DATA_B;
    input START, CLOCK;

    reg[3:0] cases;
    parameter tile = 4;

    initial
    begin
        WRITE_ENABLE <= '0;
        READY <= '1;
        cases <= '0;
    end

    always@ (posedge CLOCK or posedge START)
    begin
        if (START)
        begin
            WRITE_ENABLE <= '0;
            READY <= '0;
            cases <= '0;
        end
        else
        begin
            case(cases)
                0:
                begin
                    READ_A <= 'd0;
                    READ_B <= 'd4;
                    WRITE_REG <= 'd8;
                    cases++;
                end
                1:
                begin
                    WRITE_DATA <= DATA_A * DATA_B;
                    cases++;
                end
                2:
                begin
                    WRITE_ENABLE <= '1;
                    cases++;
                end
                3:
                begin
                    WRITE_ENABLE <= '0;
                    cases++;
                end
                4:
                begin
                    if (READ_B < tile + 3) // 7
                    begin
                        READ_B <= READ_B + 1;
                        WRITE_REG <= WRITE_REG + 1;
                        cases <= '1;
                    end
                    else if (READ_A < tile - 1) // 3
                    begin
                        READ_A <= READ_A + 1;
                        READ_B <= 'd4;
                        WRITE_REG <= WRITE_REG + 1;
                        cases <= '1;
                    end
                    else
                    begin
                        READY <= '1;
                    end
                end
                default:
                begin
                    WRITE_ENABLE <= '0;
                    READY <= '1;
                end
            endcase
        end
    end
endmodule

Q4:
One viable solution is modify the mem so that it can be read and written at the same time (refer to HW4, SWAP).
[0/1(depends on modification)] [1, 1] [0, 0] [111] [0] [SrcDest1] [SrcDest2] [SrcDest1]