CSE467: Advanced Logic Design

Carl Ebeling, Winter 1999

List of topics and concepts covered this quarter:

• Truth tables and structured logic implementations
• PALs and PLAs implementation of functions
• Table lookup implementation of functions (PROM/LUT)
• Multiplexors for functions
• Decoders for functions
• Tristates for multiplexing and busses
• Synchronous circuit design methodologies
• Timing characteristics of registers: setup/hold constraints and propagation delays
• Effects of clock skew
• Asynchronous inputs, "synchronizers" and metastability problems
• Finite state machine models: Mealy vs. Moore machines
• State diagrams and compiling to state tables and circuit implementation
• PLD implementation of state machines
• FGPA architectures: logic blocks and routing structures
• FPGA design methodologies and CAD tools: place and route
• 2-level logic minimization
• Multi-output function minimization
• Multilevel logic synthesis
• Algebraic and boolean division, kernel and cube factors
• Logic transformations including factoring and Shannon decomposition
• State minimization
• State assignment techniques
• Memory structures and control
• Static RAM architecture and timing
• Dynamic RAM architecture and timing
• Serial communication
• Verilog description of digital systems
• Logic Analyzers