CSE467 Schedule

Lecture transparencies, handouts, lab assignments, and homework assignments.
 
Week Monday Wednesday Friday
Labs
1 09/27 Introduction 
Course overview		 09/29 Combinational-logic review 
  - Gates 
  - Minimization 
  - 2-level forms		 10/01 Combinational-logic review 
  - Muxes / demuxes 
  - Hazards 
  - Table lookup (ROMs)		 None
2 10/04  Fixed-function logic 
  - Logic families 
  - Data books 
Oscilloscopes 
  - Triggering, Probing		 10/06 Electrical realities 
  - R, C, & L 
  - Time constant 
  - Bandwidth 
  - Decoupling and ground
10/08
 Sequential-logic review 
  - Flip-flops 
  - Registers 
  - Counters 
Assignment 1 due		 Combinational lab 
  - Assembling a circuit 
  - Using supplies and meters 
  - Using oscilloscopes
3 10/11 Logic analyzers 
  - Capturing data 
  - Display and analysis 
  - Transient events		 10/13 State-machine review 
  - Moore vs Mealy 
  - Data path and control 
  - State diagrams 
  - State encoding
10/15
  FPGA Introduction 
  - Compared with PLDs 
  - Xilinx logic blocks 
Assignment 2 due 
Quiz #1		 Sequential lab 
  - Assembling a circuit 
  - Using logic analyzers 
  - Capturing/displaying data 
Lab #1 due
4 10/18  Xilinx Foundation Toolset 
  - Projects 
  - Schematic capture 
  - Simulation 
  - Place & route		 10/20 Electrical realities 
  - Delays, loading 
  - Metastability, skew 
  - Power 
  - FPGA I/O
10/22
 HDLs 
Verilog for combinational logic 
Assignment 3 due		 Xilinx implementation 
  - Designing with schematics 
  - FPGA mapping 
  - Test/debugging 
Lab #2 due
5 10/25 Verilog for sequential logic  10/27 Verilog FSMs 
Verilog design examples
10/29
 Verilog synthesis 
Assignment 4 due		  Xilinx implementation 
  - Designing with Verilog 
  - FPGA mapping 
  - Test/debugging 
Lab #3 due
6 11/01 Project description  11/03 Project discussion
11/05
 HW5 Discussion 
Quiz #2		 Xilinx/LCD interface 
  - Simple state machine 
First-half lab #4 due
7 11/08 Optimizing FSMs 
  - Output encoding 
  - FSM partitioning		 11/10 Pipelining 
Retiming 
Systolic arrays
11/12
 Guest lecture 
Multilevel logic		 Xilinx ant/maze miniproject 
  - Design, implementation 
  - Debug, test 
Final lab #4 due
8 11/15 Assignment 5 due 
Lab #5 due 
MOSFETs 		 11/17 Memories 
  - SRAM 
  - DRAM 
  - ROM 
11/19
 Adders 
Multipliers 		 Project lab
9 11/22 Electrical realities 
  - Impedance matching 
  - Ringing, reflections 
  - Terminations		 11/24 Advanced topics: 
  - PCB design 
  - Wiring issues 
  - Differential signaling
11/26
 Thanksgiving holiday Thanksgiving—no lab
10 11/29 Serial & parallel protocols 
Data communication		 12/01 Advanced topics: 
  - High-speed design 
  - High-speed test
12/03
 SW for logic minimization Projects due
 11 12/06  Advanced topics: 
  - A/D conversion 
  - D/A conversion 
Projects due		  12/08 Advanced Topics: 
  - Technology for reconfigurable wires 
Projects due		      Projects due

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