Reading an SRAM cell

• Reading is hard

  • Bit line capacitance is huge (CBL > 1pF)
    • SRAM cell can’t slew bit-line quickly
    • Can lose the cell’s contents

• Design peripheral circuitry to read reliably

  • Precharge bit lines lines to Vdd/2
  • Then release the precharge
    • Reduces chance of erroneous switching
  • Use sense amps for differential sensing
    • Detect small voltage change
    • Small swings ? low power

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