Addressing a memory
address(n+m bits)
decoder
multiplexer ( 2m :1)
memorycell array
2m k-bit words per row
n
m
2n rows
k bits wide (k bits/word)
2n by 2m*k bits
Want square memory array
Want simple decoding logic
Problem: A 1Meg×1 RAM uses 1,048,576 20-input NANDs?
Want short data & address lines
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