Week7, Lecture3: Multi-Level Logic Optimization
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Table of Contents
Multi-Level Logic Optimization
Multi-level Logic for FPGAs
Some Definitions
Representation of Factored Expressions
Transformations We Will Try
Factoring Boolean Expressions
Simple Factoring - Decomposition
Case Study
Algebraic vs. Boolean Division
Kernels and Cubes
Why Kernels?
Network Operations
Example to Illustrate Transformations
Example to Illustrate Transformations
Elimination
Decomposition (decomp)
Extraction (gkx - kernels, gcx - cubes)
Simplification (simplify)
Substitution (resub)
Tabular Method for Finding Kernels
Common-Cube Extraction
Restructuring Multi-Level Logic for Speed
Summary of Multi-Level Optimization
Technology Mapping
Mapping Circuit with a Library of Cells
Covering Problem
Technology Mapping by Tree Matching
Tree matching – example
Technology Mapping for LUT FPGAs
Author:
ebeling
Email:
diorio@cs.washington.edu
Home Page:
http://www.cs.washington.edu/education/courses/467/99au/