Formal algorithm for retiming
Represent circuit as a directed graph
- Vertices v: Logic gates
- Edges e: Connections between logic (0 or more registers)
- Delay d: Delay of vertex v
- Weight w: Number of registers on edge e
Problem statement
- Given cycle time t and the circuit graph
- Adjust weights w (number of registers) so that all path delays d < t
- Preserving logic functionality
Approach
- Generate matrices for w and d
- Iterate to minimize t (use linear programming)