Parameters cannot generate logic

module add_or_sub (a, b, op, c);

parameter width = 8;

parameter add = 1’b1;

input [width-1:0] a, b;

input op;

output [width-1:0] c;

assign c = (op == add) ? (a + b) : (a - b);

endmodule

constant-valued

non-constant-valued

This code won’t work

Can evaluate constant-valued expressions