Another way

module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter zero = 0, one1 = 1, two1s = 2; // states

reg [1:0] state; // state register assign out = reduce_output(state);

always @(posedge clk) if (reset) state = zero;

else state = next_state(in, state);

function reduce_output;

input [1:0] state;

case (state)

zero: reduce_output = 0; one1: reduce_output = 0; two1s: reduce_output = 1; default: reduce_output = 0;

endcase endfunction

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