Example: Moore machine
module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter zero = 0, one1 = 1, two1s = 2; // states
reg out; reg [1:0] state; // state register reg [1:0] next_state; // always block needs reg
// Implement the state register
always @(posedge clk) if (reset) state = zero; //can put in next state logic