for

// simple encoder

module encode (A, Y);

input [7:0] A; // 8-bit input vector

output [2:0] Y; // 3-bit encoded output

reg [2:0] Y; // target of assignment

integer i; // Temporary variables for program only

reg [7:0] test;

always @(A) begin

test = 8b’00000001;

Y = 3’bx;

for (i = 0; i < 8; i = i + 1) begin

if (A == test) Y = i;

test = test << 1; // Shift left, pad with 0s

end

end

endmodule

for statements synthesize as cascaded combinational logic

? Verilog unrolls the loop

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