casez and casex

// 2-bit priority encoder

module encode (A, Y);

input [7:0] A; // 8-bit input vector

output [1:0] Y; // 3-bit encoded output

reg [1:0] Y; // target of assignment

always @(A)

casez (A)

8’bzzzz0001: Y = 0;

8’bzzzz0010: Y = 1;

8’bzzzz0100: Y = 2;

8’bzzzz1000: Y = 3;

default: Y = 2’bx; // Don’t care when input isnt 1-hot

endcase

endmodule

casez: alternatives can include z

? z bits are not used in the evaluation