case: A better way

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signal

input A, B, C, D;

output Y;

assign out = mymux(sel, A, B, C, D);

function mymux;

input [1:0] sel, A, B, C, D;

begin

case (sel)

2’b00: mymux = A;

2’b01: mymux = B;

2’b10: mymux = C;

2’b11: mymux = D;

endcase

end

endfunction

endmodule

Note: You can define a function in a file

Then include it into your Verilog module